mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-19 08:32:33 +00:00
fae15847a3
Roll the encode/decode buffer-sizing helpers (added for x86 in 49787b7de) out
to every other ISA, and document them in the cross-arch naming contract.
Per arch (arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816):
- encode_max_code_size / encode_max_relocation_count now key off the
[]Instruction slice (were int counts); bodies unchanged (* MAX_INST_SIZE).
- encode_reserve(code, relocs, instructions): grows the caller's code []u8 by
length and reserves relocs by capacity; allocates no new buffers.
- decode_max_instruction_count / decode_estimate_instruction_count: exact
ceiling and typical estimate, keyed off the min/avg instruction size per
arch (fixed-4: arm64/mips/ppc/rsp; min-2: arm32/riscv/ppc_vle; min-1: mos).
- decode_reserve(instructions, inst_info, label_defs, data, exact=false).
docs/cross_arch_design.md: helpers added to the naming contract.
No behavior change to the existing size helpers (signature only). All 10 ISAs
check + test green (x86 2282, arm32 600, arm64 461, mips 281, riscv 154, ppc 31,
ppc_vle 281, rsp 70, mos6502 148, mos65816 53).
636 lines
20 KiB
Odin
636 lines
20 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mips
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// =============================================================================
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// MIPS ENCODER
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// =============================================================================
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//
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// Fixed-width 4-byte encoding pipeline. Table-driven (single source of truth:
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// ENCODING_TABLE) and zero-allocation on the hot path -- the caller owns
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// every output buffer.
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//
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// Two-pass design (parallel to the x86 encoder):
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//
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// PASS 1 - encode each instruction to a 32-bit word, write it to `code`
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// in the requested endianness, and record a pending Relocation
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// for every label-referencing operand (forward AND backward).
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//
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// PASS 1.5 - rewrite label_defs[i] from instruction-index to byte-offset.
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// For fixed-width MIPS this is a trivial multiply-by-4 sweep
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// which the compiler vectorises.
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//
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// PASS 2 - if `resolve == true`, walk the pending relocations and patch
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// every one whose target is now known. Patched entries are
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// dropped from `relocs`; unresolvable entries (forward-
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// referenced external symbols) remain for the linker.
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//
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// Hot-path style choices:
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//
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// - `encode_one_inline`, `encoding_matches_inline`, `operand_matches_inline`,
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// `pack_operand_inline` are `#force_inline` so the per-instruction body
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// collapses into one straight-line block with full register usage --
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// no procedure-call overhead between table lookup and word store.
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//
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// - The 4-operand loop in `encode_one_inline` is hand-unrolled, with a
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// NONE fast-path on each slot so the common (<=3-operand) instruction
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// short-circuits the tail.
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//
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// - Operand packing uses a switch that the compiler renders as a jump
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// table -- same throughput as a procedure-pointer table without the
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// extra indirection layer.
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//
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// - Word writes are byte-by-byte with constant shifts; the compiler
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// pattern-matches this to a single u32 store (plus a bswap on the
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// big-endian path) while keeping the alignment-agnostic []u8 API.
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// Largest instruction we ever emit (MIPS is fixed at 4).
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MAX_INST_SIZE :: 4
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// Upper bound on bytes emitted for `n` instructions.
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encode_max_code_size :: #force_inline proc "contextless" (instructions: []Instruction) -> int {
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return len(instructions) * MAX_INST_SIZE
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}
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// Upper bound on pending relocations for `n` instructions
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// (each instruction has at most one label-referencing operand).
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encode_max_relocation_count :: #force_inline proc "contextless" (instructions: []Instruction) -> int {
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return len(instructions)
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}
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// Pre-size the caller's encode outputs (code grown by length so code[:] is a
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// valid emit target; relocs reserved by capacity) so the encode hot path never
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// reallocates. Allocates no new buffers; pass nil to skip either array.
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encode_reserve :: proc(code: ^[dynamic]u8, relocs: ^[dynamic]Relocation, instructions: []Instruction) {
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if code != nil {
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size := encode_max_code_size(instructions)
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if len(code) < size {
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resize(code, size)
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}
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}
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if relocs != nil {
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reserve(relocs, len(relocs) + encode_max_relocation_count(instructions))
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}
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}
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// =============================================================================
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// encode()
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// =============================================================================
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encode :: proc(
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instructions: []Instruction,
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label_defs: []Label_Definition,
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code: []u8,
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relocs: ^[dynamic]Relocation,
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errors: ^[dynamic]Error,
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endianness: Endianness = .BIG,
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resolve: bool = true,
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base_address: u64 = 0,
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) -> (byte_count: u32, ok: bool) {
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n_inst := u32(len(instructions))
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if u32(len(code)) < n_inst * 4 {
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append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW})
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return
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}
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errors_start := u32(len(errors))
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pending_start := u32(len(relocs))
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// ---- PASS 1 ------------------------------------------------------------
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for i in 0..<n_inst {
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inst := &instructions[i]
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word := encode_one_inline(inst, byte_count, u16(i), relocs, errors) or_return
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write_u32(code, byte_count, word, endianness)
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byte_count += 4
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}
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// ---- PASS 1.5: rewrite label_defs from inst-idx to byte-offset --------
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// For fixed-width MIPS, byte_offset = inst_idx * 4.
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for &ld in label_defs {
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if ld != LABEL_UNDEFINED {
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ld = Label_Definition(u32(ld) * 4)
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}
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}
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if !resolve {
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ok = u32(len(errors)) == errors_start
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return
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}
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// ---- PASS 2: resolve relocations ---------------------------------------
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n_relocs := u32(len(relocs))
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write_idx := pending_start
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for read_idx in pending_start..<n_relocs {
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r := relocs[read_idx]
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if resolve_relocation_inline(code, label_defs, &r, endianness, base_address, errors) {
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continue // resolved & patched -> drop
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}
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// unresolved -> keep
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if write_idx != read_idx {
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relocs[write_idx] = r
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}
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write_idx += 1
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}
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if write_idx != n_relocs {
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resize(relocs, int(write_idx))
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}
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ok = u32(len(errors)) == errors_start
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return
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}
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// =============================================================================
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// Internal: encode one instruction into a 32-bit word
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// =============================================================================
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@(private="file")
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encode_one_inline :: #force_inline proc(
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inst: ^Instruction,
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pc: u32,
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inst_idx: u16,
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relocs: ^[dynamic]Relocation,
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errors: ^[dynamic]Error,
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) -> (word: u32, ok: bool) {
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if inst.mnemonic == .INVALID {
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append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC})
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return 0, false
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}
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forms := encoding_forms(inst.mnemonic)
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if len(forms) == 0 {
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append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC})
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return 0, false
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}
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// Find a matching form. Most mnemonics have exactly one.
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form: ^Encoding
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for &f in forms {
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if encoding_matches_inline(inst, &f) {
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form = &f
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break
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}
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}
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if form == nil {
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append(errors, Error{inst_idx = u32(inst_idx), code = .NO_MATCHING_ENCODING})
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return 0, false
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}
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word = form.bits
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// Pack the four operand slots. NONE-fast-path on each slot lets the
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// common case (<= 3 user operands) short-circuit the tail.
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if form.enc[0] != .NONE {
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word |= pack_operand_inline(&inst.ops[0], form.enc[0], pc, inst_idx, relocs)
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}
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if form.enc[1] != .NONE {
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word |= pack_operand_inline(&inst.ops[1], form.enc[1], pc, inst_idx, relocs)
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}
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if form.enc[2] != .NONE {
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word |= pack_operand_inline(&inst.ops[2], form.enc[2], pc, inst_idx, relocs)
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}
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if form.enc[3] != .NONE {
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word |= pack_operand_inline(&inst.ops[3], form.enc[3], pc, inst_idx, relocs)
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}
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return word, true
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}
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// -----------------------------------------------------------------------------
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// Operand-type matcher
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// -----------------------------------------------------------------------------
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@(private="file")
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encoding_matches_inline :: #force_inline proc "contextless" (
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inst: ^Instruction, form: ^Encoding,
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) -> bool {
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return operand_matches_inline(&inst.ops[0], form.ops[0]) &&
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operand_matches_inline(&inst.ops[1], form.ops[1]) &&
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operand_matches_inline(&inst.ops[2], form.ops[2]) &&
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operand_matches_inline(&inst.ops[3], form.ops[3])
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}
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@(private="file")
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operand_matches_inline :: #force_inline proc "contextless" (
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op: ^Operand, ot: Operand_Type,
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) -> bool {
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switch ot {
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case .NONE:
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return op.kind == .NONE
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case .GPR:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_GPR
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case .GPR_ZERO:
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return op.kind == .REGISTER && op.reg == ZERO
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case .FPR_S, .FPR_D, .FPR_W, .FPR_L, .FPR_PS:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_FPR
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case .FCR:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_FCR
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case .CP0_REG:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_CP0
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case .CP2_REG:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_CP2D
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case .CP2_CTRL:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_CP2C
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case .VFPU_S, .VFPU_P, .VFPU_T, .VFPU_Q, .VFPU_M_P, .VFPU_M_T, .VFPU_M_Q:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_VFPU
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case .MSA_VEC:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_MSA
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case .IMM5, .IMM16S, .IMM16U, .IMM20, .IMM26, .SEL, .FCC,
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.GTE_SF, .GTE_MX, .GTE_V, .GTE_CV, .GTE_LM:
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return op.kind == .IMMEDIATE
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case .REL16, .REL21, .REL26, .REL_J26, .REL19, .REL18:
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return op.kind == .RELATIVE
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case .MEM:
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return op.kind == .MEMORY
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}
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return false
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}
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// -----------------------------------------------------------------------------
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// Operand packer -- where each operand's bits land in the instruction word
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// -----------------------------------------------------------------------------
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@(private="file")
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pack_operand_inline :: #force_inline proc(
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op: ^Operand,
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enc: Operand_Encoding,
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pc: u32,
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inst_idx: u16,
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relocs: ^[dynamic]Relocation,
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) -> u32 {
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switch enc {
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case .NONE:
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return 0
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// Integer GPR slots (R-type / I-type rs/rt/rd).
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case .RS:
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return (u32(reg_hw(op.reg)) & 0x1F) << 21
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case .RT:
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return (u32(reg_hw(op.reg)) & 0x1F) << 16
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case .RD:
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return (u32(reg_hw(op.reg)) & 0x1F) << 11
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case .SHAMT:
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return (u32(op.immediate) & 0x1F) << 6
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// FPU register slots (COP1 FR-format; bit positions overlap RT/RD/SHAMT).
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case .FT:
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return (u32(reg_hw(op.reg)) & 0x1F) << 16
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case .FS:
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return (u32(reg_hw(op.reg)) & 0x1F) << 11
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case .FD:
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return (u32(reg_hw(op.reg)) & 0x1F) << 6
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// Immediates.
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case .IMM_16:
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return u32(op.immediate) & 0xFFFF
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case .IMM_5:
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return (u32(op.immediate) & 0x1F) << 6
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case .IMM_20:
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return (u32(op.immediate) & 0xFFFFF) << 6
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case .IMM_26:
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// J/JAL use this with a RELATIVE operand (label target).
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// SYSCALL/BREAK/SDBBP use IMM_20 instead, so IMM_26 with an
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// IMMEDIATE operand only occurs for hand-built region jumps.
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if op.kind == .RELATIVE {
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .J26, size = 4, inst_idx = inst_idx,
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})
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return 0
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}
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return u32(op.immediate) & 0x3FFFFFF
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// Memory: rs(base) at bits 25-21 + imm16(disp) at bits 15-0.
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case .OFFSET_BASE:
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return ((u32(reg_hw(op.mem.base)) & 0x1F) << 21) | (u32(op.mem.disp) & 0xFFFF)
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// PC-relative -- emit a relocation; pass 2 patches the immediate field.
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case .BRANCH_16:
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .REL16, size = 4, inst_idx = inst_idx,
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})
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return 0
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case .BRANCH_21:
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .REL21, size = 4, inst_idx = inst_idx,
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})
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return 0
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case .BRANCH_26:
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .REL26, size = 4, inst_idx = inst_idx,
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})
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return 0
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case .BRANCH_19:
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .REL_PC19, size = 4, inst_idx = inst_idx,
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})
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return 0
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case .BRANCH_18:
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .REL_PC18, size = 4, inst_idx = inst_idx,
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})
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return 0
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// FP condition-code field (BC1*, MOVF/MOVT, C.cond.fmt).
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case .FCC_BC:
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return (u32(op.immediate) & 0x7) << 18
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case .FCC_CC:
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return (u32(op.immediate) & 0x7) << 8
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// COP0 selector (R2+).
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case .SEL:
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return u32(op.immediate) & 0x7
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// Implicit operand -- bits already baked into form.bits.
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case .IMPL:
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return 0
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// GTE cofun sub-fields (bit positions within the 25-bit cofun field).
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case .GTE_SF_BIT:
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return (u32(op.immediate) & 0x1) << 19
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case .GTE_MX_BITS:
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return (u32(op.immediate) & 0x3) << 17
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case .GTE_V_BITS:
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return (u32(op.immediate) & 0x3) << 15
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case .GTE_CV_BITS:
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return (u32(op.immediate) & 0x3) << 13
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case .GTE_LM_BIT:
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return (u32(op.immediate) & 0x1) << 10
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// VFPU register slots: 7-bit register IDs.
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case .VFPU_VD:
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return (u32(reg_vfpu_hw(op.reg)) & 0x7F) << 0
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case .VFPU_VS:
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return (u32(reg_vfpu_hw(op.reg)) & 0x7F) << 8
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case .VFPU_VT:
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return (u32(reg_vfpu_hw(op.reg)) & 0x7F) << 16
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// VFPU memory-form register: 7-bit ID split as top-5 at bits 20:16
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// and low-2 at bits 1:0.
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case .VFPU_VT_MEM:
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hw := u32(reg_vfpu_hw(op.reg)) & 0x7F
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return ((hw >> 2) & 0x1F) << 16 | (hw & 0x3) << 0
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// VFPU SP-style memory: base GPR at 25:21 + 16-bit signed disp at 15:2.
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case .VFPU_OFFSET_BASE:
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base := (u32(reg_hw(op.mem.base)) & 0x1F) << 21
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// disp stored as bytes; bits 15:2 hold disp (low 2 forced to 0).
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return base | (u32(op.mem.disp) & 0xFFFC)
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// VFPU prefix 20-bit immediate at bits 19:0.
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case .VFPU_PFX:
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return u32(op.immediate) & 0xFFFFF
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// VFPU constant selector / 5-bit immediate at bits 20:16.
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case .VFPU_CONST:
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return (u32(op.immediate) & 0x1F) << 16
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// VFPU 4-bit condition code at bits 3:0.
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case .VFPU_COND4:
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return u32(op.immediate) & 0xF
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// VFPU 3-bit VCC selector at bits 18:16.
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case .VFPU_CC3:
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return (u32(op.immediate) & 0x7) << 18
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// MSA 3R-format register slots.
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case .WD:
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return (u32(reg_hw(op.reg)) & 0x1F) << 6
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case .WS:
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return (u32(reg_hw(op.reg)) & 0x1F) << 11
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case .WT:
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return (u32(reg_hw(op.reg)) & 0x1F) << 16
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// MSA immediates / displacements.
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case .MSA_I5:
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return (u32(op.immediate) & 0x1F) << 16
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case .MSA_S10:
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return (u32(op.immediate) & 0x3FF) << 16
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case .MSA_BIT5:
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return (u32(op.immediate) & 0x1F) << 11
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case .MSA_BIT_SHIFT, .MSA_ELM_IDX:
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// The marker (data format) is fixed in `bits`; the operand drives the
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// low bits of the shift/index field at bit 16.
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return (u32(op.immediate) & 0x3F) << 16
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case .MSA_I8:
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return (u32(op.immediate) & 0xFF) << 16
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case .FR:
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return (u32(reg_hw(op.reg)) & 0x1F) << 21
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case .GPR_AT_6:
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return (u32(reg_hw(op.reg)) & 0x1F) << 6
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case .GPR_AT_11:
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return (u32(reg_hw(op.reg)) & 0x1F) << 11
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case .DSP_SA:
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return (u32(op.immediate) & 0xF) << 21
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case .RS_RT:
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r := u32(reg_hw(op.reg)) & 0x1F
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return r << 21 | r << 16
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|
case .AC_NUM:
|
|
return (u32(op.immediate) & 0x3) << 11
|
|
case .SHILO_IMM:
|
|
return (u32(op.immediate) & 0x3F) << 20
|
|
case .EXT_SIZE:
|
|
return (u32(op.immediate) & 0x1F) << 21
|
|
|
|
// MSA memory operand: base GPR at 15:11, signed-10 disp at 25:16
|
|
// (caller has already scaled the displacement by element size).
|
|
case .MSA_OFFSET_BASE_B, .MSA_OFFSET_BASE_H, .MSA_OFFSET_BASE_W, .MSA_OFFSET_BASE_D:
|
|
shift: u32 = 0
|
|
#partial switch enc {
|
|
case .MSA_OFFSET_BASE_H: shift = 1
|
|
case .MSA_OFFSET_BASE_W: shift = 2
|
|
case .MSA_OFFSET_BASE_D: shift = 3
|
|
}
|
|
base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 11
|
|
imm_bits := ((u32(op.mem.disp) >> shift) & 0x3FF) << 16
|
|
return base_bits | imm_bits
|
|
}
|
|
return 0
|
|
}
|
|
|
|
// =============================================================================
|
|
// Pass 2 -- relocation resolver
|
|
// =============================================================================
|
|
|
|
@(private="file")
|
|
resolve_relocation_inline :: #force_inline proc(
|
|
code: []u8,
|
|
label_defs: []Label_Definition,
|
|
relocation: ^Relocation,
|
|
endianness: Endianness,
|
|
base_address: u64,
|
|
errors: ^[dynamic]Error,
|
|
) -> bool {
|
|
if int(relocation.label_id) >= len(label_defs) {
|
|
return false // bogus label id -- keep as unresolved (linker can fix)
|
|
}
|
|
ld := label_defs[relocation.label_id]
|
|
if ld == LABEL_UNDEFINED {
|
|
return false // not defined yet -- keep
|
|
}
|
|
target := u32(ld)
|
|
|
|
word := read_u32(code, relocation.offset, endianness)
|
|
|
|
switch relocation.type {
|
|
case .REL16:
|
|
rel := i32(target) - i32(relocation.offset) - 4
|
|
if rel & 3 != 0 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
rel >>= 2
|
|
if rel < -32768 || rel > 32767 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
word = (word &~ 0xFFFF) | (u32(rel) & 0xFFFF)
|
|
|
|
case .REL21:
|
|
rel := i32(target) - i32(relocation.offset) - 4
|
|
if rel & 3 != 0 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
rel >>= 2
|
|
if rel < -(1<<20) || rel > (1<<20)-1 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
word = (word &~ 0x1FFFFF) | (u32(rel) & 0x1FFFFF)
|
|
|
|
case .REL26:
|
|
rel := i32(target) - i32(relocation.offset) - 4
|
|
if rel & 3 != 0 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
rel >>= 2
|
|
if rel < -(1<<25) || rel > (1<<25)-1 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
word = (word &~ 0x3FFFFFF) | (u32(rel) & 0x3FFFFFF)
|
|
|
|
case .REL_PC19:
|
|
// R6 PC-relative load: offset is relative to the instruction's own
|
|
// address (no delay-slot adjustment), scaled by 4, 19-bit signed.
|
|
rel := i32(target) - i32(relocation.offset)
|
|
if rel & 3 != 0 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
rel >>= 2
|
|
if rel < -(1<<18) || rel > (1<<18)-1 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
word = (word &~ 0x7FFFF) | (u32(rel) & 0x7FFFF)
|
|
|
|
case .REL_PC18:
|
|
// LDPC: relative to the instruction's address aligned down to 8, scaled
|
|
// by 8, 18-bit signed.
|
|
rel := i32(target) - (i32(relocation.offset) &~ i32(7))
|
|
if rel & 7 != 0 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
rel >>= 3
|
|
if rel < -(1<<17) || rel > (1<<17)-1 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
word = (word &~ 0x3FFFF) | (u32(rel) & 0x3FFFF)
|
|
|
|
case .J26:
|
|
// J/JAL: target = ((PC+4)[31:28] << 28) | (encoded_field << 2)
|
|
if target & 3 != 0 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
target_abs := base_address + u64(target)
|
|
next_pc := base_address + u64(relocation.offset) + 4
|
|
if (u32(next_pc) >> 28) != (u32(target_abs) >> 28) {
|
|
// Region crossing -- J cannot reach a different 256MB region.
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
word = (word &~ 0x3FFFFFF) | (u32(target_abs >> 2) & 0x3FFFFFF)
|
|
|
|
case .NONE, .HI16, .LO16:
|
|
// %hi/%lo absolute pairs are not auto-resolved yet (the user
|
|
// supplies raw IMM_16 today; no syntactic %hi()/%lo()).
|
|
return false
|
|
}
|
|
|
|
write_u32(code, relocation.offset, word, endianness)
|
|
return true
|
|
}
|
|
|
|
// =============================================================================
|
|
// Endian-aware u32 read/write
|
|
// =============================================================================
|
|
//
|
|
// Byte-wise stores with constant shifts: the compiler folds these into one
|
|
// u32 store (and a bswap on the big-endian path for little-endian hosts),
|
|
// without requiring the []u8 output buffer to be 4-byte aligned.
|
|
|
|
write_u32 :: #force_inline proc "contextless" (
|
|
code: []u8, offset: u32, word: u32, endianness: Endianness,
|
|
) {
|
|
if endianness == .LITTLE {
|
|
code[offset+0] = u8(word)
|
|
code[offset+1] = u8(word >> 8)
|
|
code[offset+2] = u8(word >> 16)
|
|
code[offset+3] = u8(word >> 24)
|
|
} else {
|
|
code[offset+0] = u8(word >> 24)
|
|
code[offset+1] = u8(word >> 16)
|
|
code[offset+2] = u8(word >> 8)
|
|
code[offset+3] = u8(word)
|
|
}
|
|
}
|
|
|
|
read_u32 :: #force_inline proc "contextless" (
|
|
code: []u8, offset: u32, endianness: Endianness,
|
|
) -> u32 {
|
|
if endianness == .LITTLE {
|
|
return u32(code[offset+0]) |
|
|
(u32(code[offset+1]) << 8) |
|
|
(u32(code[offset+2]) << 16) |
|
|
(u32(code[offset+3]) << 24)
|
|
}
|
|
return (u32(code[offset+0]) << 24) |
|
|
(u32(code[offset+1]) << 16) |
|
|
(u32(code[offset+2]) << 8) |
|
|
u32(code[offset+3])
|
|
}
|
|
|
|
// =============================================================================
|
|
// Bulk endian conversion (callable separately for re-targeting an already-
|
|
// encoded buffer; uses a plain loop the compiler vectorises).
|
|
// =============================================================================
|
|
|
|
// In-place 32-bit byte-swap of `code`. Length must be a multiple of 4.
|
|
// Useful for switching a freshly-encoded buffer from native to wire endian
|
|
// when the consumer wants a single endian-conversion sweep after encoding.
|
|
swap_bytes_u32_inplace :: proc(code: []u8) {
|
|
n := len(code) / 4
|
|
for i in 0..<n {
|
|
off := i * 4
|
|
b0 := code[off+0]
|
|
b1 := code[off+1]
|
|
b2 := code[off+2]
|
|
b3 := code[off+3]
|
|
code[off+0] = b3
|
|
code[off+1] = b2
|
|
code[off+2] = b1
|
|
code[off+3] = b0
|
|
}
|
|
}
|