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95df04fbe1
Move all ten ISA packages (x86, arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816) from core/rexcode/<arch> to core/rexcode/isa/<arch>, so the import pattern is now `import "core:rexcode/isa/x86"`. The shared core stays at core:rexcode/isa. Mechanical: relative `import "../isa"` / "../../isa" -> absolute "core:rexcode/isa" (the only path that survives the move; the "../" and "../.." self/generated imports move with their packages). build.lua now builds paths as <root>/isa/<name>; stale `cd <arch>` hints in the verify tools and the doc.odin paths updated. WASM stays at core/rexcode/wasm for now -- it is an IR, not an ISA, and will move under the forthcoming core:rexcode/ir once that layer lands. All 10 arches gen/builders/check/test green; import core:rexcode/isa/x86 verified working; wasm still compiles.
125 lines
5.2 KiB
Odin
125 lines
5.2 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_ppc
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// =============================================================================
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// PowerPC INSTRUCTION
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// =============================================================================
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//
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// All PowerPC instructions are 4 bytes except Power ISA 3.1 prefixed (8 bytes).
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// `length` is derived by the encoder from the matched form's `bits` /
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// `flags.prefixed`. `mode` selects PPC32 vs PPC64 form filtering (some ops
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// gate on .P64 feature).
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Instruction_Flags :: bit_field u8 {
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sets_cr0: bool | 1, // Rc bit (record — writes CR0 from result)
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has_oe: bool | 1, // OE bit (overflow-enable, "o" suffix)
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aa: bool | 1, // absolute-address flag (branch AA bit)
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lk: bool | 1, // link bit (BL, BLR, BCL, BCCTRL etc.)
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_: u8 | 4,
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}
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Instruction :: struct #packed {
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ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 14 = 56
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mnemonic: Mnemonic, // 2
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operand_count: u8, // 0..4
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flags: Instruction_Flags, // 1
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mode: Mode, // 1 (PPC32 / PPC64)
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length: u8, // 4 or 8 (prefixed)
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form_id: u16, // 0 = no hint; otherwise 1 + form index
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}
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#assert(size_of(Instruction) == 64)
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// =============================================================================
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// Builders
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// =============================================================================
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@(require_results)
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inst_none :: #force_inline proc "contextless" (m: Mnemonic, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 0, length = 4, mode = mode}
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}
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@(require_results)
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inst_r :: #force_inline proc "contextless" (m: Mnemonic, r: Register, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 4, mode = mode,
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ops = {op_reg(r), {}, {}, {}}}
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}
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@(require_results)
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inst_i :: #force_inline proc "contextless" (m: Mnemonic, v: i64, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 4, mode = mode,
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ops = {op_imm(v), {}, {}, {}}}
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}
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@(require_results)
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inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, ra: Register, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4, mode = mode,
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ops = {op_reg(rd), op_reg(ra), {}, {}}}
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}
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@(require_results)
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inst_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, v: i64, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4, mode = mode,
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ops = {op_reg(rd), op_imm(v), {}, {}}}
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}
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@(require_results)
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inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, ra, rb: Register, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4, mode = mode,
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ops = {op_reg(rd), op_reg(ra), op_reg(rb), {}}}
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}
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@(require_results)
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inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd, ra: Register, v: i64, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4, mode = mode,
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ops = {op_reg(rd), op_reg(ra), op_imm(v), {}}}
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}
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@(require_results)
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inst_r_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, ra, rb, rc: Register, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 4, length = 4, mode = mode,
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ops = {op_reg(rd), op_reg(ra), op_reg(rb), op_reg(rc)}}
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}
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// Memory load/store: RT, [RA + disp] or [RA + RB].
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@(require_results)
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inst_load :: #force_inline proc "contextless" (m: Mnemonic, rt: Register, mm: Memory, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4, mode = mode,
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ops = {op_reg(rt), op_mem(mm), {}, {}}}
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}
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@(require_results)
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inst_store :: #force_inline proc "contextless" (m: Mnemonic, rs: Register, mm: Memory, mode: Mode = .PPC32) -> Instruction {
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return inst_load(m, rs, mm, mode)
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}
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// Branches with label resolution
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@(require_results)
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inst_branch :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 4, mode = mode,
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ops = {op_label(label_id), {}, {}, {}}}
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}
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// Conditional branch with BO/BI baked into the mnemonic (BEQ/BNE/...) + label
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@(require_results)
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inst_branch_cond :: #force_inline proc "contextless" (m: Mnemonic, crf: Register, label_id: u32, mode: Mode = .PPC32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4, mode = mode,
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ops = {op_reg(crf), op_label(label_id), {}, {}}}
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}
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// Flag setters
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@(require_results)
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inst_set_rc :: #force_inline proc "contextless" (inst: Instruction) -> Instruction {
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out := inst
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out.flags.sets_cr0 = true
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return out
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}
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@(require_results)
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inst_set_oe :: #force_inline proc "contextless" (inst: Instruction) -> Instruction {
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out := inst
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out.flags.has_oe = true
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return out
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}
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@(require_results)
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inst_set_lk :: #force_inline proc "contextless" (inst: Instruction) -> Instruction {
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out := inst
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out.flags.lk = true
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return out
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}
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