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5a9a7e9f49
Shrinking Instruction to 48 was the wrong call, and measuring it said so.
The premise was that a sub-cache-line struct touches fewer lines. It does --
but `#packed` aligns the struct to 1, so a 48-byte stride straddles a line
boundary 75% of the time, and the heap base is not line-aligned either. The
old 64-byte packed layout was worse still: 100% straddling, getting none of
the benefit its size implied.
Measured on an i7-9750H (L1d 32K/core, L2 256K, L3 12M), best-of-5, median of
3 interleaved rounds, against the 64-byte packed layout this branch started
from:
scan encode decode
64 packed (was) 1.000x 1.000x 1.000x
48 packed 0.909x 1.040x 1.022x
64 align(64) 1.218x 1.034x 0.806x
Decode is ~19% faster aligned, and that holds at every working set including
ones that fit entirely in L1 -- so it is split-store cost at the store ports,
not cache-line fetches. Decode writes whole Instructions, and the aligned
stores are worth more than the 33% extra bytes they move. A fourth variant --
48 bytes with `#packed` removed -- was measured to rule out the obvious
confound, and tracked 48-packed within 0.5% everywhere, so the win is
alignment and not the loss of packing.
Encode is within a few percent throughout (it is compute-bound; the form scan
dominates), and the pure read traversal is slower, but that is a synthetic
loop and its regression is codegen, not cache -- it is present even at
L1-resident sizes where a standalone struct shows no such penalty.
The Operand and Memory work from the previous commit is what makes this
possible: a 45/48-byte payload now sits inside one line with room to spare,
where the original spent all 64 bytes. The 16-19 spare bytes cost nothing over
a straddling 48-byte struct and give new fields somewhere to land.
All 11 rexcode suites match baseline; arm64 is 73/73 byte-exact against
llvm-mc; arm32's 1680/1680 sweep passes and its encode spot-checks are
unchanged.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
162 lines
7.3 KiB
Odin
162 lines
7.3 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm32
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// =============================================================================
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// AArch32 INSTRUCTION
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// =============================================================================
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//
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// Variable-length: A32 is always 4 bytes, T16 is 2 bytes, T32 is 4 bytes (two
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// halfwords). The `length` field is filled in by the encoder from the matched
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// Encoding entry's `bits` field via `inst_size_from_bits`.
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//
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// The `mode` field tells the encoder whether to dispatch to A32 or T32
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// encoding entries; for VFP/NEON entries the encoder applies bit-28 swap as
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// documented in encoding_types.odin.
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Instruction_Flags :: bit_field u8 {
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sets_flags: bool | 1, // S bit (writes APSR.NZCV)
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wide: bool | 1, // force T32 wide form when both T16 + T32 exist
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_: u8 | 6,
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}
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// Sized and aligned to a cache line -- see the note in arm64/instructions.odin.
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// The payload is 48 bytes; padding out to 64 and aligning is worth ~21% on
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// decode, because decode writes whole Instructions and unaligned stores are
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// expensive enough to outweigh writing more bytes.
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Instruction :: struct #align(64) {
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ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 10 = 40
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mnemonic: Mnemonic, // 2
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// cond, operand_count, mode, length and the two flag bits share one
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// 16-bit word -- together they need 13 bits, and spending six bytes on
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// them was what pushed Instruction over 48. `using` keeps inst.cond,
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// inst.operand_count, inst.mode, inst.length, inst.sets_flags and
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// inst.wide reading and writing exactly as they did as plain fields.
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using _: bit_field u16 {
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cond: u8 | 4, // 0..15 (AL = 14)
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operand_count: u8 | 3, // 0..4
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mode: Mode | 1, // A32 / T32
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length: u8 | 3, // 2 or 4 bytes on the wire
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sets_flags: bool | 1, // S bit (writes APSR.NZCV)
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wide: bool | 1, // force the T32 wide form when both exist
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// 3 bits spare
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},
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// Form-id hint: when non-zero, this is (1 + the index into
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// ENCODING_TABLE[mnemonic]) of the form the decoder produced. The encoder
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// uses it as a tie-breaker for the shape-ambiguous entries the data type
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// does not separate on its own -- register lists, LDM/STM addressing
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// modes. User-constructed instructions leave it at 0 and take the
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// first shape match.
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form_id: u16,
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// The `.i32` / `.s32.f32` suffix. Zero (.NONE) means "unspecified": the
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// encoder then takes the first form of the matching shape, which is what
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// every instruction did before this field existed. Set it and the encoder
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// picks the encoding for that type.
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dt: Data_Types,
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// Spare, and free: a 48-byte struct straddles a cache line, so these 16
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// bytes cost nothing. New fields land here without changing the layout.
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_: [16]u8,
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}
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#assert(size_of(Instruction) == 64)
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#assert(align_of(Instruction) == 64)
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// =============================================================================
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// Builders
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// =============================================================================
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@(require_results)
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inst_none :: #force_inline proc "contextless" (m: Mnemonic, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 0, length = mode == .A32 ? 4 : 2, mode = mode, cond = 14}
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}
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// 1-operand
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@(require_results)
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inst_r :: #force_inline proc "contextless" (m: Mnemonic, r: Register, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(r), {}, {}, {}}}
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}
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@(require_results)
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inst_i :: #force_inline proc "contextless" (m: Mnemonic, v: i64, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_imm(v), {}, {}, {}}}
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}
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// 2-operand
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@(require_results)
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inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rm: Register, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rm), {}, {}}}
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}
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@(require_results)
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inst_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, v: i64, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_imm(v), {}, {}}}
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}
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// 3-operand data-proc (ADD/SUB/AND/etc.)
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@(require_results)
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inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm: Register, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rn), op_reg(rm), {}}}
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}
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@(require_results)
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inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd, rn: Register, v: i64, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rn), op_imm(v), {}}}
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}
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@(require_results)
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inst_r_r_r_shifted :: #force_inline proc "contextless" (
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m: Mnemonic, rd, rn, rm: Register, st: Shift_Type, amt: u8, mode: Mode = .A32,
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) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rn), op_reg_shifted(rm, st, amt), {}}}
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}
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// 4-operand MLA / MLS / SMLAL etc.
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@(require_results)
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inst_r_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm, ra: Register, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 4, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_reg(rn), op_reg(rm), op_reg(ra)}}
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}
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// Memory load/store
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@(require_results)
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inst_load :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, mm: Memory, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(rd), op_mem(mm), {}, {}}}
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}
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@(require_results)
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inst_store :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, mm: Memory, mode: Mode = .A32) -> Instruction {
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return inst_load(m, rd, mm, mode)
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}
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// LDM/STM/PUSH/POP block move
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@(require_results)
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inst_block :: #force_inline proc "contextless" (m: Mnemonic, base: Register, mask: u16, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_reg(base), op_reg_list(mask), {}, {}}}
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}
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// Branches with label
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@(require_results)
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inst_branch :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32, mode: Mode = .A32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = mode == .A32 ? 4 : 4, mode = mode, cond = 14,
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ops = {op_label(label_id), {}, {}, {}}}
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}
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// Set condition code on any builder
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@(require_results)
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inst_set_cond :: #force_inline proc "contextless" (inst: Instruction, cond: u8) -> Instruction {
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out := inst
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out.cond = cond
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return out
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}
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// Set S flag (sets APSR.NZCV)
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@(require_results)
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inst_set_flags :: #force_inline proc "contextless" (inst: Instruction) -> Instruction {
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out := inst
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out.sets_flags = true
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return out
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}
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