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5cba6402f6
The arm64 pass turned up the same class of bug elsewhere: mnemonics named
after an encoding rather than after what an assembler accepts, and forms
that no caller can reach because the thing that tells them apart is not
checked.
mips
* The printer mapped every `_` to `.`, but MSA spells the sign qualifier
with an underscore and only the element size with a dot: `adds_s.b`,
`max_s.h`, `copy_u.w`. `adds.s.b` is rejected by an assembler. 91
mnemonics were printing text that would not reassemble. The name alone
cannot decide it -- MSA's ADDS_S_D and the FP convert CVT_S_D have the
same shape and want opposite treatment -- so the family is read off the
form's feature.
* `encode` now takes `features: Feature_Set = FEATURES_ALL` and skips
forms outside it, mirroring `decode`, which has had that parameter all
along. That asymmetry was the reason 12 mnemonics carried an ISA-variant
suffix: with no way to say which MIPS you were targeting, the pre-R6 and
R6 encodings of `mul` had to be two enum members. They are now one
mnemonic with two forms. Eight of the twelve did not even need the
feature filter -- pre-R6 MADD takes rs,rt while the PS2 MMI MADD takes
rd,rs,rt, so operand matching alone separates them. Verified against
llvm-mc: pre-R6 `mul` 712a4002, R6 `mul` 012a4098, `madd $t1,$t2`
712a0000. The printer's hand-written override table is gone.
arm32
* 20 `*_LANE` mnemonics folded into their base. The lane form differs from
the base in an operand TYPE already (DPR_ELEM vs DPR), so the matcher
could always tell them apart; the split only cost us the printed name,
which was the enum name verbatim -- `vqdmulh_lane`, which no assembler
takes. VMOV/VLD1-4/VST1-4 are left alone: their lane forms collide with
the base because register lists and lane indices are not modelled.
riscv
* ZEXT_H and REV8 each carry an RV32 and an RV64 encoding with identical
operands, and the forms were already tagged rv32_only / rv64_only -- the
encoder just never looked. `encode` now takes `xlen: XLEN = .RV64` and
filters, so the RV64 encodings are reachable at all: zext.h 0805c53b and
rev8 6b85d513, both confirmed against llvm-mc.
mos6502
* SAX_NMOS folded into SAX. The undocumented NMOS store-A&X and the
HuC6280 register swap share the mnemonic `sax`; one takes a memory
operand and the other takes none, so they are just two form sets.
Verified: every rexcode suite matches HEAD exactly, all 13 packages build,
and MIPS mnemonics llvm-mc does not recognise drop from 448 to 354.
Still open: arm32 has 201 form signatures no caller can select, because the
NEON data type (.i8/.i16/.f32) is not an operand -- `inst_vadd(d0,d1,d2)`
always yields the first form, and only a decoder-supplied form_id hint can
pick another. 38 arm32 mnemonics still carry encoding-shaped names
(VPADD_F, VCEQ_Z, VLDRB_GATHER, VMOV_Q_R, ...).
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
130 lines
4.5 KiB
Odin
130 lines
4.5 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mos6502
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// =============================================================================
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// MOS 6502 family mnemonics
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// =============================================================================
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//
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// Covers the four CPU tiers we target:
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// - NMOS official 6502 (56 mnemonics)
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// - NMOS undocumented opcodes (~24, widely used on NES & Apple II)
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// - 65C02 additions (Rockwell/WDC), incl. RMB/SMB/BBR/BBS bit ops
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// - HuC6280 (PC Engine) additions: block xfer, swap regs, MMR ops
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//
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// The undocumented NMOS SAX (store A&X) and the HuC6280 SAX (swap A,X)
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// share the assembler mnemonic `sax`. They are one Mnemonic with two sets
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// of forms: the NMOS one takes a memory operand and the HuC6280 one takes
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// none, so the operand shape alone picks the right encoding.
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Mnemonic :: enum u16 {
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INVALID = 0,
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// -------------------------------------------------------------------------
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// NMOS official
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// -------------------------------------------------------------------------
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// Arithmetic / logical
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ADC, AND, ASL,
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BIT,
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CMP, CPX, CPY,
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DEC, DEX, DEY,
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EOR,
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INC, INX, INY,
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LSR,
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ORA,
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ROL, ROR,
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SBC,
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// Branches
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BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS,
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// Jumps / subroutines / interrupts
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JMP, JSR, RTI, RTS,
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BRK,
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// Flag ops
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CLC, CLD, CLI, CLV,
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SEC, SED, SEI,
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// Loads / stores
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LDA, LDX, LDY,
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STA, STX, STY,
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// Stack / transfer
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PHA, PHP, PLA, PLP,
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TAX, TAY, TSX, TXA, TXS, TYA,
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// NOP
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NOP,
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// -------------------------------------------------------------------------
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// NMOS undocumented (common subset used on NES & Apple II)
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// -------------------------------------------------------------------------
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LAX, // LDA + LDX (load A and X from memory)
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DCP, // DEC + CMP (memory)
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ISC, // INC + SBC (also ISB)
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RLA, // ROL + AND
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RRA, // ROR + ADC
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SLO, // ASL + ORA
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SRE, // LSR + EOR
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ALR, // AND #imm + LSR A
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ANC, // AND #imm with carry from N
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ARR, // AND #imm + ROR A
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AXS, // X = (A AND X) - imm (also SBX)
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LAS, // LDA / TSX / AND with stack pointer
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ANE, // A = (A | $EE) AND X AND imm -- unstable (also XAA)
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LXA, // A = X = (A | $EE) AND imm -- unstable
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SHA, // store A AND X AND high+1
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SHX, // store X AND high+1
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SHY, // store Y AND high+1
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TAS, // S = A AND X; store S AND high+1
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JAM, // halt the CPU (also KIL / HLT)
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USBC, // same as SBC #imm but at $EB (an undocumented alias)
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DOP, // double NOP (skips one operand byte)
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TOP, // triple NOP (skips two operand bytes)
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// -------------------------------------------------------------------------
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// 65C02 additions (Rockwell + WDC)
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// -------------------------------------------------------------------------
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BRA, // branch always
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INA, // INC A
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DEA, // DEC A
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PHX, PHY,
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PLX, PLY,
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STZ, // store zero
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TRB, TSB, // test-and-reset / test-and-set bits
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STP, WAI, // WDC: stop, wait-for-interrupt
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// 65C02 Rockwell bit ops -- 32 distinct opcodes
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RMB0, RMB1, RMB2, RMB3, RMB4, RMB5, RMB6, RMB7,
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SMB0, SMB1, SMB2, SMB3, SMB4, SMB5, SMB6, SMB7,
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BBR0, BBR1, BBR2, BBR3, BBR4, BBR5, BBR6, BBR7,
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BBS0, BBS1, BBS2, BBS3, BBS4, BBS5, BBS6, BBS7,
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// -------------------------------------------------------------------------
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// HuC6280 (PC Engine / TurboGrafx-16)
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// -------------------------------------------------------------------------
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SXY, // swap X, Y
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SAX, // swap A,X (HuC6280) / store A AND X (NMOS undocumented)
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SAY, // swap A, Y
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CLA, CLX, CLY, // clear A / X / Y
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CSH, CSL, // CPU speed high / low (7.16 MHz vs 1.79 MHz)
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SET, // set T flag (next op uses zp address as accumulator)
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ST0, ST1, ST2, // store immediate to MMR0/1/2
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TAM, TMA, // transfer A to/from MMR (immediate-selected)
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TST, // bit test of immediate against memory
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BSR, // branch to subroutine (PC-relative)
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// HuC6280 block transfer instructions (7-byte encoding)
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// src(2) -> dst(2), len(2) bytes
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TII, // transfer increment-increment (memcpy ascending)
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TDD, // transfer decrement-decrement (memcpy descending)
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TIN, // transfer increment-no-change (fill from src)
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TIA, // transfer increment-alternate (interleaved)
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TAI, // transfer alternate-increment (interleaved)
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}
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