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https://github.com/odin-lang/Odin.git
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a63fb51fdd
Implement VMLSV/VMLSVA (MVE multiply-subtract reduce) properly: new VN_Q_MVE (Qn at 19:17) and VM_Q_MVE (Qm at 3:1) encodings -- the actual 3-bit MVE Q fields -- with Rd at 15:12 (RDLO_A32). The earlier collision was from reusing the 4-bit VN_Q (19:16) and RD_T32 (11:8), which place the fields wrong; byte-exact vs llvm-mc now with distinct Qn/Qm/Rd. Drop three placeholder/redundant enum entries: VRINT and VPRINT (not real instructions -- llvm rejects bare 'vrint'; VPRINT is a printf-like debug pseudo-op), and VRSHL_MVE (the author's own comment marks it a placeholder; 'vrshl q,q,q' already decodes via VRSHL's MVE form). 600 tests green, verify matches llvm-mc.
2696 lines
396 KiB
Odin
2696 lines
396 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm32
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// =============================================================================
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// GENERATED FILE - DO NOT EDIT
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// =============================================================================
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//
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// Generated by tools/gen_mnemonic_builders.odin from ENCODE_FORMS / ENCODE_RUNS.
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// Regenerate with: odin run arm32/tools/gen_mnemonic_builders.odin -file
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//
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// Typed mnemonic builder procedures with overloading. Each mnemonic with at
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// least one encode form exposes an inst_<mnem> overload set (returns
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// Instruction) and an emit_<mnem> overload set (appends to a
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// ^[dynamic]Instruction). EVERY operand type is mapped to typed parameters:
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// shifted / register-shifted registers (Register, Shift_Type, u8/Register),
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// register lists (u16 mask), NEON D/Q lane elems (Register, u8), and every
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// immediate subclass (modified-imm / barrier / endian / iflags / sysm / coproc
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// / saturating / PSR field / hint / condition-operand / MVE / CDE) as i64 — the
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// encoder performs the field packing. Forms whose ordered Odin parameter-type
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// tuple duplicates an earlier form of the same mnemonic are folded out to keep
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// each overload set unambiguous (all arm32 register classes share one Register
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// type).
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// =============================================================================
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// Individual Typed Builder Procedures
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// =============================================================================
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inst_and_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_and_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_and_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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inst_and_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_and_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_immm(dst, src, imm)) }
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emit_and_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_and_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_and_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_and_r_r_rsr(dst, src, src2, shift, rs)) }
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emit_and_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_and_rlo_rlo(dst, src)) }
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inst_eor_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_eor_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_eor_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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inst_eor_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_eor_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_immm(dst, src, imm)) }
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emit_eor_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_eor_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_eor_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_eor_r_r_rsr(dst, src, src2, shift, rs)) }
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emit_eor_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_eor_rlo_rlo(dst, src)) }
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inst_sub_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_sub_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_sub_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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inst_sub_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_sub_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_sub_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_immm(dst, src, imm)) }
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emit_sub_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_sub_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_sub_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_sub_r_r_rsr(dst, src, src2, shift, rs)) }
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emit_sub_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_rlo_rlo_rlo(dst, src, src2)) }
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emit_sub_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_sub_rlo_imm8(dst, imm)) }
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inst_rsb_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_rsb_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_rsb_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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emit_rsb_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rsb_r_r_immm(dst, src, imm)) }
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emit_rsb_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_rsb_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_rsb_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_rsb_r_r_rsr(dst, src, src2, shift, rs)) }
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inst_add_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_add_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_add_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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inst_add_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_add_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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inst_add_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_add_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_immm(dst, src, imm)) }
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emit_add_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_add_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_add_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_add_r_r_rsr(dst, src, src2, shift, rs)) }
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emit_add_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_rlo_rlo_rlo(dst, src, src2)) }
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emit_add_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_add_rlo_imm8(dst, imm)) }
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emit_add_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_add_r_r(dst, src)) }
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inst_adc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_adc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_adc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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inst_adc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_adc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adc_r_r_immm(dst, src, imm)) }
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emit_adc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_adc_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_adc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_adc_r_r_rsr(dst, src, src2, shift, rs)) }
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emit_adc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_adc_rlo_rlo(dst, src)) }
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inst_sbc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_sbc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_sbc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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inst_sbc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_sbc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sbc_r_r_immm(dst, src, imm)) }
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emit_sbc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_sbc_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_sbc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_sbc_r_r_rsr(dst, src, src2, shift, rs)) }
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emit_sbc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sbc_rlo_rlo(dst, src)) }
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inst_rsc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_rsc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_rsc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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emit_rsc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rsc_r_r_immm(dst, src, imm)) }
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emit_rsc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_rsc_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_rsc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_rsc_r_r_rsr(dst, src, src2, shift, rs)) }
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inst_tst_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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inst_tst_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} }
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inst_tst_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} }
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inst_tst_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tst_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_immm(dst, imm)) }
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emit_tst_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_tst_r_rsh(dst, src, shift, amount)) }
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emit_tst_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_tst_r_rsr(dst, src, shift, rs)) }
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emit_tst_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tst_rlo_rlo(dst, src)) }
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inst_teq_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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inst_teq_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} }
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inst_teq_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} }
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emit_teq_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_teq_r_immm(dst, imm)) }
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emit_teq_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_teq_r_rsh(dst, src, shift, amount)) }
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emit_teq_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_teq_r_rsr(dst, src, shift, rs)) }
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inst_cmp_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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inst_cmp_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} }
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inst_cmp_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} }
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inst_cmp_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cmp_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_r_immm(dst, imm)) }
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emit_cmp_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_cmp_r_rsh(dst, src, shift, amount)) }
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emit_cmp_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_cmp_r_rsr(dst, src, shift, rs)) }
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emit_cmp_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmp_rlo_rlo(dst, src)) }
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inst_cmn_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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inst_cmn_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} }
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inst_cmn_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} }
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inst_cmn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cmn_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_r_immm(dst, imm)) }
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emit_cmn_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_cmn_r_rsh(dst, src, shift, amount)) }
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emit_cmn_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_cmn_r_rsr(dst, src, shift, rs)) }
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emit_cmn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmn_rlo_rlo(dst, src)) }
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inst_orr_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_orr_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_orr_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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inst_orr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_orr_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_immm(dst, src, imm)) }
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emit_orr_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_orr_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_orr_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_orr_r_r_rsr(dst, src, src2, shift, rs)) }
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emit_orr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_orr_rlo_rlo(dst, src)) }
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inst_mov_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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inst_mov_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} }
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inst_mov_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} }
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inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mov_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_immm(dst, imm)) }
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emit_mov_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_mov_r_rsh(dst, src, shift, amount)) }
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emit_mov_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_mov_r_rsr(dst, src, shift, rs)) }
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emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) }
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inst_bic_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_bic_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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inst_bic_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} }
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inst_bic_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_bic_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bic_r_r_immm(dst, src, imm)) }
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emit_bic_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_bic_r_r_rsh(dst, src, src2, shift, amount)) }
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emit_bic_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_bic_r_r_rsr(dst, src, src2, shift, rs)) }
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emit_bic_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bic_rlo_rlo(dst, src)) }
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inst_mvn_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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inst_mvn_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} }
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inst_mvn_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} }
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inst_mvn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mvn_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvn_r_immm(dst, imm)) }
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emit_mvn_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_mvn_r_rsh(dst, src, shift, amount)) }
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emit_mvn_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_mvn_r_rsr(dst, src, shift, rs)) }
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emit_mvn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_rlo_rlo(dst, src)) }
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inst_lsl_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_lsl_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_lsl_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_imm5(dst, src, imm)) }
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emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) }
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emit_lsl_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsl_rlo_rlo(dst, src)) }
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inst_lsr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_lsr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_lsr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_imm5(dst, src, imm)) }
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emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) }
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emit_lsr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsr_rlo_rlo(dst, src)) }
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inst_asr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_asr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_asr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_r_r_imm5(dst, src, imm)) }
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emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) }
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emit_asr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_asr_rlo_rlo(dst, src)) }
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inst_ror_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_ror_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_ror_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ror_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_imm5(dst, src, imm)) }
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emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) }
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emit_ror_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ror_rlo_rlo(dst, src)) }
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inst_rrx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RRX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_rrx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rrx_r_r(dst, src)) }
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inst_adr_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} }
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emit_adr_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_adr_rlo_rel(dst, offset)) }
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inst_neg_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_neg_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_rlo_rlo(dst, src)) }
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inst_movw_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVW, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_movw_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movw_r_imm16(dst, imm)) }
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inst_movt_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_movt_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movt_r_imm16(dst, imm)) }
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inst_bfc_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_imm(imm2), {}}} }
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emit_bfc_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_bfc_r_imm5_imm5w(dst, imm, imm2)) }
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inst_bfi_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFI, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_bfi_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_bfi_r_r_imm5_imm5w(dst, src, imm, imm2)) }
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inst_sbfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_sbfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sbfx_r_r_imm5_imm5w(dst, src, imm, imm2)) }
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inst_ubfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_ubfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_ubfx_r_r_imm5_imm5w(dst, src, imm, imm2)) }
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inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) }
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inst_sxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_sxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb16_r_r(dst, src)) }
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inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) }
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inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) }
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inst_uxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_uxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb16_r_r(dst, src)) }
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inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) }
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inst_sxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab_r_r_r(dst, src, src2)) }
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inst_sxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab16_r_r_r(dst, src, src2)) }
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inst_sxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtah_r_r_r(dst, src, src2)) }
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inst_uxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab_r_r_r(dst, src, src2)) }
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inst_uxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab16_r_r_r(dst, src, src2)) }
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inst_uxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtah_r_r_r(dst, src, src2)) }
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inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) }
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inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) }
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inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) }
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inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) }
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inst_revsh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REVSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_revsh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_revsh_r_r(dst, src)) }
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inst_sel_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sel_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sel_r_r_r(dst, src, src2)) }
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inst_pkhbt_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .PKHBT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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emit_pkhbt_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_pkhbt_r_r_rsh(dst, src, src2, shift, amount)) }
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inst_pkhtb_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .PKHTB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} }
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emit_pkhtb_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_pkhtb_r_r_rsh(dst, src, src2, shift, amount)) }
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inst_usad8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_usad8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usad8_r_r_r(dst, src, src2)) }
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inst_usada8_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .USADA8, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_usada8_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_usada8_r_r_r_r(dst, src, src2, src3)) }
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inst_ssat_r_imm4s_rsh :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SSAT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg_shifted(src, shift, amount), {}}} }
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emit_ssat_r_imm4s_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_ssat_r_imm4s_rsh(dst, imm, src, shift, amount)) }
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inst_usat_r_imm4s_rsh :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .USAT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg_shifted(src, shift, amount), {}}} }
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emit_usat_r_imm4s_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_usat_r_imm4s_rsh(dst, imm, src, shift, amount)) }
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inst_ssat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .SSAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} }
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emit_ssat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ssat16_r_imm4s_r(dst, imm, src)) }
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inst_usat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .USAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} }
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emit_usat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_usat16_r_imm4s_r(dst, imm, src)) }
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inst_qadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd_r_r_r(dst, src, src2)) }
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inst_qsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub_r_r_r(dst, src, src2)) }
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inst_qdadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qdadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdadd_r_r_r(dst, src, src2)) }
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inst_qdsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qdsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdsub_r_r_r(dst, src, src2)) }
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inst_sadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd8_r_r_r(dst, src, src2)) }
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inst_sadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd16_r_r_r(dst, src, src2)) }
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inst_sasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sasx_r_r_r(dst, src, src2)) }
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inst_ssax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ssax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssax_r_r_r(dst, src, src2)) }
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inst_ssub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ssub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub8_r_r_r(dst, src, src2)) }
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inst_ssub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ssub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub16_r_r_r(dst, src, src2)) }
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inst_uadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd8_r_r_r(dst, src, src2)) }
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inst_uadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd16_r_r_r(dst, src, src2)) }
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inst_uasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uasx_r_r_r(dst, src, src2)) }
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inst_usax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_usax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usax_r_r_r(dst, src, src2)) }
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inst_usub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_usub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub8_r_r_r(dst, src, src2)) }
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inst_usub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_usub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub16_r_r_r(dst, src, src2)) }
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inst_qadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd8_r_r_r(dst, src, src2)) }
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inst_qadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd16_r_r_r(dst, src, src2)) }
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inst_qasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qasx_r_r_r(dst, src, src2)) }
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inst_qsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsax_r_r_r(dst, src, src2)) }
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inst_qsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub8_r_r_r(dst, src, src2)) }
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inst_qsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_qsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub16_r_r_r(dst, src, src2)) }
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inst_uqadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uqadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd8_r_r_r(dst, src, src2)) }
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inst_uqadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uqadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd16_r_r_r(dst, src, src2)) }
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inst_uqasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uqasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqasx_r_r_r(dst, src, src2)) }
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inst_uqsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uqsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsax_r_r_r(dst, src, src2)) }
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inst_uqsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uqsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub8_r_r_r(dst, src, src2)) }
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inst_uqsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uqsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub16_r_r_r(dst, src, src2)) }
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inst_shadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_shadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd8_r_r_r(dst, src, src2)) }
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inst_shadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_shadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd16_r_r_r(dst, src, src2)) }
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inst_shasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_shasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shasx_r_r_r(dst, src, src2)) }
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inst_shsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_shsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsax_r_r_r(dst, src, src2)) }
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inst_shsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_shsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub8_r_r_r(dst, src, src2)) }
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inst_shsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_shsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub16_r_r_r(dst, src, src2)) }
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inst_uhadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uhadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd8_r_r_r(dst, src, src2)) }
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inst_uhadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uhadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd16_r_r_r(dst, src, src2)) }
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inst_uhasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uhasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhasx_r_r_r(dst, src, src2)) }
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inst_uhsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uhsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsax_r_r_r(dst, src, src2)) }
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inst_uhsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uhsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub8_r_r_r(dst, src, src2)) }
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inst_uhsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_uhsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub16_r_r_r(dst, src, src2)) }
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inst_smuad_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUAD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smuad_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuad_r_r_r(dst, src, src2)) }
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inst_smuadx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUADX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smuadx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuadx_r_r_r(dst, src, src2)) }
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inst_smusd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smusd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusd_r_r_r(dst, src, src2)) }
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inst_smusdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSDX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smusdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusdx_r_r_r(dst, src, src2)) }
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inst_smlad_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlad_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlad_r_r_r_r(dst, src, src2, src3)) }
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inst_smladx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLADX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smladx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smladx_r_r_r_r(dst, src, src2, src3)) }
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inst_smlsd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlsd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsd_r_r_r_r(dst, src, src2, src3)) }
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inst_smlsdx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlsdx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsdx_r_r_r_r(dst, src, src2, src3)) }
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inst_smlald_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlald_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlald_r_r_r_r(dst, src, src2, src3)) }
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inst_smlaldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlaldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaldx_r_r_r_r(dst, src, src2, src3)) }
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inst_smlsld_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlsld_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsld_r_r_r_r(dst, src, src2, src3)) }
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inst_smlsldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlsldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsldx_r_r_r_r(dst, src, src2, src3)) }
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inst_smmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmul_r_r_r(dst, src, src2)) }
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inst_smmulr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMULR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smmulr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmulr_r_r_r(dst, src, src2)) }
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inst_smmla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smmla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmla_r_r_r_r(dst, src, src2, src3)) }
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inst_smmlar_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLAR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smmlar_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlar_r_r_r_r(dst, src, src2, src3)) }
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inst_smmls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smmls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmls_r_r_r_r(dst, src, src2, src3)) }
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inst_smmlsr_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLSR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smmlsr_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlsr_r_r_r_r(dst, src, src2, src3)) }
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inst_mul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_mul_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_r_r_r(dst, src, src2)) }
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emit_mul_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mul_rlo_rlo(dst, src)) }
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inst_mla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_mla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mla_r_r_r_r(dst, src, src2, src3)) }
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inst_mls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_mls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mls_r_r_r_r(dst, src, src2, src3)) }
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inst_umull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_umull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umull_r_r_r_r(dst, src, src2, src3)) }
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inst_umlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_umlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umlal_r_r_r_r(dst, src, src2, src3)) }
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inst_smull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smull_r_r_r_r(dst, src, src2, src3)) }
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inst_smlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlal_r_r_r_r(dst, src, src2, src3)) }
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inst_umaal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMAAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_umaal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaal_r_r_r_r(dst, src, src2, src3)) }
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inst_smlabb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlabb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabb_r_r_r_r(dst, src, src2, src3)) }
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inst_smlabt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlabt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabt_r_r_r_r(dst, src, src2, src3)) }
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inst_smlatb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlatb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatb_r_r_r_r(dst, src, src2, src3)) }
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inst_smlatt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlatt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatt_r_r_r_r(dst, src, src2, src3)) }
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inst_smlawb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlawb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawb_r_r_r_r(dst, src, src2, src3)) }
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inst_smlawt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlawt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawt_r_r_r_r(dst, src, src2, src3)) }
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inst_smulbb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smulbb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbb_r_r_r(dst, src, src2)) }
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inst_smulbt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smulbt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbt_r_r_r(dst, src, src2)) }
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inst_smultb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smultb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultb_r_r_r(dst, src, src2)) }
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inst_smultt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smultt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultt_r_r_r(dst, src, src2)) }
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inst_smulwb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smulwb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwb_r_r_r(dst, src, src2)) }
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inst_smulwt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_smulwt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwt_r_r_r(dst, src, src2)) }
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inst_smlalbb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlalbb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbb_r_r_r_r(dst, src, src2, src3)) }
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inst_smlalbt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlalbt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbt_r_r_r_r(dst, src, src2, src3)) }
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inst_smlaltb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlaltb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltb_r_r_r_r(dst, src, src2, src3)) }
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inst_smlaltt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_smlaltt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltt_r_r_r_r(dst, src, src2, src3)) }
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inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) }
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inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) }
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inst_b_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .B, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} }
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inst_b_rel_cond :: #force_inline proc "contextless" (offset: i64, imm: i64) -> Instruction { return Instruction{mnemonic = .B, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_rel_offset(offset), op_imm(imm), {}, {}}} }
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emit_b_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_b_rel(offset)) }
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emit_b_rel_cond :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, imm: i64) { append(instructions, inst_b_rel_cond(offset, imm)) }
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inst_bl_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BL, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} }
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emit_bl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_bl_rel(offset)) }
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inst_bx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bx_r(dst)) }
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inst_blx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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inst_blx_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} }
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emit_blx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blx_r(dst)) }
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emit_blx_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_blx_rel(offset)) }
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inst_bxj_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXJ, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bxj_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxj_r(dst)) }
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inst_cbz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} }
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emit_cbz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbz_rlo_rel(dst, offset)) }
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inst_cbnz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} }
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emit_cbnz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbnz_rlo_rel(dst, offset)) }
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inst_tbb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tbb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbb_r_r(dst, src)) }
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inst_tbh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tbh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbh_r_r(dst, src)) }
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inst_msr_psr_immm :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_imm(imm2), {}, {}}} }
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inst_msr_psr_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), {}, {}}} }
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emit_msr_psr_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_psr_immm(imm, imm2)) }
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emit_msr_psr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_msr_psr_r(imm, src)) }
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inst_mrs_r_psr :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_mrs_r_psr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mrs_r_psr(dst, imm)) }
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inst_cps_ifl :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .CPS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_cps_ifl :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_cps_ifl(imm)) }
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inst_setend_end :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SETEND, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_setend_end :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_setend_end(imm)) }
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inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .NOP, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) }
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inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .YIELD, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) }
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inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFE, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) }
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inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFI, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) }
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inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEV, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) }
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inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEVL, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) }
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inst_dbg_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DBG, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_dbg_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dbg_hint(imm)) }
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inst_hint_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_hint_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_hint(imm)) }
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inst_dmb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_dmb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_barr(imm)) }
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inst_dsb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_dsb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_barr(imm)) }
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inst_isb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_isb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_barr(imm)) }
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inst_clrex_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CLREX, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_clrex_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clrex_none()) }
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inst_pld_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLD, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} }
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emit_pld_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pld_mem(dst)) }
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inst_pldw_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLDW, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} }
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emit_pldw_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pldw_mem(dst)) }
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inst_pli_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLI, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} }
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emit_pli_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pli_mem(dst)) }
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inst_hlt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_hlt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_imm(imm)) }
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inst_dcps1_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPS1, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_dcps1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcps1_none()) }
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inst_dcps2_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPS2, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_dcps2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcps2_none()) }
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inst_dcps3_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPS3, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_dcps3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcps3_none()) }
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inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ERET, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) }
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inst_esb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ESB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_esb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_esb_none()) }
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inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) }
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inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) }
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inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CSDB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) }
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inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) }
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inst_setpan_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SETPAN, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_setpan_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_setpan_hint(imm)) }
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inst_svc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_svc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_imm(imm)) }
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inst_bkpt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BKPT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_bkpt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bkpt_imm(imm)) }
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inst_hvc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_hvc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_imm(imm)) }
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inst_smc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_smc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_imm(imm)) }
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inst_udf_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .UDF, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_udf_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_udf_imm(imm)) }
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inst_ldr_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldr_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldr_r_mem(dst, src)) }
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inst_str_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_str_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_str_r_mem(dst, src)) }
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inst_ldrb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrb_r_mem(dst, src)) }
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inst_strb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_strb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strb_r_mem(dst, src)) }
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inst_ldrh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrh_r_mem(dst, src)) }
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inst_strh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_strh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strh_r_mem(dst, src)) }
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inst_ldrsb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrsb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsb_r_mem(dst, src)) }
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inst_ldrsh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrsh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsh_r_mem(dst, src)) }
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inst_ldrd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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inst_ldrd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_ldrd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrd_r_mem(dst, src)) }
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emit_ldrd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrd_r_r_mem(dst, src, src2)) }
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inst_strd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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inst_strd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_strd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strd_r_mem(dst, src)) }
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emit_strd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strd_r_r_mem(dst, src, src2)) }
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inst_ldrt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrt_r_mem(dst, src)) }
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inst_strt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_strt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strt_r_mem(dst, src)) }
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inst_ldrbt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRBT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrbt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrbt_r_mem(dst, src)) }
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inst_strbt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRBT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_strbt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strbt_r_mem(dst, src)) }
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inst_ldrht_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRHT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrht_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrht_r_mem(dst, src)) }
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inst_strht_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRHT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_strht_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strht_r_mem(dst, src)) }
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inst_ldrsbt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSBT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrsbt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsbt_r_mem(dst, src)) }
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inst_ldrsht_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSHT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrsht_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsht_r_mem(dst, src)) }
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inst_lda_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_lda_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_lda_r_mem(dst, src)) }
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inst_stl_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_stl_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stl_r_mem(dst, src)) }
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inst_ldab_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldab_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldab_r_mem(dst, src)) }
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inst_stlb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_stlb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlb_r_mem(dst, src)) }
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inst_ldah_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldah_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldah_r_mem(dst, src)) }
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inst_stlh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_stlh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlh_r_mem(dst, src)) }
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inst_ldrex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrex_r_mem(dst, src)) }
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inst_strex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_strex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strex_r_r_mem(dst, src, src2)) }
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inst_ldrexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexb_r_mem(dst, src)) }
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inst_strexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_strexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexb_r_r_mem(dst, src, src2)) }
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inst_ldrexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldrexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexh_r_mem(dst, src)) }
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inst_strexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_strexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexh_r_r_mem(dst, src, src2)) }
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inst_ldrexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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inst_ldrexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_ldrexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexd_r_mem(dst, src)) }
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emit_ldrexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrexd_r_r_mem(dst, src, src2)) }
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inst_strexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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inst_strexd_r_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(src3)}} }
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emit_strexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexd_r_r_mem(dst, src, src2)) }
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emit_strexd_r_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Memory) { append(instructions, inst_strexd_r_r_r_mem(dst, src, src2, src3)) }
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inst_ldaex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldaex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaex_r_mem(dst, src)) }
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inst_stlex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_stlex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlex_r_r_mem(dst, src, src2)) }
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inst_ldaexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldaexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexb_r_mem(dst, src)) }
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inst_stlexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_stlexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexb_r_r_mem(dst, src, src2)) }
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inst_ldaexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldaexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexh_r_mem(dst, src)) }
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inst_stlexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_stlexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexh_r_r_mem(dst, src, src2)) }
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inst_ldaexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_ldaexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexd_r_mem(dst, src)) }
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inst_stlexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_stlexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexd_r_r_mem(dst, src, src2)) }
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inst_ldm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_ldm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldm_r_list(dst, regs)) }
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inst_stm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_stm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stm_r_list(dst, regs)) }
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inst_push_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .PUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} }
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emit_push_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_push_list(regs)) }
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inst_pop_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .POP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} }
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emit_pop_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_pop_list(regs)) }
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inst_swp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWP, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_swp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swp_r_r_r(dst, src, src2)) }
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inst_swpb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWPB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_swpb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swpb_r_r_r(dst, src, src2)) }
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inst_rfe_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_rfe_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfe_r(dst)) }
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inst_srs_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_srs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_srs_imm(imm)) }
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inst_cdp_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_cdp_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp_cpn_cpop_crd_crd(dst, imm, src, src2)) }
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inst_cdp2_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_cdp2_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp2_cpn_cpop_crd_crd(dst, imm, src, src2)) }
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inst_mcr_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_mcr_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcr_cpn_cpop_r_crd(dst, imm, src, src2)) }
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inst_mcr2_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCR2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_mcr2_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcr2_cpn_cpop_r_crd(dst, imm, src, src2)) }
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inst_mrc_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRC, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_mrc_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrc_cpn_cpop_r_crd(dst, imm, src, src2)) }
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inst_mrc2_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRC2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_mrc2_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrc2_cpn_cpop_r_crd(dst, imm, src, src2)) }
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inst_mcrr_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCRR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_mcrr_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcrr_cpn_cpop_r_r(dst, imm, src, src2)) }
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inst_mcrr2_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCRR2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_mcrr2_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcrr2_cpn_cpop_r_r(dst, imm, src, src2)) }
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inst_mrrc_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRRC, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_mrrc_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrrc_cpn_cpop_r_r(dst, imm, src, src2)) }
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inst_mrrc2_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRRC2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_mrrc2_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrrc2_cpn_cpop_r_r(dst, imm, src, src2)) }
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inst_ldc_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_ldc_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldc_cpn_crd_mem(dst, src, src2)) }
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inst_ldc2_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDC2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_ldc2_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldc2_cpn_crd_mem(dst, src, src2)) }
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inst_stc_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_stc_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stc_cpn_crd_mem(dst, src, src2)) }
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inst_stc2_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STC2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} }
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emit_stc2_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stc2_cpn_crd_mem(dst, src, src2)) }
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inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32B, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) }
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inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) }
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inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32W, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) }
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inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) }
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inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) }
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inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) }
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inst_vadd_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vadd_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadd_s_s_s(dst, src, src2)) }
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inst_vsub_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsub_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsub_s_s_s(dst, src, src2)) }
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inst_vmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmul_s_s_s(dst, src, src2)) }
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inst_vdiv_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdiv_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdiv_s_s_s(dst, src, src2)) }
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inst_vmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmla_s_s_s(dst, src, src2)) }
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inst_vmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmls_s_s_s(dst, src, src2)) }
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inst_vnmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vnmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmul_s_s_s(dst, src, src2)) }
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inst_vnmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vnmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmla_s_s_s(dst, src, src2)) }
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inst_vnmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vnmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmls_s_s_s(dst, src, src2)) }
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inst_vfma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_s_s_s(dst, src, src2)) }
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inst_vfms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfms_s_s_s(dst, src, src2)) }
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inst_vfnma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfnma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnma_s_s_s(dst, src, src2)) }
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inst_vfnms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfnms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnms_s_s_s(dst, src, src2)) }
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inst_vabs_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VABS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vabs_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vabs_s_s(dst, src)) }
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inst_vneg_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VNEG, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vneg_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vneg_s_s(dst, src)) }
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inst_vsqrt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSQRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vsqrt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vsqrt_s_s(dst, src)) }
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inst_vcmp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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inst_vcmp_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_vcmp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmp_s_s(dst, src)) }
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emit_vcmp_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmp_s(dst)) }
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inst_vcmpe_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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inst_vcmpe_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_vcmpe_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmpe_s_s(dst, src)) }
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emit_vcmpe_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmpe_s(dst)) }
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inst_vcvt_d_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcvt_d_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_d_s(dst, src)) }
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inst_vcvtb_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcvtb_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtb_s_s(dst, src)) }
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inst_vcvtt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcvtt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtt_s_s(dst, src)) }
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inst_vcvta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcvta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvta_s_s(dst, src)) }
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inst_vcvtn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcvtn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtn_s_s(dst, src)) }
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inst_vcvtp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcvtp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtp_s_s(dst, src)) }
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inst_vcvtm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcvtm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtm_s_s(dst, src)) }
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inst_vcvtr_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcvtr_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtr_s_s(dst, src)) }
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inst_vmov_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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inst_vmov_s_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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inst_vmov_r_r_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_vmov_r_r_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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inst_vmov_r_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} }
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inst_vmov_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} }
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emit_vmov_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmov_s_s(dst, src)) }
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emit_vmov_s_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmov_s_imm8(dst, imm)) }
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emit_vmov_r_r_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmov_r_r_d(dst, src, src2)) }
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emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmov_r_r_s_s(dst, src, src2, src3)) }
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emit_vmov_r_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_dlane(dst, src, lane)) }
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emit_vmov_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_dlane_r(dst, lane, src)) }
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inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) }
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inst_vmsr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMSR, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_vmsr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmsr_r(dst)) }
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inst_vldr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vldr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldr_s_mem(dst, src)) }
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inst_vstr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vstr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstr_s_mem(dst, src)) }
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inst_vldm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VLDM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_vldm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vldm_r_slist(dst, regs)) }
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inst_vstm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VSTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_vstm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vstm_r_slist(dst, regs)) }
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inst_vpush_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} }
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emit_vpush_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpush_slist(regs)) }
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inst_vpop_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPOP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} }
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emit_vpop_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpop_slist(regs)) }
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inst_vsel_s_s_s_cond :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSEL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vsel_s_s_s_cond :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vsel_s_s_s_cond(dst, src, src2, imm)) }
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inst_vmaxnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxnm_s_s_s(dst, src, src2)) }
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inst_vminnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminnm_s_s_s(dst, src, src2)) }
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inst_vrinta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrinta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrinta_s_s(dst, src)) }
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inst_vrintn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrintn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintn_s_s(dst, src)) }
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inst_vrintp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrintp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintp_s_s(dst, src)) }
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inst_vrintm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrintm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintm_s_s(dst, src)) }
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inst_vrintr_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrintr_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintr_s_s(dst, src)) }
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inst_vrintz_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrintz_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintz_s_s(dst, src)) }
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inst_vrintx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrintx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintx_s_s(dst, src)) }
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inst_vaddl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddl_q_d_d(dst, src, src2)) }
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inst_vaddw_q_q_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddw_q_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddw_q_q_d(dst, src, src2)) }
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inst_vsubl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubl_q_d_d(dst, src, src2)) }
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inst_vsubw_q_q_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubw_q_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubw_q_q_d(dst, src, src2)) }
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inst_vhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhadd_d_d_d(dst, src, src2)) }
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inst_vhsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vhsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhsub_d_d_d(dst, src, src2)) }
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inst_vrhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrhadd_d_d_d(dst, src, src2)) }
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inst_vqadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqadd_d_d_d(dst, src, src2)) }
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inst_vqsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqsub_d_d_d(dst, src, src2)) }
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inst_vmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmull_q_d_d(dst, src, src2)) }
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inst_vmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlal_q_d_d(dst, src, src2)) }
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inst_vmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsl_q_d_d(dst, src, src2)) }
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inst_vqdmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqdmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmull_q_d_d(dst, src, src2)) }
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inst_vqdmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqdmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlal_q_d_d(dst, src, src2)) }
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inst_vqdmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqdmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsl_q_d_d(dst, src, src2)) }
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inst_vqdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmulh_d_d_d(dst, src, src2)) }
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inst_vqrdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqrdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmulh_d_d_d(dst, src, src2)) }
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inst_vqdmulh_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vqdmulh_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmulh_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vqrdmulh_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMULH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vqrdmulh_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmulh_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vqrdmlah_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqrdmlah_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlah_d_d_d(dst, src, src2)) }
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inst_vqrdmlsh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqrdmlsh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsh_d_d_d(dst, src, src2)) }
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inst_vaba_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaba_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaba_d_d_d(dst, src, src2)) }
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inst_vabal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vabal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabal_q_d_d(dst, src, src2)) }
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inst_vabd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vabd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabd_d_d_d(dst, src, src2)) }
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inst_vabdl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABDL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vabdl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabdl_q_d_d(dst, src, src2)) }
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inst_vand_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vand_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vand_d_d_d(dst, src, src2)) }
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inst_vbic_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vbic_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbic_d_d_d(dst, src, src2)) }
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inst_vorr_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vorr_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorr_d_d_d(dst, src, src2)) }
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inst_vorn_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vorn_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorn_d_d_d(dst, src, src2)) }
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inst_veor_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_veor_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_veor_d_d_d(dst, src, src2)) }
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inst_vbsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vbsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbsl_d_d_d(dst, src, src2)) }
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inst_vbit_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vbit_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbit_d_d_d(dst, src, src2)) }
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inst_vbif_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIF, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vbif_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbif_d_d_d(dst, src, src2)) }
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inst_vmvn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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inst_vmvn_d_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_vmvn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmvn_d_d(dst, src)) }
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emit_vmvn_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmvn_d_imm(dst, imm)) }
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inst_vmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovn_d_q(dst, src)) }
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inst_vqmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vqmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovn_d_q(dst, src)) }
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inst_vqmovun_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vqmovun_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovun_d_q(dst, src)) }
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inst_vmovl_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmovl_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovl_q_d(dst, src)) }
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inst_vtst_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTST, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vtst_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtst_d_d_d(dst, src, src2)) }
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inst_vceq_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCEQ, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vceq_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vceq_d_d_d(dst, src, src2)) }
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inst_vcge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcge_d_d_d(dst, src, src2)) }
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inst_vcgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcgt_d_d_d(dst, src, src2)) }
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inst_vcle_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCLE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcle_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcle_d_d_d(dst, src, src2)) }
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inst_vclt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCLT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vclt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vclt_d_d_d(dst, src, src2)) }
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inst_vacge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vacge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacge_d_d_d(dst, src, src2)) }
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inst_vacgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vacgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacgt_d_d_d(dst, src, src2)) }
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inst_vacle_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACLE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vacle_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacle_d_d_d(dst, src, src2)) }
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inst_vaclt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACLT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaclt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaclt_d_d_d(dst, src, src2)) }
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inst_vmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmax_d_d_d(dst, src, src2)) }
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inst_vmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmin_d_d_d(dst, src, src2)) }
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inst_vpmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmax_d_d_d(dst, src, src2)) }
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inst_vpmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmin_d_d_d(dst, src, src2)) }
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inst_vpadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_d_d_d(dst, src, src2)) }
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inst_vpaddl_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADDL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vpaddl_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpaddl_d_d(dst, src)) }
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inst_vpadal_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADAL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vpadal_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpadal_d_d(dst, src)) }
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inst_vrecpe_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrecpe_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_d_d(dst, src)) }
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inst_vrecps_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRECPS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrecps_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrecps_d_d_d(dst, src, src2)) }
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inst_vrsqrte_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrsqrte_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_d_d(dst, src)) }
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inst_vrsqrts_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrsqrts_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrsqrts_d_d_d(dst, src, src2)) }
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inst_vshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vshl_d_d_d(dst, src, src2)) }
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inst_vshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshr_d_d_imm(dst, src, imm)) }
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inst_vsra_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vsra_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsra_d_d_imm(dst, src, imm)) }
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inst_vrshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrshl_d_d_d(dst, src, src2)) }
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inst_vrshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vrshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshr_d_d_imm(dst, src, imm)) }
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inst_vrsra_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSRA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vrsra_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrsra_d_d_imm(dst, src, imm)) }
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inst_vsli_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSLI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vsli_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsli_d_d_imm(dst, src, imm)) }
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inst_vsri_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vsri_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsri_d_d_imm(dst, src, imm)) }
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inst_vqshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_vqshl_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqshl_d_d_d(dst, src, src2)) }
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emit_vqshl_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshl_d_d_imm(dst, src, imm)) }
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inst_vqshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrn_d_q_imm(dst, src, imm)) }
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inst_vqshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrun_d_q_imm(dst, src, imm)) }
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inst_vqrshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqrshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrshl_d_d_d(dst, src, src2)) }
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inst_vqrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrn_d_q_imm(dst, src, imm)) }
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inst_vqrshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqrshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrun_d_q_imm(dst, src, imm)) }
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inst_vshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrn_d_q_imm(dst, src, imm)) }
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inst_vrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrn_d_q_imm(dst, src, imm)) }
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inst_vshll_q_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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inst_vshll_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vshll_q_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshll_q_d_imm(dst, src, imm)) }
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emit_vshll_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vshll_q_d(dst, src)) }
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inst_vcls_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcls_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcls_d_d(dst, src)) }
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inst_vclz_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vclz_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclz_d_d(dst, src)) }
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inst_vcnt_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCNT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcnt_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcnt_d_d(dst, src)) }
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inst_vpadd_f_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD_F, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpadd_f_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_f_d_d_d(dst, src, src2)) }
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inst_vrecpe_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrecpe_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_f_d_d(dst, src)) }
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inst_vrsqrte_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrsqrte_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_f_d_d(dst, src)) }
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inst_vrev16_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrev16_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev16_d_d(dst, src)) }
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inst_vrev32_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV32, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrev32_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev32_d_d(dst, src)) }
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inst_vrev64_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV64, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrev64_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev64_d_d(dst, src)) }
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inst_vext_d_d_d_imm4 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vext_d_d_d_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vext_d_d_d_imm4(dst, src, src2, imm)) }
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inst_vtbl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_vtbl_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} }
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emit_vtbl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbl_d_d_d(dst, src, src2)) }
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emit_vtbl_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbl_d_dlist_d(dst, regs, src)) }
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inst_vtbx_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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inst_vtbx_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} }
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emit_vtbx_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbx_d_d_d(dst, src, src2)) }
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emit_vtbx_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbx_d_dlist_d(dst, regs, src)) }
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inst_vtrn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VTRN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vtrn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vtrn_d_d(dst, src)) }
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inst_vuzp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUZP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vuzp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vuzp_d_d(dst, src)) }
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inst_vzip_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VZIP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vzip_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vzip_d_d(dst, src)) }
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inst_vdup_d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VDUP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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inst_vdup_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VDUP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} }
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emit_vdup_d_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vdup_d_r(dst, src)) }
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emit_vdup_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vdup_d_dlane(dst, src, lane)) }
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inst_vswp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSWP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vswp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vswp_d_d(dst, src)) }
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inst_vmov_lane_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} }
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emit_vmov_lane_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_lane_dlane_r(dst, lane, src)) }
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inst_vld1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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inst_vld1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} }
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emit_vld1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld1_dlist_mem(regs, src)) }
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emit_vld1_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_dlane_mem(dst, lane, src)) }
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inst_vld2_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld2_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_dlist_mem(regs, src)) }
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inst_vld3_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld3_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_dlist_mem(regs, src)) }
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inst_vld4_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld4_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_dlist_mem(regs, src)) }
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inst_vst1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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inst_vst1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} }
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emit_vst1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst1_dlist_mem(regs, src)) }
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emit_vst1_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_dlane_mem(dst, lane, src)) }
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inst_vst2_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst2_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_dlist_mem(regs, src)) }
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inst_vst3_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst3_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_dlist_mem(regs, src)) }
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inst_vst4_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst4_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_dlist_mem(regs, src)) }
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inst_aese_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_aese_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_q_q(dst, src)) }
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inst_aesd_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_aesd_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_q_q(dst, src)) }
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inst_aesmc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_aesmc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_q_q(dst, src)) }
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inst_aesimc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_aesimc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_q_q(dst, src)) }
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inst_sha1h_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1H, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_sha1h_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_q_q(dst, src)) }
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inst_sha1su0_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sha1su0_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_q_q_q(dst, src, src2)) }
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inst_sha1su1_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_sha1su1_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_q_q(dst, src)) }
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inst_sha1c_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sha1c_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_q_q_q(dst, src, src2)) }
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inst_sha1m_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sha1m_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_q_q_q(dst, src, src2)) }
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inst_sha1p_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sha1p_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_q_q_q(dst, src, src2)) }
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inst_sha256h_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sha256h_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_q_q_q(dst, src, src2)) }
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inst_sha256h2_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sha256h2_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_q_q_q(dst, src, src2)) }
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inst_sha256su0_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_sha256su0_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_q_q(dst, src)) }
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inst_sha256su1_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sha256su1_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_q_q_q(dst, src, src2)) }
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inst_vjcvt_s_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VJCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vjcvt_s_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vjcvt_s_d(dst, src)) }
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inst_vsdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsdot_d_d_d(dst, src, src2)) }
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inst_vudot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vudot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vudot_d_d_d(dst, src, src2)) }
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inst_vsdot_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vsdot_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsdot_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vudot_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vudot_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vudot_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vcvt_bf16_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT_BF16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcvt_bf16_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_bf16_d_q(dst, src)) }
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inst_vdot_bf16_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDOT_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdot_bf16_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdot_bf16_d_d_d(dst, src, src2)) }
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inst_vfma_bf16_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfma_bf16_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_bf16_q_q_q(dst, src, src2)) }
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inst_vmmla_bf16_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMMLA_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmmla_bf16_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmmla_bf16_q_q_q(dst, src, src2)) }
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inst_vfmal_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfmal_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmal_d_d_d(dst, src, src2)) }
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inst_vfmsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfmsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmsl_d_d_d(dst, src, src2)) }
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inst_vcmla_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vcmla_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcmla_d_d_d_imm(dst, src, src2, imm)) }
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inst_vcadd_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCADD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vcadd_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcadd_d_d_d_imm(dst, src, src2, imm)) }
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inst_vcmla_lane_d_d_dlane_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA_LANE, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), op_imm(imm)}} }
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emit_vcmla_lane_d_d_dlane_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8, imm: i64) { append(instructions, inst_vcmla_lane_d_d_dlane_imm(dst, src, src2, lane, imm)) }
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inst_vsmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsmmla_q_q_q(dst, src, src2)) }
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inst_vummla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vummla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vummla_q_q_q(dst, src, src2)) }
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inst_vusmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vusmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusmmla_q_q_q(dst, src, src2)) }
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inst_vsudot_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsudot_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsudot_q_q_q(dst, src, src2)) }
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inst_vusdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vusdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusdot_d_d_d(dst, src, src2)) }
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inst_vsudot_lane_q_q_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSUDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vsudot_lane_q_q_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsudot_lane_q_q_dlane(dst, src, src2, lane)) }
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inst_vusdot_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUSDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vusdot_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vusdot_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vmul_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMUL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vmul_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmul_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vmla_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLA_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vmla_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmla_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vmls_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLS_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vmls_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmls_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vmull_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMULL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vmull_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmull_lane_q_d_dlane(dst, src, src2, lane)) }
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inst_vmlal_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLAL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vmlal_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlal_lane_q_d_dlane(dst, src, src2, lane)) }
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inst_vmlsl_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLSL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vmlsl_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlsl_lane_q_d_dlane(dst, src, src2, lane)) }
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inst_vqdmull_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vqdmull_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmull_lane_q_d_dlane(dst, src, src2, lane)) }
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inst_vqdmlal_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLAL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vqdmlal_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlal_lane_q_d_dlane(dst, src, src2, lane)) }
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inst_vqdmlsl_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLSL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vqdmlsl_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlsl_lane_q_d_dlane(dst, src, src2, lane)) }
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inst_vfma_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMA_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vfma_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfma_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vfms_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMS_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vfms_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfms_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vqrdmlah_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLAH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vqrdmlah_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlah_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vqrdmlsh_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLSH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
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emit_vqrdmlsh_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlsh_lane_d_d_dlane(dst, src, src2, lane)) }
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inst_vqabs_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQABS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vqabs_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqabs_q_q(dst, src)) }
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inst_vqneg_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQNEG, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vqneg_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqneg_q_q(dst, src)) }
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inst_vmovx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmovx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovx_s_s(dst, src)) }
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inst_vins_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VINS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vins_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vins_s_s(dst, src)) }
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inst_vldrb_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRB_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} }
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emit_vldrb_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrb_gather_q_mem_q(dst, src, src2)) }
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inst_vldrh_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRH_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} }
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emit_vldrh_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrh_gather_q_mem_q(dst, src, src2)) }
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inst_vldrw_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRW_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} }
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emit_vldrw_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrw_gather_q_mem_q(dst, src, src2)) }
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inst_vldrd_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRD_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} }
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emit_vldrd_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrd_gather_q_mem_q(dst, src, src2)) }
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inst_vstrb_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRB_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} }
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emit_vstrb_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrb_scatter_q_mem_q(dst, src, src2)) }
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inst_vstrh_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRH_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} }
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emit_vstrh_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrh_scatter_q_mem_q(dst, src, src2)) }
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inst_vstrw_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRW_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} }
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emit_vstrw_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrw_scatter_q_mem_q(dst, src, src2)) }
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inst_vstrd_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRD_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} }
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emit_vstrd_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrd_scatter_q_mem_q(dst, src, src2)) }
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inst_vceq_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCEQ_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vceq_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vceq_z_d_d(dst, src)) }
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inst_vcge_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGE_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcge_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcge_z_d_d(dst, src)) }
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inst_vcgt_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGT_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcgt_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcgt_z_d_d(dst, src)) }
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inst_vcle_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLE_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcle_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcle_z_d_d(dst, src)) }
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inst_vclt_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLT_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vclt_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclt_z_d_d(dst, src)) }
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inst_vld2r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld2r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2r_dlist_mem(regs, src)) }
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inst_vld3r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld3r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3r_dlist_mem(regs, src)) }
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inst_vld4r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld4r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4r_dlist_mem(regs, src)) }
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inst_vld1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} }
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emit_vld1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_lane_dlane_mem(dst, lane, src)) }
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inst_vld2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_lane_dlist_mem(regs, src)) }
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inst_vld3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_lane_dlist_mem(regs, src)) }
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inst_vld4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_lane_dlist_mem(regs, src)) }
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inst_vst1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} }
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emit_vst1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_lane_dlane_mem(dst, lane, src)) }
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inst_vst2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_lane_dlist_mem(regs, src)) }
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inst_vst3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_lane_dlist_mem(regs, src)) }
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inst_vst4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_lane_dlist_mem(regs, src)) }
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inst_vcvt_fixed_s_s_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCVT_FIXED, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vcvt_fixed_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcvt_fixed_s_s_imm(dst, src, imm)) }
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inst_it_cond_imm4 :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .IT, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_imm(imm), op_imm(imm2), {}, {}}} }
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emit_it_cond_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_it_cond_imm4(imm, imm2)) }
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inst_tt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tt_r_r(dst, src)) }
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inst_ttt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ttt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttt_r_r(dst, src)) }
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inst_tta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tta_r_r(dst, src)) }
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inst_ttat_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTAT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ttat_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttat_r_r(dst, src)) }
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inst_sg_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SG, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_sg_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sg_none()) }
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inst_bxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxns_r(dst)) }
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inst_blxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} }
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emit_blxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blxns_r(dst)) }
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inst_pac_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PAC, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_pac_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pac_none()) }
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inst_pacbti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PACBTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_pacbti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacbti_none()) }
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inst_aut_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .AUT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_aut_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_aut_none()) }
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inst_autg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AUTG, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_autg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_autg_r_r_r(dst, src, src2)) }
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inst_bti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_none()) }
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inst_wls_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} }
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emit_wls_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wls_r_rel(dst, offset)) }
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inst_wlstp_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLSTP, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} }
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emit_wlstp_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wlstp_r_rel(dst, offset)) }
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inst_dls_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLS, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_dls_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dls_r(dst)) }
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inst_dlstp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLSTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_dlstp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dlstp_r(dst)) }
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inst_le_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LE, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} }
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emit_le_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_le_rel(offset)) }
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inst_letp_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LETP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} }
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emit_letp_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_letp_rel(offset)) }
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inst_lctp_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .LCTP, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_lctp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lctp_none()) }
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inst_cx1_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} }
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emit_cx1_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1_cp_r_imm(imm, src, imm2)) }
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inst_cx1a_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} }
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emit_cx1a_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1a_cp_r_imm(imm, src, imm2)) }
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inst_cx1d_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1D, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} }
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emit_cx1d_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1d_cp_r_imm(imm, src, imm2)) }
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inst_cx1da_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1DA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} }
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emit_cx1da_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1da_cp_r_imm(imm, src, imm2)) }
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inst_cx2_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} }
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emit_cx2_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2_cp_r_r_imm(imm, src, src2, imm2)) }
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inst_cx2a_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} }
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emit_cx2a_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2a_cp_r_r_imm(imm, src, src2, imm2)) }
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inst_cx2d_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2D, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} }
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emit_cx2d_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2d_cp_r_r_imm(imm, src, src2, imm2)) }
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inst_cx2da_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2DA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} }
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emit_cx2da_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2da_cp_r_r_imm(imm, src, src2, imm2)) }
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inst_cx3_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_cx3_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3_cp_r_r_r(imm, src, src2, src3)) }
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inst_cx3a_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_cx3a_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3a_cp_r_r_r(imm, src, src2, src3)) }
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inst_cx3d_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3D, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_cx3d_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3d_cp_r_r_r(imm, src, src2, src3)) }
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inst_cx3da_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3DA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_cx3da_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3da_cp_r_r_r(imm, src, src2, src3)) }
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inst_vcx1_cp_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} }
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emit_vcx1_cp_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_vcx1_cp_s_imm(imm, src, imm2)) }
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inst_vcx1a_cp_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} }
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emit_vcx1a_cp_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_vcx1a_cp_s_imm(imm, src, imm2)) }
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inst_vcx2_cp_s_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX2, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} }
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emit_vcx2_cp_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_vcx2_cp_s_s_imm(imm, src, src2, imm2)) }
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inst_vcx2a_cp_s_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX2A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} }
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emit_vcx2a_cp_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_vcx2a_cp_s_s_imm(imm, src, src2, imm2)) }
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inst_vcx3_cp_s_s_s :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VCX3, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vcx3_cp_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_vcx3_cp_s_s_s(imm, src, src2, src3)) }
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inst_vcx3a_cp_s_s_s :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VCX3A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vcx3a_cp_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_vcx3a_cp_s_s_s(imm, src, src2, src3)) }
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inst_vpt_vpt_cond_q_q :: #force_inline proc "contextless" (imm: i64, imm2: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPT, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_imm(imm2), op_reg(src), op_reg(src2)}} }
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emit_vpt_vpt_cond_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64, src: Register, src2: Register) { append(instructions, inst_vpt_vpt_cond_q_q(imm, imm2, src, src2)) }
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inst_vpst_vpt :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .VPST, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_vpst_vpt :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_vpst_vpt(imm)) }
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inst_vpsel_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPSEL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpsel_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpsel_q_q_q(dst, src, src2)) }
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inst_vpnot_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .VPNOT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} }
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emit_vpnot_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vpnot_none()) }
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inst_vctp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_vctp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vctp_r(dst)) }
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inst_vaddv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vaddv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddv_r_q(dst, src)) }
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inst_vaddva_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDVA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vaddva_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddva_r_q(dst, src)) }
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inst_vaddlv_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddlv_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlv_r_r_q(dst, src, src2)) }
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inst_vaddlva_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddlva_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlva_r_r_q(dst, src, src2)) }
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inst_vmaxv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmaxv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxv_r_q(dst, src)) }
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inst_vmaxav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmaxav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxav_r_q(dst, src)) }
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inst_vminv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vminv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminv_r_q(dst, src)) }
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inst_vminav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vminav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminav_r_q(dst, src)) }
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inst_vmaxnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmaxnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmv_r_q(dst, src)) }
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inst_vmaxnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmaxnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmav_r_q(dst, src)) }
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inst_vminnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vminnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmv_r_q(dst, src)) }
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inst_vminnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vminnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmav_r_q(dst, src)) }
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inst_vabav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vabav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabav_r_q_q(dst, src, src2)) }
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inst_vmladav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmladav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladav_r_q_q(dst, src, src2)) }
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inst_vmladava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmladava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladava_r_q_q(dst, src, src2)) }
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inst_vmladavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmladavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavx_r_q_q(dst, src, src2)) }
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inst_vmladavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmladavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavax_r_q_q(dst, src, src2)) }
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inst_vmlaldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmlaldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldav_r_r_q_q(dst, src, src2, src3)) }
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inst_vmlaldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmlaldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldava_r_r_q_q(dst, src, src2, src3)) }
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inst_vmlaldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmlaldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavx_r_r_q_q(dst, src, src2, src3)) }
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inst_vmlaldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmlaldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavax_r_r_q_q(dst, src, src2, src3)) }
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inst_vmlsdav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlsdav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdav_r_q_q(dst, src, src2)) }
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inst_vmlsdava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlsdava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdava_r_q_q(dst, src, src2)) }
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inst_vmlsdavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlsdavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavx_r_q_q(dst, src, src2)) }
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inst_vmlsdavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlsdavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavax_r_q_q(dst, src, src2)) }
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inst_vmlsldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmlsldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldav_r_r_q_q(dst, src, src2, src3)) }
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inst_vmlsldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmlsldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldava_r_r_q_q(dst, src, src2, src3)) }
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inst_vmlsldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmlsldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavx_r_r_q_q(dst, src, src2, src3)) }
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inst_vmlsldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmlsldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavax_r_r_q_q(dst, src, src2, src3)) }
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inst_vrmlaldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vrmlaldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavh_r_r_q_q(dst, src, src2, src3)) }
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inst_vrmlaldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vrmlaldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavha_r_r_q_q(dst, src, src2, src3)) }
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inst_vrmlaldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vrmlaldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhx_r_r_q_q(dst, src, src2, src3)) }
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inst_vrmlaldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vrmlaldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhax_r_r_q_q(dst, src, src2, src3)) }
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inst_vrmlsldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vrmlsldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavh_r_r_q_q(dst, src, src2, src3)) }
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inst_vrmlsldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vrmlsldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavha_r_r_q_q(dst, src, src2, src3)) }
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inst_vrmlsldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vrmlsldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhx_r_r_q_q(dst, src, src2, src3)) }
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inst_vrmlsldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vrmlsldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhax_r_r_q_q(dst, src, src2, src3)) }
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inst_vmlav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlav_r_q_q(dst, src, src2)) }
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inst_vmlava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlava_r_q_q(dst, src, src2)) }
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inst_vmlsv_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlsv_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsv_r_q_q(dst, src, src2)) }
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inst_vmlsva_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlsva_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsva_r_q_q(dst, src, src2)) }
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inst_vcmul_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMUL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmul_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmul_q_q_q(dst, src, src2)) }
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inst_vhcadd_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHCADD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vhcadd_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhcadd_q_q_q(dst, src, src2)) }
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inst_vbrsr_q_q_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBRSR, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vbrsr_q_q_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbrsr_q_q_r(dst, src, src2)) }
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inst_vshlc_q_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLC, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vshlc_q_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshlc_q_r_imm5(dst, src, imm)) }
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inst_vddup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vddup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vddup_q_r_imm(dst, src, imm)) }
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inst_vidup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vidup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vidup_q_r_imm(dst, src, imm)) }
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inst_vdwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vdwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vdwdup_q_r_r_imm(dst, src, src2, imm)) }
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inst_viwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_viwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_viwdup_q_r_r_imm(dst, src, src2, imm)) }
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inst_vmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnb_q_q(dst, src)) }
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inst_vmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnt_q_q(dst, src)) }
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inst_vqmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vqmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnb_q_q(dst, src)) }
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inst_vqmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vqmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnt_q_q(dst, src)) }
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inst_vqmovunb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vqmovunb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunb_q_q(dst, src)) }
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inst_vqmovunt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vqmovunt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunt_q_q(dst, src)) }
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inst_vshllb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vshllb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllb_q_q_imm5(dst, src, imm)) }
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inst_vshllt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vshllt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllt_q_q_imm5(dst, src, imm)) }
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inst_vmullb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmullb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullb_q_q_q(dst, src, src2)) }
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inst_vmullt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmullt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullt_q_q_q(dst, src, src2)) }
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inst_vmlalb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlalb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalb_q_q_q(dst, src, src2)) }
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inst_vmlalt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlalt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalt_q_q_q(dst, src, src2)) }
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inst_vmlslb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlslb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslb_q_q_q(dst, src, src2)) }
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inst_vmlslt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmlslt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslt_q_q_q(dst, src, src2)) }
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inst_vshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnb_q_q_imm5(dst, src, imm)) }
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inst_vshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnt_q_q_imm5(dst, src, imm)) }
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inst_vrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnb_q_q_imm5(dst, src, imm)) }
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inst_vrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnt_q_q_imm5(dst, src, imm)) }
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inst_vqshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnb_q_q_imm5(dst, src, imm)) }
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inst_vqshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnt_q_q_imm5(dst, src, imm)) }
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inst_vqrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnb_q_q_imm5(dst, src, imm)) }
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inst_vqrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnt_q_q_imm5(dst, src, imm)) }
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inst_vqshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunb_q_q_imm5(dst, src, imm)) }
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inst_vqshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunt_q_q_imm5(dst, src, imm)) }
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inst_vqrshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqrshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunb_q_q_imm5(dst, src, imm)) }
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inst_vqrshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vqrshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunt_q_q_imm5(dst, src, imm)) }
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inst_vmov_q_r_qlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_Q_R, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_reg(src), {}, {}}} }
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emit_vmov_q_r_qlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_q_r_qlane_r(dst, lane, src)) }
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inst_vmov_r_q_r_qlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV_R_Q, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_qpr_lane(src, lane), {}, {}}} }
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emit_vmov_r_q_r_qlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_q_r_qlane(dst, src, lane)) }
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inst_vmov_2gpr_q_qlane_qlane_r_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV_2GPR_Q, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_qpr_lane(src, lane2), op_reg(src2), op_reg(src3)}} }
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emit_vmov_2gpr_q_qlane_qlane_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) { append(instructions, inst_vmov_2gpr_q_qlane_qlane_r_r(dst, lane, src, lane2, src2, src3)) }
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inst_vqdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladh_q_q_q(dst, src, src2)) }
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inst_vqdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladhx_q_q_q(dst, src, src2)) }
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inst_vqdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdh_q_q_q(dst, src, src2)) }
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inst_vqdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdhx_q_q_q(dst, src, src2)) }
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inst_vqrdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqrdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladh_q_q_q(dst, src, src2)) }
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inst_vqrdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqrdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladhx_q_q_q(dst, src, src2)) }
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inst_vqrdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqrdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdh_q_q_q(dst, src, src2)) }
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inst_vqrdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vqrdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdhx_q_q_q(dst, src, src2)) }
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inst_vhcadd_sat_q_q_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VHCADD_SAT, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vhcadd_sat_q_q_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vhcadd_sat_q_q_q_imm(dst, src, src2, imm)) }
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inst_vcmla_mve_q_q_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA_MVE, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vcmla_mve_q_q_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcmla_mve_q_q_q_imm(dst, src, src2, imm)) }
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inst_vldrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vldrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrb_q_mem(dst, src)) }
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inst_vldrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vldrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrh_q_mem(dst, src)) }
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inst_vldrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vldrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrw_q_mem(dst, src)) }
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inst_vldrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vldrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrd_q_mem(dst, src)) }
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inst_vstrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vstrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrb_q_mem(dst, src)) }
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inst_vstrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vstrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrh_q_mem(dst, src)) }
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inst_vstrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vstrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrw_q_mem(dst, src)) }
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inst_vstrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vstrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrd_q_mem(dst, src)) }
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inst_vld20_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD20, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld20_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld20_qlist_mem(regs, src)) }
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inst_vld21_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD21, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld21_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld21_qlist_mem(regs, src)) }
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inst_vld40_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD40, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld40_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld40_qlist_mem(regs, src)) }
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inst_vld41_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD41, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld41_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld41_qlist_mem(regs, src)) }
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inst_vld42_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD42, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld42_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld42_qlist_mem(regs, src)) }
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inst_vld43_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD43, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld43_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld43_qlist_mem(regs, src)) }
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inst_vst20_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST20, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst20_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst20_qlist_mem(regs, src)) }
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inst_vst21_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST21, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst21_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst21_qlist_mem(regs, src)) }
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inst_vst40_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST40, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst40_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst40_qlist_mem(regs, src)) }
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inst_vst41_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST41, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vst41_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst41_qlist_mem(regs, src)) }
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inst_vst42_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST42, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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|
emit_vst42_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst42_qlist_mem(regs, src)) }
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|
inst_vst43_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST43, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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|
emit_vst43_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst43_qlist_mem(regs, src)) }
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|
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// =============================================================================
|
|
// Overload Groups
|
|
// =============================================================================
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|
|
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inst_and :: proc{ inst_and_r_r_immm, inst_and_r_r_rsh, inst_and_r_r_rsr, inst_and_rlo_rlo }
|
|
emit_and :: proc{ emit_and_r_r_immm, emit_and_r_r_rsh, emit_and_r_r_rsr, emit_and_rlo_rlo }
|
|
inst_eor :: proc{ inst_eor_r_r_immm, inst_eor_r_r_rsh, inst_eor_r_r_rsr, inst_eor_rlo_rlo }
|
|
emit_eor :: proc{ emit_eor_r_r_immm, emit_eor_r_r_rsh, emit_eor_r_r_rsr, emit_eor_rlo_rlo }
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inst_sub :: proc{ inst_sub_r_r_immm, inst_sub_r_r_rsh, inst_sub_r_r_rsr, inst_sub_rlo_rlo_rlo, inst_sub_rlo_imm8 }
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|
emit_sub :: proc{ emit_sub_r_r_immm, emit_sub_r_r_rsh, emit_sub_r_r_rsr, emit_sub_rlo_rlo_rlo, emit_sub_rlo_imm8 }
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|
inst_rsb :: proc{ inst_rsb_r_r_immm, inst_rsb_r_r_rsh, inst_rsb_r_r_rsr }
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|
emit_rsb :: proc{ emit_rsb_r_r_immm, emit_rsb_r_r_rsh, emit_rsb_r_r_rsr }
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|
inst_add :: proc{ inst_add_r_r_immm, inst_add_r_r_rsh, inst_add_r_r_rsr, inst_add_rlo_rlo_rlo, inst_add_rlo_imm8, inst_add_r_r }
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|
emit_add :: proc{ emit_add_r_r_immm, emit_add_r_r_rsh, emit_add_r_r_rsr, emit_add_rlo_rlo_rlo, emit_add_rlo_imm8, emit_add_r_r }
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inst_adc :: proc{ inst_adc_r_r_immm, inst_adc_r_r_rsh, inst_adc_r_r_rsr, inst_adc_rlo_rlo }
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emit_adc :: proc{ emit_adc_r_r_immm, emit_adc_r_r_rsh, emit_adc_r_r_rsr, emit_adc_rlo_rlo }
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inst_sbc :: proc{ inst_sbc_r_r_immm, inst_sbc_r_r_rsh, inst_sbc_r_r_rsr, inst_sbc_rlo_rlo }
|
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emit_sbc :: proc{ emit_sbc_r_r_immm, emit_sbc_r_r_rsh, emit_sbc_r_r_rsr, emit_sbc_rlo_rlo }
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inst_rsc :: proc{ inst_rsc_r_r_immm, inst_rsc_r_r_rsh, inst_rsc_r_r_rsr }
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emit_rsc :: proc{ emit_rsc_r_r_immm, emit_rsc_r_r_rsh, emit_rsc_r_r_rsr }
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inst_tst :: proc{ inst_tst_r_immm, inst_tst_r_rsh, inst_tst_r_rsr, inst_tst_rlo_rlo }
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emit_tst :: proc{ emit_tst_r_immm, emit_tst_r_rsh, emit_tst_r_rsr, emit_tst_rlo_rlo }
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inst_teq :: proc{ inst_teq_r_immm, inst_teq_r_rsh, inst_teq_r_rsr }
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emit_teq :: proc{ emit_teq_r_immm, emit_teq_r_rsh, emit_teq_r_rsr }
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inst_cmp :: proc{ inst_cmp_r_immm, inst_cmp_r_rsh, inst_cmp_r_rsr, inst_cmp_rlo_rlo }
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emit_cmp :: proc{ emit_cmp_r_immm, emit_cmp_r_rsh, emit_cmp_r_rsr, emit_cmp_rlo_rlo }
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inst_cmn :: proc{ inst_cmn_r_immm, inst_cmn_r_rsh, inst_cmn_r_rsr, inst_cmn_rlo_rlo }
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emit_cmn :: proc{ emit_cmn_r_immm, emit_cmn_r_rsh, emit_cmn_r_rsr, emit_cmn_rlo_rlo }
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inst_orr :: proc{ inst_orr_r_r_immm, inst_orr_r_r_rsh, inst_orr_r_r_rsr, inst_orr_rlo_rlo }
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emit_orr :: proc{ emit_orr_r_r_immm, emit_orr_r_r_rsh, emit_orr_r_r_rsr, emit_orr_rlo_rlo }
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inst_mov :: proc{ inst_mov_r_immm, inst_mov_r_rsh, inst_mov_r_rsr, inst_mov_r_r }
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emit_mov :: proc{ emit_mov_r_immm, emit_mov_r_rsh, emit_mov_r_rsr, emit_mov_r_r }
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inst_bic :: proc{ inst_bic_r_r_immm, inst_bic_r_r_rsh, inst_bic_r_r_rsr, inst_bic_rlo_rlo }
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emit_bic :: proc{ emit_bic_r_r_immm, emit_bic_r_r_rsh, emit_bic_r_r_rsr, emit_bic_rlo_rlo }
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inst_mvn :: proc{ inst_mvn_r_immm, inst_mvn_r_rsh, inst_mvn_r_rsr, inst_mvn_rlo_rlo }
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emit_mvn :: proc{ emit_mvn_r_immm, emit_mvn_r_rsh, emit_mvn_r_rsr, emit_mvn_rlo_rlo }
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|
inst_lsl :: proc{ inst_lsl_r_r_imm5, inst_lsl_r_r_r, inst_lsl_rlo_rlo }
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|
emit_lsl :: proc{ emit_lsl_r_r_imm5, emit_lsl_r_r_r, emit_lsl_rlo_rlo }
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inst_lsr :: proc{ inst_lsr_r_r_imm5, inst_lsr_r_r_r, inst_lsr_rlo_rlo }
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emit_lsr :: proc{ emit_lsr_r_r_imm5, emit_lsr_r_r_r, emit_lsr_rlo_rlo }
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|
inst_asr :: proc{ inst_asr_r_r_imm5, inst_asr_r_r_r, inst_asr_rlo_rlo }
|
|
emit_asr :: proc{ emit_asr_r_r_imm5, emit_asr_r_r_r, emit_asr_rlo_rlo }
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|
inst_ror :: proc{ inst_ror_r_r_imm5, inst_ror_r_r_r, inst_ror_rlo_rlo }
|
|
emit_ror :: proc{ emit_ror_r_r_imm5, emit_ror_r_r_r, emit_ror_rlo_rlo }
|
|
inst_rrx :: inst_rrx_r_r
|
|
emit_rrx :: emit_rrx_r_r
|
|
inst_adr :: inst_adr_rlo_rel
|
|
emit_adr :: emit_adr_rlo_rel
|
|
inst_neg :: inst_neg_rlo_rlo
|
|
emit_neg :: emit_neg_rlo_rlo
|
|
inst_movw :: inst_movw_r_imm16
|
|
emit_movw :: emit_movw_r_imm16
|
|
inst_movt :: inst_movt_r_imm16
|
|
emit_movt :: emit_movt_r_imm16
|
|
inst_bfc :: inst_bfc_r_imm5_imm5w
|
|
emit_bfc :: emit_bfc_r_imm5_imm5w
|
|
inst_bfi :: inst_bfi_r_r_imm5_imm5w
|
|
emit_bfi :: emit_bfi_r_r_imm5_imm5w
|
|
inst_sbfx :: inst_sbfx_r_r_imm5_imm5w
|
|
emit_sbfx :: emit_sbfx_r_r_imm5_imm5w
|
|
inst_ubfx :: inst_ubfx_r_r_imm5_imm5w
|
|
emit_ubfx :: emit_ubfx_r_r_imm5_imm5w
|
|
inst_sxtb :: inst_sxtb_r_r
|
|
emit_sxtb :: emit_sxtb_r_r
|
|
inst_sxtb16 :: inst_sxtb16_r_r
|
|
emit_sxtb16 :: emit_sxtb16_r_r
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|
inst_sxth :: inst_sxth_r_r
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|
emit_sxth :: emit_sxth_r_r
|
|
inst_uxtb :: inst_uxtb_r_r
|
|
emit_uxtb :: emit_uxtb_r_r
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|
inst_uxtb16 :: inst_uxtb16_r_r
|
|
emit_uxtb16 :: emit_uxtb16_r_r
|
|
inst_uxth :: inst_uxth_r_r
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|
emit_uxth :: emit_uxth_r_r
|
|
inst_sxtab :: inst_sxtab_r_r_r
|
|
emit_sxtab :: emit_sxtab_r_r_r
|
|
inst_sxtab16 :: inst_sxtab16_r_r_r
|
|
emit_sxtab16 :: emit_sxtab16_r_r_r
|
|
inst_sxtah :: inst_sxtah_r_r_r
|
|
emit_sxtah :: emit_sxtah_r_r_r
|
|
inst_uxtab :: inst_uxtab_r_r_r
|
|
emit_uxtab :: emit_uxtab_r_r_r
|
|
inst_uxtab16 :: inst_uxtab16_r_r_r
|
|
emit_uxtab16 :: emit_uxtab16_r_r_r
|
|
inst_uxtah :: inst_uxtah_r_r_r
|
|
emit_uxtah :: emit_uxtah_r_r_r
|
|
inst_clz :: inst_clz_r_r
|
|
emit_clz :: emit_clz_r_r
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|
inst_rbit :: inst_rbit_r_r
|
|
emit_rbit :: emit_rbit_r_r
|
|
inst_rev :: inst_rev_r_r
|
|
emit_rev :: emit_rev_r_r
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|
inst_rev16 :: inst_rev16_r_r
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|
emit_rev16 :: emit_rev16_r_r
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|
inst_revsh :: inst_revsh_r_r
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|
emit_revsh :: emit_revsh_r_r
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|
inst_sel :: inst_sel_r_r_r
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|
emit_sel :: emit_sel_r_r_r
|
|
inst_pkhbt :: inst_pkhbt_r_r_rsh
|
|
emit_pkhbt :: emit_pkhbt_r_r_rsh
|
|
inst_pkhtb :: inst_pkhtb_r_r_rsh
|
|
emit_pkhtb :: emit_pkhtb_r_r_rsh
|
|
inst_usad8 :: inst_usad8_r_r_r
|
|
emit_usad8 :: emit_usad8_r_r_r
|
|
inst_usada8 :: inst_usada8_r_r_r_r
|
|
emit_usada8 :: emit_usada8_r_r_r_r
|
|
inst_ssat :: inst_ssat_r_imm4s_rsh
|
|
emit_ssat :: emit_ssat_r_imm4s_rsh
|
|
inst_usat :: inst_usat_r_imm4s_rsh
|
|
emit_usat :: emit_usat_r_imm4s_rsh
|
|
inst_ssat16 :: inst_ssat16_r_imm4s_r
|
|
emit_ssat16 :: emit_ssat16_r_imm4s_r
|
|
inst_usat16 :: inst_usat16_r_imm4s_r
|
|
emit_usat16 :: emit_usat16_r_imm4s_r
|
|
inst_qadd :: inst_qadd_r_r_r
|
|
emit_qadd :: emit_qadd_r_r_r
|
|
inst_qsub :: inst_qsub_r_r_r
|
|
emit_qsub :: emit_qsub_r_r_r
|
|
inst_qdadd :: inst_qdadd_r_r_r
|
|
emit_qdadd :: emit_qdadd_r_r_r
|
|
inst_qdsub :: inst_qdsub_r_r_r
|
|
emit_qdsub :: emit_qdsub_r_r_r
|
|
inst_sadd8 :: inst_sadd8_r_r_r
|
|
emit_sadd8 :: emit_sadd8_r_r_r
|
|
inst_sadd16 :: inst_sadd16_r_r_r
|
|
emit_sadd16 :: emit_sadd16_r_r_r
|
|
inst_sasx :: inst_sasx_r_r_r
|
|
emit_sasx :: emit_sasx_r_r_r
|
|
inst_ssax :: inst_ssax_r_r_r
|
|
emit_ssax :: emit_ssax_r_r_r
|
|
inst_ssub8 :: inst_ssub8_r_r_r
|
|
emit_ssub8 :: emit_ssub8_r_r_r
|
|
inst_ssub16 :: inst_ssub16_r_r_r
|
|
emit_ssub16 :: emit_ssub16_r_r_r
|
|
inst_uadd8 :: inst_uadd8_r_r_r
|
|
emit_uadd8 :: emit_uadd8_r_r_r
|
|
inst_uadd16 :: inst_uadd16_r_r_r
|
|
emit_uadd16 :: emit_uadd16_r_r_r
|
|
inst_uasx :: inst_uasx_r_r_r
|
|
emit_uasx :: emit_uasx_r_r_r
|
|
inst_usax :: inst_usax_r_r_r
|
|
emit_usax :: emit_usax_r_r_r
|
|
inst_usub8 :: inst_usub8_r_r_r
|
|
emit_usub8 :: emit_usub8_r_r_r
|
|
inst_usub16 :: inst_usub16_r_r_r
|
|
emit_usub16 :: emit_usub16_r_r_r
|
|
inst_qadd8 :: inst_qadd8_r_r_r
|
|
emit_qadd8 :: emit_qadd8_r_r_r
|
|
inst_qadd16 :: inst_qadd16_r_r_r
|
|
emit_qadd16 :: emit_qadd16_r_r_r
|
|
inst_qasx :: inst_qasx_r_r_r
|
|
emit_qasx :: emit_qasx_r_r_r
|
|
inst_qsax :: inst_qsax_r_r_r
|
|
emit_qsax :: emit_qsax_r_r_r
|
|
inst_qsub8 :: inst_qsub8_r_r_r
|
|
emit_qsub8 :: emit_qsub8_r_r_r
|
|
inst_qsub16 :: inst_qsub16_r_r_r
|
|
emit_qsub16 :: emit_qsub16_r_r_r
|
|
inst_uqadd8 :: inst_uqadd8_r_r_r
|
|
emit_uqadd8 :: emit_uqadd8_r_r_r
|
|
inst_uqadd16 :: inst_uqadd16_r_r_r
|
|
emit_uqadd16 :: emit_uqadd16_r_r_r
|
|
inst_uqasx :: inst_uqasx_r_r_r
|
|
emit_uqasx :: emit_uqasx_r_r_r
|
|
inst_uqsax :: inst_uqsax_r_r_r
|
|
emit_uqsax :: emit_uqsax_r_r_r
|
|
inst_uqsub8 :: inst_uqsub8_r_r_r
|
|
emit_uqsub8 :: emit_uqsub8_r_r_r
|
|
inst_uqsub16 :: inst_uqsub16_r_r_r
|
|
emit_uqsub16 :: emit_uqsub16_r_r_r
|
|
inst_shadd8 :: inst_shadd8_r_r_r
|
|
emit_shadd8 :: emit_shadd8_r_r_r
|
|
inst_shadd16 :: inst_shadd16_r_r_r
|
|
emit_shadd16 :: emit_shadd16_r_r_r
|
|
inst_shasx :: inst_shasx_r_r_r
|
|
emit_shasx :: emit_shasx_r_r_r
|
|
inst_shsax :: inst_shsax_r_r_r
|
|
emit_shsax :: emit_shsax_r_r_r
|
|
inst_shsub8 :: inst_shsub8_r_r_r
|
|
emit_shsub8 :: emit_shsub8_r_r_r
|
|
inst_shsub16 :: inst_shsub16_r_r_r
|
|
emit_shsub16 :: emit_shsub16_r_r_r
|
|
inst_uhadd8 :: inst_uhadd8_r_r_r
|
|
emit_uhadd8 :: emit_uhadd8_r_r_r
|
|
inst_uhadd16 :: inst_uhadd16_r_r_r
|
|
emit_uhadd16 :: emit_uhadd16_r_r_r
|
|
inst_uhasx :: inst_uhasx_r_r_r
|
|
emit_uhasx :: emit_uhasx_r_r_r
|
|
inst_uhsax :: inst_uhsax_r_r_r
|
|
emit_uhsax :: emit_uhsax_r_r_r
|
|
inst_uhsub8 :: inst_uhsub8_r_r_r
|
|
emit_uhsub8 :: emit_uhsub8_r_r_r
|
|
inst_uhsub16 :: inst_uhsub16_r_r_r
|
|
emit_uhsub16 :: emit_uhsub16_r_r_r
|
|
inst_smuad :: inst_smuad_r_r_r
|
|
emit_smuad :: emit_smuad_r_r_r
|
|
inst_smuadx :: inst_smuadx_r_r_r
|
|
emit_smuadx :: emit_smuadx_r_r_r
|
|
inst_smusd :: inst_smusd_r_r_r
|
|
emit_smusd :: emit_smusd_r_r_r
|
|
inst_smusdx :: inst_smusdx_r_r_r
|
|
emit_smusdx :: emit_smusdx_r_r_r
|
|
inst_smlad :: inst_smlad_r_r_r_r
|
|
emit_smlad :: emit_smlad_r_r_r_r
|
|
inst_smladx :: inst_smladx_r_r_r_r
|
|
emit_smladx :: emit_smladx_r_r_r_r
|
|
inst_smlsd :: inst_smlsd_r_r_r_r
|
|
emit_smlsd :: emit_smlsd_r_r_r_r
|
|
inst_smlsdx :: inst_smlsdx_r_r_r_r
|
|
emit_smlsdx :: emit_smlsdx_r_r_r_r
|
|
inst_smlald :: inst_smlald_r_r_r_r
|
|
emit_smlald :: emit_smlald_r_r_r_r
|
|
inst_smlaldx :: inst_smlaldx_r_r_r_r
|
|
emit_smlaldx :: emit_smlaldx_r_r_r_r
|
|
inst_smlsld :: inst_smlsld_r_r_r_r
|
|
emit_smlsld :: emit_smlsld_r_r_r_r
|
|
inst_smlsldx :: inst_smlsldx_r_r_r_r
|
|
emit_smlsldx :: emit_smlsldx_r_r_r_r
|
|
inst_smmul :: inst_smmul_r_r_r
|
|
emit_smmul :: emit_smmul_r_r_r
|
|
inst_smmulr :: inst_smmulr_r_r_r
|
|
emit_smmulr :: emit_smmulr_r_r_r
|
|
inst_smmla :: inst_smmla_r_r_r_r
|
|
emit_smmla :: emit_smmla_r_r_r_r
|
|
inst_smmlar :: inst_smmlar_r_r_r_r
|
|
emit_smmlar :: emit_smmlar_r_r_r_r
|
|
inst_smmls :: inst_smmls_r_r_r_r
|
|
emit_smmls :: emit_smmls_r_r_r_r
|
|
inst_smmlsr :: inst_smmlsr_r_r_r_r
|
|
emit_smmlsr :: emit_smmlsr_r_r_r_r
|
|
inst_mul :: proc{ inst_mul_r_r_r, inst_mul_rlo_rlo }
|
|
emit_mul :: proc{ emit_mul_r_r_r, emit_mul_rlo_rlo }
|
|
inst_mla :: inst_mla_r_r_r_r
|
|
emit_mla :: emit_mla_r_r_r_r
|
|
inst_mls :: inst_mls_r_r_r_r
|
|
emit_mls :: emit_mls_r_r_r_r
|
|
inst_umull :: inst_umull_r_r_r_r
|
|
emit_umull :: emit_umull_r_r_r_r
|
|
inst_umlal :: inst_umlal_r_r_r_r
|
|
emit_umlal :: emit_umlal_r_r_r_r
|
|
inst_smull :: inst_smull_r_r_r_r
|
|
emit_smull :: emit_smull_r_r_r_r
|
|
inst_smlal :: inst_smlal_r_r_r_r
|
|
emit_smlal :: emit_smlal_r_r_r_r
|
|
inst_umaal :: inst_umaal_r_r_r_r
|
|
emit_umaal :: emit_umaal_r_r_r_r
|
|
inst_smlabb :: inst_smlabb_r_r_r_r
|
|
emit_smlabb :: emit_smlabb_r_r_r_r
|
|
inst_smlabt :: inst_smlabt_r_r_r_r
|
|
emit_smlabt :: emit_smlabt_r_r_r_r
|
|
inst_smlatb :: inst_smlatb_r_r_r_r
|
|
emit_smlatb :: emit_smlatb_r_r_r_r
|
|
inst_smlatt :: inst_smlatt_r_r_r_r
|
|
emit_smlatt :: emit_smlatt_r_r_r_r
|
|
inst_smlawb :: inst_smlawb_r_r_r_r
|
|
emit_smlawb :: emit_smlawb_r_r_r_r
|
|
inst_smlawt :: inst_smlawt_r_r_r_r
|
|
emit_smlawt :: emit_smlawt_r_r_r_r
|
|
inst_smulbb :: inst_smulbb_r_r_r
|
|
emit_smulbb :: emit_smulbb_r_r_r
|
|
inst_smulbt :: inst_smulbt_r_r_r
|
|
emit_smulbt :: emit_smulbt_r_r_r
|
|
inst_smultb :: inst_smultb_r_r_r
|
|
emit_smultb :: emit_smultb_r_r_r
|
|
inst_smultt :: inst_smultt_r_r_r
|
|
emit_smultt :: emit_smultt_r_r_r
|
|
inst_smulwb :: inst_smulwb_r_r_r
|
|
emit_smulwb :: emit_smulwb_r_r_r
|
|
inst_smulwt :: inst_smulwt_r_r_r
|
|
emit_smulwt :: emit_smulwt_r_r_r
|
|
inst_smlalbb :: inst_smlalbb_r_r_r_r
|
|
emit_smlalbb :: emit_smlalbb_r_r_r_r
|
|
inst_smlalbt :: inst_smlalbt_r_r_r_r
|
|
emit_smlalbt :: emit_smlalbt_r_r_r_r
|
|
inst_smlaltb :: inst_smlaltb_r_r_r_r
|
|
emit_smlaltb :: emit_smlaltb_r_r_r_r
|
|
inst_smlaltt :: inst_smlaltt_r_r_r_r
|
|
emit_smlaltt :: emit_smlaltt_r_r_r_r
|
|
inst_sdiv :: inst_sdiv_r_r_r
|
|
emit_sdiv :: emit_sdiv_r_r_r
|
|
inst_udiv :: inst_udiv_r_r_r
|
|
emit_udiv :: emit_udiv_r_r_r
|
|
inst_b :: proc{ inst_b_rel, inst_b_rel_cond }
|
|
emit_b :: proc{ emit_b_rel, emit_b_rel_cond }
|
|
inst_bl :: inst_bl_rel
|
|
emit_bl :: emit_bl_rel
|
|
inst_bx :: inst_bx_r
|
|
emit_bx :: emit_bx_r
|
|
inst_blx :: proc{ inst_blx_r, inst_blx_rel }
|
|
emit_blx :: proc{ emit_blx_r, emit_blx_rel }
|
|
inst_bxj :: inst_bxj_r
|
|
emit_bxj :: emit_bxj_r
|
|
inst_cbz :: inst_cbz_rlo_rel
|
|
emit_cbz :: emit_cbz_rlo_rel
|
|
inst_cbnz :: inst_cbnz_rlo_rel
|
|
emit_cbnz :: emit_cbnz_rlo_rel
|
|
inst_tbb :: inst_tbb_r_r
|
|
emit_tbb :: emit_tbb_r_r
|
|
inst_tbh :: inst_tbh_r_r
|
|
emit_tbh :: emit_tbh_r_r
|
|
inst_msr :: proc{ inst_msr_psr_immm, inst_msr_psr_r }
|
|
emit_msr :: proc{ emit_msr_psr_immm, emit_msr_psr_r }
|
|
inst_mrs :: inst_mrs_r_psr
|
|
emit_mrs :: emit_mrs_r_psr
|
|
inst_cps :: inst_cps_ifl
|
|
emit_cps :: emit_cps_ifl
|
|
inst_setend :: inst_setend_end
|
|
emit_setend :: emit_setend_end
|
|
inst_nop :: inst_nop_none
|
|
emit_nop :: emit_nop_none
|
|
inst_yield :: inst_yield_none
|
|
emit_yield :: emit_yield_none
|
|
inst_wfe :: inst_wfe_none
|
|
emit_wfe :: emit_wfe_none
|
|
inst_wfi :: inst_wfi_none
|
|
emit_wfi :: emit_wfi_none
|
|
inst_sev :: inst_sev_none
|
|
emit_sev :: emit_sev_none
|
|
inst_sevl :: inst_sevl_none
|
|
emit_sevl :: emit_sevl_none
|
|
inst_dbg :: inst_dbg_hint
|
|
emit_dbg :: emit_dbg_hint
|
|
inst_hint :: inst_hint_hint
|
|
emit_hint :: emit_hint_hint
|
|
inst_dmb :: inst_dmb_barr
|
|
emit_dmb :: emit_dmb_barr
|
|
inst_dsb :: inst_dsb_barr
|
|
emit_dsb :: emit_dsb_barr
|
|
inst_isb :: inst_isb_barr
|
|
emit_isb :: emit_isb_barr
|
|
inst_clrex :: inst_clrex_none
|
|
emit_clrex :: emit_clrex_none
|
|
inst_pld :: inst_pld_mem
|
|
emit_pld :: emit_pld_mem
|
|
inst_pldw :: inst_pldw_mem
|
|
emit_pldw :: emit_pldw_mem
|
|
inst_pli :: inst_pli_mem
|
|
emit_pli :: emit_pli_mem
|
|
inst_hlt :: inst_hlt_imm
|
|
emit_hlt :: emit_hlt_imm
|
|
inst_dcps1 :: inst_dcps1_none
|
|
emit_dcps1 :: emit_dcps1_none
|
|
inst_dcps2 :: inst_dcps2_none
|
|
emit_dcps2 :: emit_dcps2_none
|
|
inst_dcps3 :: inst_dcps3_none
|
|
emit_dcps3 :: emit_dcps3_none
|
|
inst_eret :: inst_eret_none
|
|
emit_eret :: emit_eret_none
|
|
inst_esb :: inst_esb_none
|
|
emit_esb :: emit_esb_none
|
|
inst_psb_csync :: inst_psb_csync_none
|
|
emit_psb_csync :: emit_psb_csync_none
|
|
inst_tsb_csync :: inst_tsb_csync_none
|
|
emit_tsb_csync :: emit_tsb_csync_none
|
|
inst_csdb :: inst_csdb_none
|
|
emit_csdb :: emit_csdb_none
|
|
inst_sb :: inst_sb_none
|
|
emit_sb :: emit_sb_none
|
|
inst_setpan :: inst_setpan_hint
|
|
emit_setpan :: emit_setpan_hint
|
|
inst_svc :: inst_svc_imm
|
|
emit_svc :: emit_svc_imm
|
|
inst_bkpt :: inst_bkpt_imm
|
|
emit_bkpt :: emit_bkpt_imm
|
|
inst_hvc :: inst_hvc_imm
|
|
emit_hvc :: emit_hvc_imm
|
|
inst_smc :: inst_smc_imm
|
|
emit_smc :: emit_smc_imm
|
|
inst_udf :: inst_udf_imm
|
|
emit_udf :: emit_udf_imm
|
|
inst_ldr :: inst_ldr_r_mem
|
|
emit_ldr :: emit_ldr_r_mem
|
|
inst_str :: inst_str_r_mem
|
|
emit_str :: emit_str_r_mem
|
|
inst_ldrb :: inst_ldrb_r_mem
|
|
emit_ldrb :: emit_ldrb_r_mem
|
|
inst_strb :: inst_strb_r_mem
|
|
emit_strb :: emit_strb_r_mem
|
|
inst_ldrh :: inst_ldrh_r_mem
|
|
emit_ldrh :: emit_ldrh_r_mem
|
|
inst_strh :: inst_strh_r_mem
|
|
emit_strh :: emit_strh_r_mem
|
|
inst_ldrsb :: inst_ldrsb_r_mem
|
|
emit_ldrsb :: emit_ldrsb_r_mem
|
|
inst_ldrsh :: inst_ldrsh_r_mem
|
|
emit_ldrsh :: emit_ldrsh_r_mem
|
|
inst_ldrd :: proc{ inst_ldrd_r_mem, inst_ldrd_r_r_mem }
|
|
emit_ldrd :: proc{ emit_ldrd_r_mem, emit_ldrd_r_r_mem }
|
|
inst_strd :: proc{ inst_strd_r_mem, inst_strd_r_r_mem }
|
|
emit_strd :: proc{ emit_strd_r_mem, emit_strd_r_r_mem }
|
|
inst_ldrt :: inst_ldrt_r_mem
|
|
emit_ldrt :: emit_ldrt_r_mem
|
|
inst_strt :: inst_strt_r_mem
|
|
emit_strt :: emit_strt_r_mem
|
|
inst_ldrbt :: inst_ldrbt_r_mem
|
|
emit_ldrbt :: emit_ldrbt_r_mem
|
|
inst_strbt :: inst_strbt_r_mem
|
|
emit_strbt :: emit_strbt_r_mem
|
|
inst_ldrht :: inst_ldrht_r_mem
|
|
emit_ldrht :: emit_ldrht_r_mem
|
|
inst_strht :: inst_strht_r_mem
|
|
emit_strht :: emit_strht_r_mem
|
|
inst_ldrsbt :: inst_ldrsbt_r_mem
|
|
emit_ldrsbt :: emit_ldrsbt_r_mem
|
|
inst_ldrsht :: inst_ldrsht_r_mem
|
|
emit_ldrsht :: emit_ldrsht_r_mem
|
|
inst_lda :: inst_lda_r_mem
|
|
emit_lda :: emit_lda_r_mem
|
|
inst_stl :: inst_stl_r_mem
|
|
emit_stl :: emit_stl_r_mem
|
|
inst_ldab :: inst_ldab_r_mem
|
|
emit_ldab :: emit_ldab_r_mem
|
|
inst_stlb :: inst_stlb_r_mem
|
|
emit_stlb :: emit_stlb_r_mem
|
|
inst_ldah :: inst_ldah_r_mem
|
|
emit_ldah :: emit_ldah_r_mem
|
|
inst_stlh :: inst_stlh_r_mem
|
|
emit_stlh :: emit_stlh_r_mem
|
|
inst_ldrex :: inst_ldrex_r_mem
|
|
emit_ldrex :: emit_ldrex_r_mem
|
|
inst_strex :: inst_strex_r_r_mem
|
|
emit_strex :: emit_strex_r_r_mem
|
|
inst_ldrexb :: inst_ldrexb_r_mem
|
|
emit_ldrexb :: emit_ldrexb_r_mem
|
|
inst_strexb :: inst_strexb_r_r_mem
|
|
emit_strexb :: emit_strexb_r_r_mem
|
|
inst_ldrexh :: inst_ldrexh_r_mem
|
|
emit_ldrexh :: emit_ldrexh_r_mem
|
|
inst_strexh :: inst_strexh_r_r_mem
|
|
emit_strexh :: emit_strexh_r_r_mem
|
|
inst_ldrexd :: proc{ inst_ldrexd_r_mem, inst_ldrexd_r_r_mem }
|
|
emit_ldrexd :: proc{ emit_ldrexd_r_mem, emit_ldrexd_r_r_mem }
|
|
inst_strexd :: proc{ inst_strexd_r_r_mem, inst_strexd_r_r_r_mem }
|
|
emit_strexd :: proc{ emit_strexd_r_r_mem, emit_strexd_r_r_r_mem }
|
|
inst_ldaex :: inst_ldaex_r_mem
|
|
emit_ldaex :: emit_ldaex_r_mem
|
|
inst_stlex :: inst_stlex_r_r_mem
|
|
emit_stlex :: emit_stlex_r_r_mem
|
|
inst_ldaexb :: inst_ldaexb_r_mem
|
|
emit_ldaexb :: emit_ldaexb_r_mem
|
|
inst_stlexb :: inst_stlexb_r_r_mem
|
|
emit_stlexb :: emit_stlexb_r_r_mem
|
|
inst_ldaexh :: inst_ldaexh_r_mem
|
|
emit_ldaexh :: emit_ldaexh_r_mem
|
|
inst_stlexh :: inst_stlexh_r_r_mem
|
|
emit_stlexh :: emit_stlexh_r_r_mem
|
|
inst_ldaexd :: inst_ldaexd_r_mem
|
|
emit_ldaexd :: emit_ldaexd_r_mem
|
|
inst_stlexd :: inst_stlexd_r_r_mem
|
|
emit_stlexd :: emit_stlexd_r_r_mem
|
|
inst_ldm :: inst_ldm_r_list
|
|
emit_ldm :: emit_ldm_r_list
|
|
inst_stm :: inst_stm_r_list
|
|
emit_stm :: emit_stm_r_list
|
|
inst_push :: inst_push_list
|
|
emit_push :: emit_push_list
|
|
inst_pop :: inst_pop_list
|
|
emit_pop :: emit_pop_list
|
|
inst_swp :: inst_swp_r_r_r
|
|
emit_swp :: emit_swp_r_r_r
|
|
inst_swpb :: inst_swpb_r_r_r
|
|
emit_swpb :: emit_swpb_r_r_r
|
|
inst_rfe :: inst_rfe_r
|
|
emit_rfe :: emit_rfe_r
|
|
inst_srs :: inst_srs_imm
|
|
emit_srs :: emit_srs_imm
|
|
inst_cdp :: inst_cdp_cpn_cpop_crd_crd
|
|
emit_cdp :: emit_cdp_cpn_cpop_crd_crd
|
|
inst_cdp2 :: inst_cdp2_cpn_cpop_crd_crd
|
|
emit_cdp2 :: emit_cdp2_cpn_cpop_crd_crd
|
|
inst_mcr :: inst_mcr_cpn_cpop_r_crd
|
|
emit_mcr :: emit_mcr_cpn_cpop_r_crd
|
|
inst_mcr2 :: inst_mcr2_cpn_cpop_r_crd
|
|
emit_mcr2 :: emit_mcr2_cpn_cpop_r_crd
|
|
inst_mrc :: inst_mrc_cpn_cpop_r_crd
|
|
emit_mrc :: emit_mrc_cpn_cpop_r_crd
|
|
inst_mrc2 :: inst_mrc2_cpn_cpop_r_crd
|
|
emit_mrc2 :: emit_mrc2_cpn_cpop_r_crd
|
|
inst_mcrr :: inst_mcrr_cpn_cpop_r_r
|
|
emit_mcrr :: emit_mcrr_cpn_cpop_r_r
|
|
inst_mcrr2 :: inst_mcrr2_cpn_cpop_r_r
|
|
emit_mcrr2 :: emit_mcrr2_cpn_cpop_r_r
|
|
inst_mrrc :: inst_mrrc_cpn_cpop_r_r
|
|
emit_mrrc :: emit_mrrc_cpn_cpop_r_r
|
|
inst_mrrc2 :: inst_mrrc2_cpn_cpop_r_r
|
|
emit_mrrc2 :: emit_mrrc2_cpn_cpop_r_r
|
|
inst_ldc :: inst_ldc_cpn_crd_mem
|
|
emit_ldc :: emit_ldc_cpn_crd_mem
|
|
inst_ldc2 :: inst_ldc2_cpn_crd_mem
|
|
emit_ldc2 :: emit_ldc2_cpn_crd_mem
|
|
inst_stc :: inst_stc_cpn_crd_mem
|
|
emit_stc :: emit_stc_cpn_crd_mem
|
|
inst_stc2 :: inst_stc2_cpn_crd_mem
|
|
emit_stc2 :: emit_stc2_cpn_crd_mem
|
|
inst_crc32b :: inst_crc32b_r_r_r
|
|
emit_crc32b :: emit_crc32b_r_r_r
|
|
inst_crc32h :: inst_crc32h_r_r_r
|
|
emit_crc32h :: emit_crc32h_r_r_r
|
|
inst_crc32w :: inst_crc32w_r_r_r
|
|
emit_crc32w :: emit_crc32w_r_r_r
|
|
inst_crc32cb :: inst_crc32cb_r_r_r
|
|
emit_crc32cb :: emit_crc32cb_r_r_r
|
|
inst_crc32ch :: inst_crc32ch_r_r_r
|
|
emit_crc32ch :: emit_crc32ch_r_r_r
|
|
inst_crc32cw :: inst_crc32cw_r_r_r
|
|
emit_crc32cw :: emit_crc32cw_r_r_r
|
|
inst_vadd :: inst_vadd_s_s_s
|
|
emit_vadd :: emit_vadd_s_s_s
|
|
inst_vsub :: inst_vsub_s_s_s
|
|
emit_vsub :: emit_vsub_s_s_s
|
|
inst_vmul :: inst_vmul_s_s_s
|
|
emit_vmul :: emit_vmul_s_s_s
|
|
inst_vdiv :: inst_vdiv_s_s_s
|
|
emit_vdiv :: emit_vdiv_s_s_s
|
|
inst_vmla :: inst_vmla_s_s_s
|
|
emit_vmla :: emit_vmla_s_s_s
|
|
inst_vmls :: inst_vmls_s_s_s
|
|
emit_vmls :: emit_vmls_s_s_s
|
|
inst_vnmul :: inst_vnmul_s_s_s
|
|
emit_vnmul :: emit_vnmul_s_s_s
|
|
inst_vnmla :: inst_vnmla_s_s_s
|
|
emit_vnmla :: emit_vnmla_s_s_s
|
|
inst_vnmls :: inst_vnmls_s_s_s
|
|
emit_vnmls :: emit_vnmls_s_s_s
|
|
inst_vfma :: inst_vfma_s_s_s
|
|
emit_vfma :: emit_vfma_s_s_s
|
|
inst_vfms :: inst_vfms_s_s_s
|
|
emit_vfms :: emit_vfms_s_s_s
|
|
inst_vfnma :: inst_vfnma_s_s_s
|
|
emit_vfnma :: emit_vfnma_s_s_s
|
|
inst_vfnms :: inst_vfnms_s_s_s
|
|
emit_vfnms :: emit_vfnms_s_s_s
|
|
inst_vabs :: inst_vabs_s_s
|
|
emit_vabs :: emit_vabs_s_s
|
|
inst_vneg :: inst_vneg_s_s
|
|
emit_vneg :: emit_vneg_s_s
|
|
inst_vsqrt :: inst_vsqrt_s_s
|
|
emit_vsqrt :: emit_vsqrt_s_s
|
|
inst_vcmp :: proc{ inst_vcmp_s_s, inst_vcmp_s }
|
|
emit_vcmp :: proc{ emit_vcmp_s_s, emit_vcmp_s }
|
|
inst_vcmpe :: proc{ inst_vcmpe_s_s, inst_vcmpe_s }
|
|
emit_vcmpe :: proc{ emit_vcmpe_s_s, emit_vcmpe_s }
|
|
inst_vcvt :: inst_vcvt_d_s
|
|
emit_vcvt :: emit_vcvt_d_s
|
|
inst_vcvtb :: inst_vcvtb_s_s
|
|
emit_vcvtb :: emit_vcvtb_s_s
|
|
inst_vcvtt :: inst_vcvtt_s_s
|
|
emit_vcvtt :: emit_vcvtt_s_s
|
|
inst_vcvta :: inst_vcvta_s_s
|
|
emit_vcvta :: emit_vcvta_s_s
|
|
inst_vcvtn :: inst_vcvtn_s_s
|
|
emit_vcvtn :: emit_vcvtn_s_s
|
|
inst_vcvtp :: inst_vcvtp_s_s
|
|
emit_vcvtp :: emit_vcvtp_s_s
|
|
inst_vcvtm :: inst_vcvtm_s_s
|
|
emit_vcvtm :: emit_vcvtm_s_s
|
|
inst_vcvtr :: inst_vcvtr_s_s
|
|
emit_vcvtr :: emit_vcvtr_s_s
|
|
inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_dlane_r }
|
|
emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_dlane_r }
|
|
inst_vmrs :: inst_vmrs_r
|
|
emit_vmrs :: emit_vmrs_r
|
|
inst_vmsr :: inst_vmsr_r
|
|
emit_vmsr :: emit_vmsr_r
|
|
inst_vldr :: inst_vldr_s_mem
|
|
emit_vldr :: emit_vldr_s_mem
|
|
inst_vstr :: inst_vstr_s_mem
|
|
emit_vstr :: emit_vstr_s_mem
|
|
inst_vldm :: inst_vldm_r_slist
|
|
emit_vldm :: emit_vldm_r_slist
|
|
inst_vstm :: inst_vstm_r_slist
|
|
emit_vstm :: emit_vstm_r_slist
|
|
inst_vpush :: inst_vpush_slist
|
|
emit_vpush :: emit_vpush_slist
|
|
inst_vpop :: inst_vpop_slist
|
|
emit_vpop :: emit_vpop_slist
|
|
inst_vsel :: inst_vsel_s_s_s_cond
|
|
emit_vsel :: emit_vsel_s_s_s_cond
|
|
inst_vmaxnm :: inst_vmaxnm_s_s_s
|
|
emit_vmaxnm :: emit_vmaxnm_s_s_s
|
|
inst_vminnm :: inst_vminnm_s_s_s
|
|
emit_vminnm :: emit_vminnm_s_s_s
|
|
inst_vrinta :: inst_vrinta_s_s
|
|
emit_vrinta :: emit_vrinta_s_s
|
|
inst_vrintn :: inst_vrintn_s_s
|
|
emit_vrintn :: emit_vrintn_s_s
|
|
inst_vrintp :: inst_vrintp_s_s
|
|
emit_vrintp :: emit_vrintp_s_s
|
|
inst_vrintm :: inst_vrintm_s_s
|
|
emit_vrintm :: emit_vrintm_s_s
|
|
inst_vrintr :: inst_vrintr_s_s
|
|
emit_vrintr :: emit_vrintr_s_s
|
|
inst_vrintz :: inst_vrintz_s_s
|
|
emit_vrintz :: emit_vrintz_s_s
|
|
inst_vrintx :: inst_vrintx_s_s
|
|
emit_vrintx :: emit_vrintx_s_s
|
|
inst_vaddl :: inst_vaddl_q_d_d
|
|
emit_vaddl :: emit_vaddl_q_d_d
|
|
inst_vaddw :: inst_vaddw_q_q_d
|
|
emit_vaddw :: emit_vaddw_q_q_d
|
|
inst_vsubl :: inst_vsubl_q_d_d
|
|
emit_vsubl :: emit_vsubl_q_d_d
|
|
inst_vsubw :: inst_vsubw_q_q_d
|
|
emit_vsubw :: emit_vsubw_q_q_d
|
|
inst_vhadd :: inst_vhadd_d_d_d
|
|
emit_vhadd :: emit_vhadd_d_d_d
|
|
inst_vhsub :: inst_vhsub_d_d_d
|
|
emit_vhsub :: emit_vhsub_d_d_d
|
|
inst_vrhadd :: inst_vrhadd_d_d_d
|
|
emit_vrhadd :: emit_vrhadd_d_d_d
|
|
inst_vqadd :: inst_vqadd_d_d_d
|
|
emit_vqadd :: emit_vqadd_d_d_d
|
|
inst_vqsub :: inst_vqsub_d_d_d
|
|
emit_vqsub :: emit_vqsub_d_d_d
|
|
inst_vmull :: inst_vmull_q_d_d
|
|
emit_vmull :: emit_vmull_q_d_d
|
|
inst_vmlal :: inst_vmlal_q_d_d
|
|
emit_vmlal :: emit_vmlal_q_d_d
|
|
inst_vmlsl :: inst_vmlsl_q_d_d
|
|
emit_vmlsl :: emit_vmlsl_q_d_d
|
|
inst_vqdmull :: inst_vqdmull_q_d_d
|
|
emit_vqdmull :: emit_vqdmull_q_d_d
|
|
inst_vqdmlal :: inst_vqdmlal_q_d_d
|
|
emit_vqdmlal :: emit_vqdmlal_q_d_d
|
|
inst_vqdmlsl :: inst_vqdmlsl_q_d_d
|
|
emit_vqdmlsl :: emit_vqdmlsl_q_d_d
|
|
inst_vqdmulh :: inst_vqdmulh_d_d_d
|
|
emit_vqdmulh :: emit_vqdmulh_d_d_d
|
|
inst_vqrdmulh :: inst_vqrdmulh_d_d_d
|
|
emit_vqrdmulh :: emit_vqrdmulh_d_d_d
|
|
inst_vqdmulh_lane :: inst_vqdmulh_lane_d_d_dlane
|
|
emit_vqdmulh_lane :: emit_vqdmulh_lane_d_d_dlane
|
|
inst_vqrdmulh_lane :: inst_vqrdmulh_lane_d_d_dlane
|
|
emit_vqrdmulh_lane :: emit_vqrdmulh_lane_d_d_dlane
|
|
inst_vqrdmlah :: inst_vqrdmlah_d_d_d
|
|
emit_vqrdmlah :: emit_vqrdmlah_d_d_d
|
|
inst_vqrdmlsh :: inst_vqrdmlsh_d_d_d
|
|
emit_vqrdmlsh :: emit_vqrdmlsh_d_d_d
|
|
inst_vaba :: inst_vaba_d_d_d
|
|
emit_vaba :: emit_vaba_d_d_d
|
|
inst_vabal :: inst_vabal_q_d_d
|
|
emit_vabal :: emit_vabal_q_d_d
|
|
inst_vabd :: inst_vabd_d_d_d
|
|
emit_vabd :: emit_vabd_d_d_d
|
|
inst_vabdl :: inst_vabdl_q_d_d
|
|
emit_vabdl :: emit_vabdl_q_d_d
|
|
inst_vand :: inst_vand_d_d_d
|
|
emit_vand :: emit_vand_d_d_d
|
|
inst_vbic :: inst_vbic_d_d_d
|
|
emit_vbic :: emit_vbic_d_d_d
|
|
inst_vorr :: inst_vorr_d_d_d
|
|
emit_vorr :: emit_vorr_d_d_d
|
|
inst_vorn :: inst_vorn_d_d_d
|
|
emit_vorn :: emit_vorn_d_d_d
|
|
inst_veor :: inst_veor_d_d_d
|
|
emit_veor :: emit_veor_d_d_d
|
|
inst_vbsl :: inst_vbsl_d_d_d
|
|
emit_vbsl :: emit_vbsl_d_d_d
|
|
inst_vbit :: inst_vbit_d_d_d
|
|
emit_vbit :: emit_vbit_d_d_d
|
|
inst_vbif :: inst_vbif_d_d_d
|
|
emit_vbif :: emit_vbif_d_d_d
|
|
inst_vmvn :: proc{ inst_vmvn_d_d, inst_vmvn_d_imm }
|
|
emit_vmvn :: proc{ emit_vmvn_d_d, emit_vmvn_d_imm }
|
|
inst_vmovn :: inst_vmovn_d_q
|
|
emit_vmovn :: emit_vmovn_d_q
|
|
inst_vqmovn :: inst_vqmovn_d_q
|
|
emit_vqmovn :: emit_vqmovn_d_q
|
|
inst_vqmovun :: inst_vqmovun_d_q
|
|
emit_vqmovun :: emit_vqmovun_d_q
|
|
inst_vmovl :: inst_vmovl_q_d
|
|
emit_vmovl :: emit_vmovl_q_d
|
|
inst_vtst :: inst_vtst_d_d_d
|
|
emit_vtst :: emit_vtst_d_d_d
|
|
inst_vceq :: inst_vceq_d_d_d
|
|
emit_vceq :: emit_vceq_d_d_d
|
|
inst_vcge :: inst_vcge_d_d_d
|
|
emit_vcge :: emit_vcge_d_d_d
|
|
inst_vcgt :: inst_vcgt_d_d_d
|
|
emit_vcgt :: emit_vcgt_d_d_d
|
|
inst_vcle :: inst_vcle_d_d_d
|
|
emit_vcle :: emit_vcle_d_d_d
|
|
inst_vclt :: inst_vclt_d_d_d
|
|
emit_vclt :: emit_vclt_d_d_d
|
|
inst_vacge :: inst_vacge_d_d_d
|
|
emit_vacge :: emit_vacge_d_d_d
|
|
inst_vacgt :: inst_vacgt_d_d_d
|
|
emit_vacgt :: emit_vacgt_d_d_d
|
|
inst_vacle :: inst_vacle_d_d_d
|
|
emit_vacle :: emit_vacle_d_d_d
|
|
inst_vaclt :: inst_vaclt_d_d_d
|
|
emit_vaclt :: emit_vaclt_d_d_d
|
|
inst_vmax :: inst_vmax_d_d_d
|
|
emit_vmax :: emit_vmax_d_d_d
|
|
inst_vmin :: inst_vmin_d_d_d
|
|
emit_vmin :: emit_vmin_d_d_d
|
|
inst_vpmax :: inst_vpmax_d_d_d
|
|
emit_vpmax :: emit_vpmax_d_d_d
|
|
inst_vpmin :: inst_vpmin_d_d_d
|
|
emit_vpmin :: emit_vpmin_d_d_d
|
|
inst_vpadd :: inst_vpadd_d_d_d
|
|
emit_vpadd :: emit_vpadd_d_d_d
|
|
inst_vpaddl :: inst_vpaddl_d_d
|
|
emit_vpaddl :: emit_vpaddl_d_d
|
|
inst_vpadal :: inst_vpadal_d_d
|
|
emit_vpadal :: emit_vpadal_d_d
|
|
inst_vrecpe :: inst_vrecpe_d_d
|
|
emit_vrecpe :: emit_vrecpe_d_d
|
|
inst_vrecps :: inst_vrecps_d_d_d
|
|
emit_vrecps :: emit_vrecps_d_d_d
|
|
inst_vrsqrte :: inst_vrsqrte_d_d
|
|
emit_vrsqrte :: emit_vrsqrte_d_d
|
|
inst_vrsqrts :: inst_vrsqrts_d_d_d
|
|
emit_vrsqrts :: emit_vrsqrts_d_d_d
|
|
inst_vshl :: inst_vshl_d_d_d
|
|
emit_vshl :: emit_vshl_d_d_d
|
|
inst_vshr :: inst_vshr_d_d_imm
|
|
emit_vshr :: emit_vshr_d_d_imm
|
|
inst_vsra :: inst_vsra_d_d_imm
|
|
emit_vsra :: emit_vsra_d_d_imm
|
|
inst_vrshl :: inst_vrshl_d_d_d
|
|
emit_vrshl :: emit_vrshl_d_d_d
|
|
inst_vrshr :: inst_vrshr_d_d_imm
|
|
emit_vrshr :: emit_vrshr_d_d_imm
|
|
inst_vrsra :: inst_vrsra_d_d_imm
|
|
emit_vrsra :: emit_vrsra_d_d_imm
|
|
inst_vsli :: inst_vsli_d_d_imm
|
|
emit_vsli :: emit_vsli_d_d_imm
|
|
inst_vsri :: inst_vsri_d_d_imm
|
|
emit_vsri :: emit_vsri_d_d_imm
|
|
inst_vqshl :: proc{ inst_vqshl_d_d_d, inst_vqshl_d_d_imm }
|
|
emit_vqshl :: proc{ emit_vqshl_d_d_d, emit_vqshl_d_d_imm }
|
|
inst_vqshrn :: inst_vqshrn_d_q_imm
|
|
emit_vqshrn :: emit_vqshrn_d_q_imm
|
|
inst_vqshrun :: inst_vqshrun_d_q_imm
|
|
emit_vqshrun :: emit_vqshrun_d_q_imm
|
|
inst_vqrshl :: inst_vqrshl_d_d_d
|
|
emit_vqrshl :: emit_vqrshl_d_d_d
|
|
inst_vqrshrn :: inst_vqrshrn_d_q_imm
|
|
emit_vqrshrn :: emit_vqrshrn_d_q_imm
|
|
inst_vqrshrun :: inst_vqrshrun_d_q_imm
|
|
emit_vqrshrun :: emit_vqrshrun_d_q_imm
|
|
inst_vshrn :: inst_vshrn_d_q_imm
|
|
emit_vshrn :: emit_vshrn_d_q_imm
|
|
inst_vrshrn :: inst_vrshrn_d_q_imm
|
|
emit_vrshrn :: emit_vrshrn_d_q_imm
|
|
inst_vshll :: proc{ inst_vshll_q_d_imm, inst_vshll_q_d }
|
|
emit_vshll :: proc{ emit_vshll_q_d_imm, emit_vshll_q_d }
|
|
inst_vcls :: inst_vcls_d_d
|
|
emit_vcls :: emit_vcls_d_d
|
|
inst_vclz :: inst_vclz_d_d
|
|
emit_vclz :: emit_vclz_d_d
|
|
inst_vcnt :: inst_vcnt_d_d
|
|
emit_vcnt :: emit_vcnt_d_d
|
|
inst_vpadd_f :: inst_vpadd_f_d_d_d
|
|
emit_vpadd_f :: emit_vpadd_f_d_d_d
|
|
inst_vrecpe_f :: inst_vrecpe_f_d_d
|
|
emit_vrecpe_f :: emit_vrecpe_f_d_d
|
|
inst_vrsqrte_f :: inst_vrsqrte_f_d_d
|
|
emit_vrsqrte_f :: emit_vrsqrte_f_d_d
|
|
inst_vrev16 :: inst_vrev16_d_d
|
|
emit_vrev16 :: emit_vrev16_d_d
|
|
inst_vrev32 :: inst_vrev32_d_d
|
|
emit_vrev32 :: emit_vrev32_d_d
|
|
inst_vrev64 :: inst_vrev64_d_d
|
|
emit_vrev64 :: emit_vrev64_d_d
|
|
inst_vext :: inst_vext_d_d_d_imm4
|
|
emit_vext :: emit_vext_d_d_d_imm4
|
|
inst_vtbl :: proc{ inst_vtbl_d_d_d, inst_vtbl_d_dlist_d }
|
|
emit_vtbl :: proc{ emit_vtbl_d_d_d, emit_vtbl_d_dlist_d }
|
|
inst_vtbx :: proc{ inst_vtbx_d_d_d, inst_vtbx_d_dlist_d }
|
|
emit_vtbx :: proc{ emit_vtbx_d_d_d, emit_vtbx_d_dlist_d }
|
|
inst_vtrn :: inst_vtrn_d_d
|
|
emit_vtrn :: emit_vtrn_d_d
|
|
inst_vuzp :: inst_vuzp_d_d
|
|
emit_vuzp :: emit_vuzp_d_d
|
|
inst_vzip :: inst_vzip_d_d
|
|
emit_vzip :: emit_vzip_d_d
|
|
inst_vdup :: proc{ inst_vdup_d_r, inst_vdup_d_dlane }
|
|
emit_vdup :: proc{ emit_vdup_d_r, emit_vdup_d_dlane }
|
|
inst_vswp :: inst_vswp_d_d
|
|
emit_vswp :: emit_vswp_d_d
|
|
inst_vmov_lane :: inst_vmov_lane_dlane_r
|
|
emit_vmov_lane :: emit_vmov_lane_dlane_r
|
|
inst_vld1 :: proc{ inst_vld1_dlist_mem, inst_vld1_dlane_mem }
|
|
emit_vld1 :: proc{ emit_vld1_dlist_mem, emit_vld1_dlane_mem }
|
|
inst_vld2 :: inst_vld2_dlist_mem
|
|
emit_vld2 :: emit_vld2_dlist_mem
|
|
inst_vld3 :: inst_vld3_dlist_mem
|
|
emit_vld3 :: emit_vld3_dlist_mem
|
|
inst_vld4 :: inst_vld4_dlist_mem
|
|
emit_vld4 :: emit_vld4_dlist_mem
|
|
inst_vst1 :: proc{ inst_vst1_dlist_mem, inst_vst1_dlane_mem }
|
|
emit_vst1 :: proc{ emit_vst1_dlist_mem, emit_vst1_dlane_mem }
|
|
inst_vst2 :: inst_vst2_dlist_mem
|
|
emit_vst2 :: emit_vst2_dlist_mem
|
|
inst_vst3 :: inst_vst3_dlist_mem
|
|
emit_vst3 :: emit_vst3_dlist_mem
|
|
inst_vst4 :: inst_vst4_dlist_mem
|
|
emit_vst4 :: emit_vst4_dlist_mem
|
|
inst_aese :: inst_aese_q_q
|
|
emit_aese :: emit_aese_q_q
|
|
inst_aesd :: inst_aesd_q_q
|
|
emit_aesd :: emit_aesd_q_q
|
|
inst_aesmc :: inst_aesmc_q_q
|
|
emit_aesmc :: emit_aesmc_q_q
|
|
inst_aesimc :: inst_aesimc_q_q
|
|
emit_aesimc :: emit_aesimc_q_q
|
|
inst_sha1h :: inst_sha1h_q_q
|
|
emit_sha1h :: emit_sha1h_q_q
|
|
inst_sha1su0 :: inst_sha1su0_q_q_q
|
|
emit_sha1su0 :: emit_sha1su0_q_q_q
|
|
inst_sha1su1 :: inst_sha1su1_q_q
|
|
emit_sha1su1 :: emit_sha1su1_q_q
|
|
inst_sha1c :: inst_sha1c_q_q_q
|
|
emit_sha1c :: emit_sha1c_q_q_q
|
|
inst_sha1m :: inst_sha1m_q_q_q
|
|
emit_sha1m :: emit_sha1m_q_q_q
|
|
inst_sha1p :: inst_sha1p_q_q_q
|
|
emit_sha1p :: emit_sha1p_q_q_q
|
|
inst_sha256h :: inst_sha256h_q_q_q
|
|
emit_sha256h :: emit_sha256h_q_q_q
|
|
inst_sha256h2 :: inst_sha256h2_q_q_q
|
|
emit_sha256h2 :: emit_sha256h2_q_q_q
|
|
inst_sha256su0 :: inst_sha256su0_q_q
|
|
emit_sha256su0 :: emit_sha256su0_q_q
|
|
inst_sha256su1 :: inst_sha256su1_q_q_q
|
|
emit_sha256su1 :: emit_sha256su1_q_q_q
|
|
inst_vjcvt :: inst_vjcvt_s_d
|
|
emit_vjcvt :: emit_vjcvt_s_d
|
|
inst_vsdot :: inst_vsdot_d_d_d
|
|
emit_vsdot :: emit_vsdot_d_d_d
|
|
inst_vudot :: inst_vudot_d_d_d
|
|
emit_vudot :: emit_vudot_d_d_d
|
|
inst_vsdot_lane :: inst_vsdot_lane_d_d_dlane
|
|
emit_vsdot_lane :: emit_vsdot_lane_d_d_dlane
|
|
inst_vudot_lane :: inst_vudot_lane_d_d_dlane
|
|
emit_vudot_lane :: emit_vudot_lane_d_d_dlane
|
|
inst_vcvt_bf16 :: inst_vcvt_bf16_d_q
|
|
emit_vcvt_bf16 :: emit_vcvt_bf16_d_q
|
|
inst_vdot_bf16 :: inst_vdot_bf16_d_d_d
|
|
emit_vdot_bf16 :: emit_vdot_bf16_d_d_d
|
|
inst_vfma_bf16 :: inst_vfma_bf16_q_q_q
|
|
emit_vfma_bf16 :: emit_vfma_bf16_q_q_q
|
|
inst_vmmla_bf16 :: inst_vmmla_bf16_q_q_q
|
|
emit_vmmla_bf16 :: emit_vmmla_bf16_q_q_q
|
|
inst_vfmal :: inst_vfmal_d_d_d
|
|
emit_vfmal :: emit_vfmal_d_d_d
|
|
inst_vfmsl :: inst_vfmsl_d_d_d
|
|
emit_vfmsl :: emit_vfmsl_d_d_d
|
|
inst_vcmla :: inst_vcmla_d_d_d_imm
|
|
emit_vcmla :: emit_vcmla_d_d_d_imm
|
|
inst_vcadd :: inst_vcadd_d_d_d_imm
|
|
emit_vcadd :: emit_vcadd_d_d_d_imm
|
|
inst_vcmla_lane :: inst_vcmla_lane_d_d_dlane_imm
|
|
emit_vcmla_lane :: emit_vcmla_lane_d_d_dlane_imm
|
|
inst_vsmmla :: inst_vsmmla_q_q_q
|
|
emit_vsmmla :: emit_vsmmla_q_q_q
|
|
inst_vummla :: inst_vummla_q_q_q
|
|
emit_vummla :: emit_vummla_q_q_q
|
|
inst_vusmmla :: inst_vusmmla_q_q_q
|
|
emit_vusmmla :: emit_vusmmla_q_q_q
|
|
inst_vsudot :: inst_vsudot_q_q_q
|
|
emit_vsudot :: emit_vsudot_q_q_q
|
|
inst_vusdot :: inst_vusdot_d_d_d
|
|
emit_vusdot :: emit_vusdot_d_d_d
|
|
inst_vsudot_lane :: inst_vsudot_lane_q_q_dlane
|
|
emit_vsudot_lane :: emit_vsudot_lane_q_q_dlane
|
|
inst_vusdot_lane :: inst_vusdot_lane_d_d_dlane
|
|
emit_vusdot_lane :: emit_vusdot_lane_d_d_dlane
|
|
inst_vmul_lane :: inst_vmul_lane_d_d_dlane
|
|
emit_vmul_lane :: emit_vmul_lane_d_d_dlane
|
|
inst_vmla_lane :: inst_vmla_lane_d_d_dlane
|
|
emit_vmla_lane :: emit_vmla_lane_d_d_dlane
|
|
inst_vmls_lane :: inst_vmls_lane_d_d_dlane
|
|
emit_vmls_lane :: emit_vmls_lane_d_d_dlane
|
|
inst_vmull_lane :: inst_vmull_lane_q_d_dlane
|
|
emit_vmull_lane :: emit_vmull_lane_q_d_dlane
|
|
inst_vmlal_lane :: inst_vmlal_lane_q_d_dlane
|
|
emit_vmlal_lane :: emit_vmlal_lane_q_d_dlane
|
|
inst_vmlsl_lane :: inst_vmlsl_lane_q_d_dlane
|
|
emit_vmlsl_lane :: emit_vmlsl_lane_q_d_dlane
|
|
inst_vqdmull_lane :: inst_vqdmull_lane_q_d_dlane
|
|
emit_vqdmull_lane :: emit_vqdmull_lane_q_d_dlane
|
|
inst_vqdmlal_lane :: inst_vqdmlal_lane_q_d_dlane
|
|
emit_vqdmlal_lane :: emit_vqdmlal_lane_q_d_dlane
|
|
inst_vqdmlsl_lane :: inst_vqdmlsl_lane_q_d_dlane
|
|
emit_vqdmlsl_lane :: emit_vqdmlsl_lane_q_d_dlane
|
|
inst_vfma_lane :: inst_vfma_lane_d_d_dlane
|
|
emit_vfma_lane :: emit_vfma_lane_d_d_dlane
|
|
inst_vfms_lane :: inst_vfms_lane_d_d_dlane
|
|
emit_vfms_lane :: emit_vfms_lane_d_d_dlane
|
|
inst_vqrdmlah_lane :: inst_vqrdmlah_lane_d_d_dlane
|
|
emit_vqrdmlah_lane :: emit_vqrdmlah_lane_d_d_dlane
|
|
inst_vqrdmlsh_lane :: inst_vqrdmlsh_lane_d_d_dlane
|
|
emit_vqrdmlsh_lane :: emit_vqrdmlsh_lane_d_d_dlane
|
|
inst_vqabs :: inst_vqabs_q_q
|
|
emit_vqabs :: emit_vqabs_q_q
|
|
inst_vqneg :: inst_vqneg_q_q
|
|
emit_vqneg :: emit_vqneg_q_q
|
|
inst_vmovx :: inst_vmovx_s_s
|
|
emit_vmovx :: emit_vmovx_s_s
|
|
inst_vins :: inst_vins_s_s
|
|
emit_vins :: emit_vins_s_s
|
|
inst_vldrb_gather :: inst_vldrb_gather_q_mem_q
|
|
emit_vldrb_gather :: emit_vldrb_gather_q_mem_q
|
|
inst_vldrh_gather :: inst_vldrh_gather_q_mem_q
|
|
emit_vldrh_gather :: emit_vldrh_gather_q_mem_q
|
|
inst_vldrw_gather :: inst_vldrw_gather_q_mem_q
|
|
emit_vldrw_gather :: emit_vldrw_gather_q_mem_q
|
|
inst_vldrd_gather :: inst_vldrd_gather_q_mem_q
|
|
emit_vldrd_gather :: emit_vldrd_gather_q_mem_q
|
|
inst_vstrb_scatter :: inst_vstrb_scatter_q_mem_q
|
|
emit_vstrb_scatter :: emit_vstrb_scatter_q_mem_q
|
|
inst_vstrh_scatter :: inst_vstrh_scatter_q_mem_q
|
|
emit_vstrh_scatter :: emit_vstrh_scatter_q_mem_q
|
|
inst_vstrw_scatter :: inst_vstrw_scatter_q_mem_q
|
|
emit_vstrw_scatter :: emit_vstrw_scatter_q_mem_q
|
|
inst_vstrd_scatter :: inst_vstrd_scatter_q_mem_q
|
|
emit_vstrd_scatter :: emit_vstrd_scatter_q_mem_q
|
|
inst_vceq_z :: inst_vceq_z_d_d
|
|
emit_vceq_z :: emit_vceq_z_d_d
|
|
inst_vcge_z :: inst_vcge_z_d_d
|
|
emit_vcge_z :: emit_vcge_z_d_d
|
|
inst_vcgt_z :: inst_vcgt_z_d_d
|
|
emit_vcgt_z :: emit_vcgt_z_d_d
|
|
inst_vcle_z :: inst_vcle_z_d_d
|
|
emit_vcle_z :: emit_vcle_z_d_d
|
|
inst_vclt_z :: inst_vclt_z_d_d
|
|
emit_vclt_z :: emit_vclt_z_d_d
|
|
inst_vld2r :: inst_vld2r_dlist_mem
|
|
emit_vld2r :: emit_vld2r_dlist_mem
|
|
inst_vld3r :: inst_vld3r_dlist_mem
|
|
emit_vld3r :: emit_vld3r_dlist_mem
|
|
inst_vld4r :: inst_vld4r_dlist_mem
|
|
emit_vld4r :: emit_vld4r_dlist_mem
|
|
inst_vld1_lane :: inst_vld1_lane_dlane_mem
|
|
emit_vld1_lane :: emit_vld1_lane_dlane_mem
|
|
inst_vld2_lane :: inst_vld2_lane_dlist_mem
|
|
emit_vld2_lane :: emit_vld2_lane_dlist_mem
|
|
inst_vld3_lane :: inst_vld3_lane_dlist_mem
|
|
emit_vld3_lane :: emit_vld3_lane_dlist_mem
|
|
inst_vld4_lane :: inst_vld4_lane_dlist_mem
|
|
emit_vld4_lane :: emit_vld4_lane_dlist_mem
|
|
inst_vst1_lane :: inst_vst1_lane_dlane_mem
|
|
emit_vst1_lane :: emit_vst1_lane_dlane_mem
|
|
inst_vst2_lane :: inst_vst2_lane_dlist_mem
|
|
emit_vst2_lane :: emit_vst2_lane_dlist_mem
|
|
inst_vst3_lane :: inst_vst3_lane_dlist_mem
|
|
emit_vst3_lane :: emit_vst3_lane_dlist_mem
|
|
inst_vst4_lane :: inst_vst4_lane_dlist_mem
|
|
emit_vst4_lane :: emit_vst4_lane_dlist_mem
|
|
inst_vcvt_fixed :: inst_vcvt_fixed_s_s_imm
|
|
emit_vcvt_fixed :: emit_vcvt_fixed_s_s_imm
|
|
inst_it :: inst_it_cond_imm4
|
|
emit_it :: emit_it_cond_imm4
|
|
inst_tt :: inst_tt_r_r
|
|
emit_tt :: emit_tt_r_r
|
|
inst_ttt :: inst_ttt_r_r
|
|
emit_ttt :: emit_ttt_r_r
|
|
inst_tta :: inst_tta_r_r
|
|
emit_tta :: emit_tta_r_r
|
|
inst_ttat :: inst_ttat_r_r
|
|
emit_ttat :: emit_ttat_r_r
|
|
inst_sg :: inst_sg_none
|
|
emit_sg :: emit_sg_none
|
|
inst_bxns :: inst_bxns_r
|
|
emit_bxns :: emit_bxns_r
|
|
inst_blxns :: inst_blxns_r
|
|
emit_blxns :: emit_blxns_r
|
|
inst_pac :: inst_pac_none
|
|
emit_pac :: emit_pac_none
|
|
inst_pacbti :: inst_pacbti_none
|
|
emit_pacbti :: emit_pacbti_none
|
|
inst_aut :: inst_aut_none
|
|
emit_aut :: emit_aut_none
|
|
inst_autg :: inst_autg_r_r_r
|
|
emit_autg :: emit_autg_r_r_r
|
|
inst_bti :: inst_bti_none
|
|
emit_bti :: emit_bti_none
|
|
inst_wls :: inst_wls_r_rel
|
|
emit_wls :: emit_wls_r_rel
|
|
inst_wlstp :: inst_wlstp_r_rel
|
|
emit_wlstp :: emit_wlstp_r_rel
|
|
inst_dls :: inst_dls_r
|
|
emit_dls :: emit_dls_r
|
|
inst_dlstp :: inst_dlstp_r
|
|
emit_dlstp :: emit_dlstp_r
|
|
inst_le :: inst_le_rel
|
|
emit_le :: emit_le_rel
|
|
inst_letp :: inst_letp_rel
|
|
emit_letp :: emit_letp_rel
|
|
inst_lctp :: inst_lctp_none
|
|
emit_lctp :: emit_lctp_none
|
|
inst_cx1 :: inst_cx1_cp_r_imm
|
|
emit_cx1 :: emit_cx1_cp_r_imm
|
|
inst_cx1a :: inst_cx1a_cp_r_imm
|
|
emit_cx1a :: emit_cx1a_cp_r_imm
|
|
inst_cx1d :: inst_cx1d_cp_r_imm
|
|
emit_cx1d :: emit_cx1d_cp_r_imm
|
|
inst_cx1da :: inst_cx1da_cp_r_imm
|
|
emit_cx1da :: emit_cx1da_cp_r_imm
|
|
inst_cx2 :: inst_cx2_cp_r_r_imm
|
|
emit_cx2 :: emit_cx2_cp_r_r_imm
|
|
inst_cx2a :: inst_cx2a_cp_r_r_imm
|
|
emit_cx2a :: emit_cx2a_cp_r_r_imm
|
|
inst_cx2d :: inst_cx2d_cp_r_r_imm
|
|
emit_cx2d :: emit_cx2d_cp_r_r_imm
|
|
inst_cx2da :: inst_cx2da_cp_r_r_imm
|
|
emit_cx2da :: emit_cx2da_cp_r_r_imm
|
|
inst_cx3 :: inst_cx3_cp_r_r_r
|
|
emit_cx3 :: emit_cx3_cp_r_r_r
|
|
inst_cx3a :: inst_cx3a_cp_r_r_r
|
|
emit_cx3a :: emit_cx3a_cp_r_r_r
|
|
inst_cx3d :: inst_cx3d_cp_r_r_r
|
|
emit_cx3d :: emit_cx3d_cp_r_r_r
|
|
inst_cx3da :: inst_cx3da_cp_r_r_r
|
|
emit_cx3da :: emit_cx3da_cp_r_r_r
|
|
inst_vcx1 :: inst_vcx1_cp_s_imm
|
|
emit_vcx1 :: emit_vcx1_cp_s_imm
|
|
inst_vcx1a :: inst_vcx1a_cp_s_imm
|
|
emit_vcx1a :: emit_vcx1a_cp_s_imm
|
|
inst_vcx2 :: inst_vcx2_cp_s_s_imm
|
|
emit_vcx2 :: emit_vcx2_cp_s_s_imm
|
|
inst_vcx2a :: inst_vcx2a_cp_s_s_imm
|
|
emit_vcx2a :: emit_vcx2a_cp_s_s_imm
|
|
inst_vcx3 :: inst_vcx3_cp_s_s_s
|
|
emit_vcx3 :: emit_vcx3_cp_s_s_s
|
|
inst_vcx3a :: inst_vcx3a_cp_s_s_s
|
|
emit_vcx3a :: emit_vcx3a_cp_s_s_s
|
|
inst_vpt :: inst_vpt_vpt_cond_q_q
|
|
emit_vpt :: emit_vpt_vpt_cond_q_q
|
|
inst_vpst :: inst_vpst_vpt
|
|
emit_vpst :: emit_vpst_vpt
|
|
inst_vpsel :: inst_vpsel_q_q_q
|
|
emit_vpsel :: emit_vpsel_q_q_q
|
|
inst_vpnot :: inst_vpnot_none
|
|
emit_vpnot :: emit_vpnot_none
|
|
inst_vctp :: inst_vctp_r
|
|
emit_vctp :: emit_vctp_r
|
|
inst_vaddv :: inst_vaddv_r_q
|
|
emit_vaddv :: emit_vaddv_r_q
|
|
inst_vaddva :: inst_vaddva_r_q
|
|
emit_vaddva :: emit_vaddva_r_q
|
|
inst_vaddlv :: inst_vaddlv_r_r_q
|
|
emit_vaddlv :: emit_vaddlv_r_r_q
|
|
inst_vaddlva :: inst_vaddlva_r_r_q
|
|
emit_vaddlva :: emit_vaddlva_r_r_q
|
|
inst_vmaxv :: inst_vmaxv_r_q
|
|
emit_vmaxv :: emit_vmaxv_r_q
|
|
inst_vmaxav :: inst_vmaxav_r_q
|
|
emit_vmaxav :: emit_vmaxav_r_q
|
|
inst_vminv :: inst_vminv_r_q
|
|
emit_vminv :: emit_vminv_r_q
|
|
inst_vminav :: inst_vminav_r_q
|
|
emit_vminav :: emit_vminav_r_q
|
|
inst_vmaxnmv :: inst_vmaxnmv_r_q
|
|
emit_vmaxnmv :: emit_vmaxnmv_r_q
|
|
inst_vmaxnmav :: inst_vmaxnmav_r_q
|
|
emit_vmaxnmav :: emit_vmaxnmav_r_q
|
|
inst_vminnmv :: inst_vminnmv_r_q
|
|
emit_vminnmv :: emit_vminnmv_r_q
|
|
inst_vminnmav :: inst_vminnmav_r_q
|
|
emit_vminnmav :: emit_vminnmav_r_q
|
|
inst_vabav :: inst_vabav_r_q_q
|
|
emit_vabav :: emit_vabav_r_q_q
|
|
inst_vmladav :: inst_vmladav_r_q_q
|
|
emit_vmladav :: emit_vmladav_r_q_q
|
|
inst_vmladava :: inst_vmladava_r_q_q
|
|
emit_vmladava :: emit_vmladava_r_q_q
|
|
inst_vmladavx :: inst_vmladavx_r_q_q
|
|
emit_vmladavx :: emit_vmladavx_r_q_q
|
|
inst_vmladavax :: inst_vmladavax_r_q_q
|
|
emit_vmladavax :: emit_vmladavax_r_q_q
|
|
inst_vmlaldav :: inst_vmlaldav_r_r_q_q
|
|
emit_vmlaldav :: emit_vmlaldav_r_r_q_q
|
|
inst_vmlaldava :: inst_vmlaldava_r_r_q_q
|
|
emit_vmlaldava :: emit_vmlaldava_r_r_q_q
|
|
inst_vmlaldavx :: inst_vmlaldavx_r_r_q_q
|
|
emit_vmlaldavx :: emit_vmlaldavx_r_r_q_q
|
|
inst_vmlaldavax :: inst_vmlaldavax_r_r_q_q
|
|
emit_vmlaldavax :: emit_vmlaldavax_r_r_q_q
|
|
inst_vmlsdav :: inst_vmlsdav_r_q_q
|
|
emit_vmlsdav :: emit_vmlsdav_r_q_q
|
|
inst_vmlsdava :: inst_vmlsdava_r_q_q
|
|
emit_vmlsdava :: emit_vmlsdava_r_q_q
|
|
inst_vmlsdavx :: inst_vmlsdavx_r_q_q
|
|
emit_vmlsdavx :: emit_vmlsdavx_r_q_q
|
|
inst_vmlsdavax :: inst_vmlsdavax_r_q_q
|
|
emit_vmlsdavax :: emit_vmlsdavax_r_q_q
|
|
inst_vmlsldav :: inst_vmlsldav_r_r_q_q
|
|
emit_vmlsldav :: emit_vmlsldav_r_r_q_q
|
|
inst_vmlsldava :: inst_vmlsldava_r_r_q_q
|
|
emit_vmlsldava :: emit_vmlsldava_r_r_q_q
|
|
inst_vmlsldavx :: inst_vmlsldavx_r_r_q_q
|
|
emit_vmlsldavx :: emit_vmlsldavx_r_r_q_q
|
|
inst_vmlsldavax :: inst_vmlsldavax_r_r_q_q
|
|
emit_vmlsldavax :: emit_vmlsldavax_r_r_q_q
|
|
inst_vrmlaldavh :: inst_vrmlaldavh_r_r_q_q
|
|
emit_vrmlaldavh :: emit_vrmlaldavh_r_r_q_q
|
|
inst_vrmlaldavha :: inst_vrmlaldavha_r_r_q_q
|
|
emit_vrmlaldavha :: emit_vrmlaldavha_r_r_q_q
|
|
inst_vrmlaldavhx :: inst_vrmlaldavhx_r_r_q_q
|
|
emit_vrmlaldavhx :: emit_vrmlaldavhx_r_r_q_q
|
|
inst_vrmlaldavhax :: inst_vrmlaldavhax_r_r_q_q
|
|
emit_vrmlaldavhax :: emit_vrmlaldavhax_r_r_q_q
|
|
inst_vrmlsldavh :: inst_vrmlsldavh_r_r_q_q
|
|
emit_vrmlsldavh :: emit_vrmlsldavh_r_r_q_q
|
|
inst_vrmlsldavha :: inst_vrmlsldavha_r_r_q_q
|
|
emit_vrmlsldavha :: emit_vrmlsldavha_r_r_q_q
|
|
inst_vrmlsldavhx :: inst_vrmlsldavhx_r_r_q_q
|
|
emit_vrmlsldavhx :: emit_vrmlsldavhx_r_r_q_q
|
|
inst_vrmlsldavhax :: inst_vrmlsldavhax_r_r_q_q
|
|
emit_vrmlsldavhax :: emit_vrmlsldavhax_r_r_q_q
|
|
inst_vmlav :: inst_vmlav_r_q_q
|
|
emit_vmlav :: emit_vmlav_r_q_q
|
|
inst_vmlava :: inst_vmlava_r_q_q
|
|
emit_vmlava :: emit_vmlava_r_q_q
|
|
inst_vmlsv :: inst_vmlsv_r_q_q
|
|
emit_vmlsv :: emit_vmlsv_r_q_q
|
|
inst_vmlsva :: inst_vmlsva_r_q_q
|
|
emit_vmlsva :: emit_vmlsva_r_q_q
|
|
inst_vcmul :: inst_vcmul_q_q_q
|
|
emit_vcmul :: emit_vcmul_q_q_q
|
|
inst_vhcadd :: inst_vhcadd_q_q_q
|
|
emit_vhcadd :: emit_vhcadd_q_q_q
|
|
inst_vbrsr :: inst_vbrsr_q_q_r
|
|
emit_vbrsr :: emit_vbrsr_q_q_r
|
|
inst_vshlc :: inst_vshlc_q_r_imm5
|
|
emit_vshlc :: emit_vshlc_q_r_imm5
|
|
inst_vddup :: inst_vddup_q_r_imm
|
|
emit_vddup :: emit_vddup_q_r_imm
|
|
inst_vidup :: inst_vidup_q_r_imm
|
|
emit_vidup :: emit_vidup_q_r_imm
|
|
inst_vdwdup :: inst_vdwdup_q_r_r_imm
|
|
emit_vdwdup :: emit_vdwdup_q_r_r_imm
|
|
inst_viwdup :: inst_viwdup_q_r_r_imm
|
|
emit_viwdup :: emit_viwdup_q_r_r_imm
|
|
inst_vmovnb :: inst_vmovnb_q_q
|
|
emit_vmovnb :: emit_vmovnb_q_q
|
|
inst_vmovnt :: inst_vmovnt_q_q
|
|
emit_vmovnt :: emit_vmovnt_q_q
|
|
inst_vqmovnb :: inst_vqmovnb_q_q
|
|
emit_vqmovnb :: emit_vqmovnb_q_q
|
|
inst_vqmovnt :: inst_vqmovnt_q_q
|
|
emit_vqmovnt :: emit_vqmovnt_q_q
|
|
inst_vqmovunb :: inst_vqmovunb_q_q
|
|
emit_vqmovunb :: emit_vqmovunb_q_q
|
|
inst_vqmovunt :: inst_vqmovunt_q_q
|
|
emit_vqmovunt :: emit_vqmovunt_q_q
|
|
inst_vshllb :: inst_vshllb_q_q_imm5
|
|
emit_vshllb :: emit_vshllb_q_q_imm5
|
|
inst_vshllt :: inst_vshllt_q_q_imm5
|
|
emit_vshllt :: emit_vshllt_q_q_imm5
|
|
inst_vmullb :: inst_vmullb_q_q_q
|
|
emit_vmullb :: emit_vmullb_q_q_q
|
|
inst_vmullt :: inst_vmullt_q_q_q
|
|
emit_vmullt :: emit_vmullt_q_q_q
|
|
inst_vmlalb :: inst_vmlalb_q_q_q
|
|
emit_vmlalb :: emit_vmlalb_q_q_q
|
|
inst_vmlalt :: inst_vmlalt_q_q_q
|
|
emit_vmlalt :: emit_vmlalt_q_q_q
|
|
inst_vmlslb :: inst_vmlslb_q_q_q
|
|
emit_vmlslb :: emit_vmlslb_q_q_q
|
|
inst_vmlslt :: inst_vmlslt_q_q_q
|
|
emit_vmlslt :: emit_vmlslt_q_q_q
|
|
inst_vshrnb :: inst_vshrnb_q_q_imm5
|
|
emit_vshrnb :: emit_vshrnb_q_q_imm5
|
|
inst_vshrnt :: inst_vshrnt_q_q_imm5
|
|
emit_vshrnt :: emit_vshrnt_q_q_imm5
|
|
inst_vrshrnb :: inst_vrshrnb_q_q_imm5
|
|
emit_vrshrnb :: emit_vrshrnb_q_q_imm5
|
|
inst_vrshrnt :: inst_vrshrnt_q_q_imm5
|
|
emit_vrshrnt :: emit_vrshrnt_q_q_imm5
|
|
inst_vqshrnb :: inst_vqshrnb_q_q_imm5
|
|
emit_vqshrnb :: emit_vqshrnb_q_q_imm5
|
|
inst_vqshrnt :: inst_vqshrnt_q_q_imm5
|
|
emit_vqshrnt :: emit_vqshrnt_q_q_imm5
|
|
inst_vqrshrnb :: inst_vqrshrnb_q_q_imm5
|
|
emit_vqrshrnb :: emit_vqrshrnb_q_q_imm5
|
|
inst_vqrshrnt :: inst_vqrshrnt_q_q_imm5
|
|
emit_vqrshrnt :: emit_vqrshrnt_q_q_imm5
|
|
inst_vqshrunb :: inst_vqshrunb_q_q_imm5
|
|
emit_vqshrunb :: emit_vqshrunb_q_q_imm5
|
|
inst_vqshrunt :: inst_vqshrunt_q_q_imm5
|
|
emit_vqshrunt :: emit_vqshrunt_q_q_imm5
|
|
inst_vqrshrunb :: inst_vqrshrunb_q_q_imm5
|
|
emit_vqrshrunb :: emit_vqrshrunb_q_q_imm5
|
|
inst_vqrshrunt :: inst_vqrshrunt_q_q_imm5
|
|
emit_vqrshrunt :: emit_vqrshrunt_q_q_imm5
|
|
inst_vmov_q_r :: inst_vmov_q_r_qlane_r
|
|
emit_vmov_q_r :: emit_vmov_q_r_qlane_r
|
|
inst_vmov_r_q :: inst_vmov_r_q_r_qlane
|
|
emit_vmov_r_q :: emit_vmov_r_q_r_qlane
|
|
inst_vmov_2gpr_q :: inst_vmov_2gpr_q_qlane_qlane_r_r
|
|
emit_vmov_2gpr_q :: emit_vmov_2gpr_q_qlane_qlane_r_r
|
|
inst_vqdmladh :: inst_vqdmladh_q_q_q
|
|
emit_vqdmladh :: emit_vqdmladh_q_q_q
|
|
inst_vqdmladhx :: inst_vqdmladhx_q_q_q
|
|
emit_vqdmladhx :: emit_vqdmladhx_q_q_q
|
|
inst_vqdmlsdh :: inst_vqdmlsdh_q_q_q
|
|
emit_vqdmlsdh :: emit_vqdmlsdh_q_q_q
|
|
inst_vqdmlsdhx :: inst_vqdmlsdhx_q_q_q
|
|
emit_vqdmlsdhx :: emit_vqdmlsdhx_q_q_q
|
|
inst_vqrdmladh :: inst_vqrdmladh_q_q_q
|
|
emit_vqrdmladh :: emit_vqrdmladh_q_q_q
|
|
inst_vqrdmladhx :: inst_vqrdmladhx_q_q_q
|
|
emit_vqrdmladhx :: emit_vqrdmladhx_q_q_q
|
|
inst_vqrdmlsdh :: inst_vqrdmlsdh_q_q_q
|
|
emit_vqrdmlsdh :: emit_vqrdmlsdh_q_q_q
|
|
inst_vqrdmlsdhx :: inst_vqrdmlsdhx_q_q_q
|
|
emit_vqrdmlsdhx :: emit_vqrdmlsdhx_q_q_q
|
|
inst_vhcadd_sat :: inst_vhcadd_sat_q_q_q_imm
|
|
emit_vhcadd_sat :: emit_vhcadd_sat_q_q_q_imm
|
|
inst_vcmla_mve :: inst_vcmla_mve_q_q_q_imm
|
|
emit_vcmla_mve :: emit_vcmla_mve_q_q_q_imm
|
|
inst_vldrb :: inst_vldrb_q_mem
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emit_vldrb :: emit_vldrb_q_mem
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inst_vldrh :: inst_vldrh_q_mem
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emit_vldrh :: emit_vldrh_q_mem
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inst_vldrw :: inst_vldrw_q_mem
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emit_vldrw :: emit_vldrw_q_mem
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inst_vldrd :: inst_vldrd_q_mem
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emit_vldrd :: emit_vldrd_q_mem
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|
inst_vstrb :: inst_vstrb_q_mem
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|
emit_vstrb :: emit_vstrb_q_mem
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|
inst_vstrh :: inst_vstrh_q_mem
|
|
emit_vstrh :: emit_vstrh_q_mem
|
|
inst_vstrw :: inst_vstrw_q_mem
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|
emit_vstrw :: emit_vstrw_q_mem
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|
inst_vstrd :: inst_vstrd_q_mem
|
|
emit_vstrd :: emit_vstrd_q_mem
|
|
inst_vld20 :: inst_vld20_qlist_mem
|
|
emit_vld20 :: emit_vld20_qlist_mem
|
|
inst_vld21 :: inst_vld21_qlist_mem
|
|
emit_vld21 :: emit_vld21_qlist_mem
|
|
inst_vld40 :: inst_vld40_qlist_mem
|
|
emit_vld40 :: emit_vld40_qlist_mem
|
|
inst_vld41 :: inst_vld41_qlist_mem
|
|
emit_vld41 :: emit_vld41_qlist_mem
|
|
inst_vld42 :: inst_vld42_qlist_mem
|
|
emit_vld42 :: emit_vld42_qlist_mem
|
|
inst_vld43 :: inst_vld43_qlist_mem
|
|
emit_vld43 :: emit_vld43_qlist_mem
|
|
inst_vst20 :: inst_vst20_qlist_mem
|
|
emit_vst20 :: emit_vst20_qlist_mem
|
|
inst_vst21 :: inst_vst21_qlist_mem
|
|
emit_vst21 :: emit_vst21_qlist_mem
|
|
inst_vst40 :: inst_vst40_qlist_mem
|
|
emit_vst40 :: emit_vst40_qlist_mem
|
|
inst_vst41 :: inst_vst41_qlist_mem
|
|
emit_vst41 :: emit_vst41_qlist_mem
|
|
inst_vst42 :: inst_vst42_qlist_mem
|
|
emit_vst42 :: emit_vst42_qlist_mem
|
|
inst_vst43 :: inst_vst43_qlist_mem
|
|
emit_vst43 :: emit_vst43_qlist_mem
|