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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
244 lines
9.0 KiB
Odin
244 lines
9.0 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm32_tests
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import "core:fmt"
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import a "../"
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// =============================================================================
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// AArch32 ENCODING_TABLE sweep
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// =============================================================================
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//
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// For every entry in ENCODING_TABLE, this builds a canonical word with safe
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// operand fills, decodes it, verifies the decoder picked the right mnemonic,
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// and re-encodes the decoded Instruction to verify pack/unpack are mutual
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// inverses on the masked bits.
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//
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// What this catches:
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// * Bucket misses: decoder fails to find the entry from its own canonical
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// bits. Implies the dispatch index is missing a bucket for this form.
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// * Wrong-entry decode: bucket has the entry but a different entry's mask
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// happens to also match.
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// * Pack/unpack asymmetry: decoder returns operands that, when re-encoded,
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// produce a different bit pattern (off-by-one in a field shift, wrong
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// sign handling, etc.).
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Sweep_Stats :: struct {
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total: int,
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ok: int,
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fail_decode: int, // decoder returned INVALID
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fail_mnemonic: int, // decoded a different mnemonic
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fail_reencode: int, // re-encoded word doesn't match (masked)
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fail_encode: int, // re-encode itself failed
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}
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run_sweep_tests :: proc() {
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fmt.println("\n==== ENCODING_TABLE sweep ====")
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a32_stats, t32_stats, t16_stats: Sweep_Stats
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// Cap the per-bucket failure printing so a wholesale regression doesn't
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// wallpaper the test output.
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max_fail_print :: 80
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failed_examples: int
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only_print_kind: string = ""
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for mn in a.Mnemonic {
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_run := a.ENCODE_RUNS[u16(mn)]
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forms := a.ENCODE_FORMS[_run.start:][:_run.count]
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for &f, idx in forms {
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ilen := a.inst_size_from_bits(f.bits, f.mode)
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// Canonical word: form.bits | safe-fill operand bits.
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word := f.bits
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for _, k in f.enc { word |= sweep_safe_fill(f.enc[k]) }
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// Operand-type-driven extras: GPR_RSR needs a non-zero Rs in bits
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// 11..8 to disambiguate from GPR_SHIFTED on decode/re-encode; the
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// base bits already set bit 4 (the RSR flag), but Rs=0 would alias
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// with R0 and the shape_matches predicate requires shift_amt != 0.
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for _, k in f.enc {
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if f.ops[k] == .GPR_RSR && (f.enc[k] == .RM_A32 || f.enc[k] == .RM_T32) {
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word |= u32(4) << 8
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}
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}
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// Bake AL cond for conditional A32.
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if f.mode == .A32 && (f.mask >> 28) == 0 {
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word = (word & 0x0FFFFFFF) | (0xE << 28)
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}
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stats := &a32_stats
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if f.mode != .A32 { stats = ilen == 4 ? &t32_stats : &t16_stats }
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stats.total += 1
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// Serialize to bytes per mode/ilen.
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buf: [4]u8
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if f.mode == .A32 {
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buf[0] = u8(word); buf[1] = u8(word >> 8)
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buf[2] = u8(word >> 16); buf[3] = u8(word >> 24)
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} else if ilen == 4 {
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hi := u16(word >> 16); lo := u16(word & 0xFFFF)
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buf[0] = u8(hi); buf[1] = u8(hi >> 8)
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buf[2] = u8(lo); buf[3] = u8(lo >> 8)
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} else {
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v := u16(word & 0xFFFF)
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buf[0] = u8(v); buf[1] = u8(v >> 8)
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}
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n := int(ilen)
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relocs := []a.Relocation{}
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insts: [dynamic]a.Instruction
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info: [dynamic]a.Instruction_Info
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label_defs: [dynamic]a.Label_Definition
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errors: [dynamic]a.Error
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defer { delete(insts); delete(info); delete(label_defs); delete(errors) }
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a.decode(buf[:n], relocs, &insts, &info, &label_defs, &errors, f.mode)
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if len(insts) == 0 || insts[0].mnemonic == .INVALID {
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stats.fail_decode += 1
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if failed_examples < max_fail_print && (only_print_kind == "" || only_print_kind == "decode") {
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fmt.printf(" [decode ] %v[%d] %08X mode=%v ilen=%d mask=%08X bits=%08X\n",
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mn, idx, word, f.mode, ilen, f.mask, f.bits)
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failed_examples += 1
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}
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continue
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}
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// Mnemonic mismatch is acceptable IF the decoded mnemonic
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// re-encodes to the same masked bits (a legitimate alias — e.g.
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// MOV+shift is canonically LSL). We defer the verdict to the
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// bytes-roundtrip check below; track for diagnostics only.
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mnem_alias := insts[0].mnemonic != mn
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// Re-encode and verify masked bits.
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ren_relocs: [dynamic]a.Relocation
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ren_errors: [dynamic]a.Error
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out: [4]u8
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defer { delete(ren_relocs); delete(ren_errors) }
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res := a.encode(insts[:], label_defs[:], out[:], &ren_relocs, &ren_errors, resolve=false)
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if !res.success {
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stats.fail_encode += 1
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if failed_examples < max_fail_print && (only_print_kind == "" || only_print_kind == "re-enc") {
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fmt.printf(" [re-enc ] %v[%d] %08X re-encode failed\n", mn, idx, word)
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failed_examples += 1
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}
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continue
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}
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// Reassemble the produced word for comparison.
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word2: u32
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if f.mode == .A32 {
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word2 = u32(out[0]) | u32(out[1]) << 8 | u32(out[2]) << 16 | u32(out[3]) << 24
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} else if ilen == 4 {
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hi := u32(out[0]) | u32(out[1]) << 8
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lo := u32(out[2]) | u32(out[3]) << 8
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word2 = (hi << 16) | lo
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} else {
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word2 = u32(out[0]) | u32(out[1]) << 8
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}
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if (word2 & f.mask) != (word & f.mask) {
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if mnem_alias { stats.fail_mnemonic += 1 } else { stats.fail_reencode += 1 }
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if failed_examples < max_fail_print && (only_print_kind == "" || only_print_kind == "reenc!=") {
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fmt.printf(" [reenc!= ] %v[%d] in %08X out %08X mask %08X (xor %08X)\n",
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mn, idx, word, word2, f.mask, (word ~ word2) & f.mask)
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failed_examples += 1
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}
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continue
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}
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stats.ok += 1
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}
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}
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report :: proc(name: string, s: ^Sweep_Stats) {
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fmt.printf(" %s: %d total | ok=%d decode=%d mnem=%d enc=%d reenc=%d\n",
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name, s.total, s.ok,
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s.fail_decode, s.fail_mnemonic, s.fail_encode, s.fail_reencode)
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}
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report("A32", &a32_stats)
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report("T32", &t32_stats)
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report("T16", &t16_stats)
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grand_total := a32_stats.total + t32_stats.total + t16_stats.total
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grand_ok := a32_stats.ok + t32_stats.ok + t16_stats.ok
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grand_fail := grand_total - grand_ok
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fmt.printf("\n==> arm32 sweep: %d / %d ok (%.1f%%), %d failed\n",
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grand_ok, grand_total, 100.0 * f32(grand_ok) / f32(grand_total), grand_fail)
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if grand_fail > 0 { fail_count += grand_fail }
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}
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// -----------------------------------------------------------------------------
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// Safe-fill operand bits per encoding (mirror of tools/dump_verify_input.odin)
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// -----------------------------------------------------------------------------
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//
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// Distinct registers per role so a mis-shifted field corrupts the output
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// instead of accidentally aliasing another register's slot.
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@(private="file")
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sweep_safe_fill :: proc(enc: a.Operand_Encoding) -> u32 {
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#partial switch enc {
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// ---- A32 GPR slots ----
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case .RD: return u32(1) << 12
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case .RN_A32: return u32(2) << 16
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case .RM_A32: return u32(3)
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case .RS_A32: return u32(4) << 8
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case .RT_A32: return u32(1) << 12
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case .RT2_A32: return u32(2) << 16
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case .RA_A32: return u32(5) << 12
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case .RDLO_A32: return u32(1) << 12
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case .RDHI_A32: return u32(2) << 16
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// ---- T32 GPR slots ----
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case .RD_T32: return u32(1) << 8
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case .RN_T32: return u32(2) << 16
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// Some MVE entries fix the LSB of Rm (bit 0) to zero, so the canonical
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// word for those forms must use an even-numbered Rm (R2 = 0010). Older
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// safe-fills used R3 here, which collided with the parity constraint.
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case .RM_T32: return u32(2)
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case .RT_T32: return u32(1) << 12
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case .RT2_T32: return u32(2) << 8
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case .RA_T32: return u32(5) << 12
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// ---- T16 GPR slots ----
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case .RD_T16_LO: return 1
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case .RM_T16_LO, .RN_T16_LO: return u32(2) << 3
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case .RD_T16_HI: return 1
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case .RM_T16_HI: return u32(2) << 3
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// ---- VFP/NEON split-register fields (even Q values for MVE compat) ----
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case .VD_S, .VD_D: return u32(1) << 12
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case .VD_Q: return u32(2) << 12
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case .VN_S, .VN_D: return u32(2) << 16
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case .VN_Q: return u32(4) << 16
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case .VM_S, .VM_D: return u32(3)
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case .VM_Q: return u32(6)
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// ---- MVE Q regs ----
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case .QD_MVE: return u32(1) << 13
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case .QN_MVE: return u32(2) << 17
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case .QM_MVE: return u32(3) << 1
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// ---- Memory ----
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case .MEM_IMM12_OFFSET, .MEM_IMM8_OFFSET,
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.MEM_PRE_INDEX, .MEM_POST_INDEX:
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return (u32(4) << 16) | (u32(1) << 23)
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case .MEM_REG_OFFSET, .MEM_DOUBLEREG:
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// Include Rm at bits 3..0 so the resulting Memory has index != R0,
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// letting the encoder pick the register-offset form on round-trip.
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return (u32(4) << 16) | (u32(1) << 23) | u32(3)
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case .MEM_LITERAL:
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return u32(1) << 23
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// ---- Register lists ----
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case .VFP_S_LIST, .VFP_D_LIST: return 4
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case .A32_REG_LIST: return 0x0030
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// ---- Coprocessor ----
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case .COPROC_NUM_FIELD: return u32(15) << 8
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case .COPROC_CRN_FIELD: return u32(1) << 16
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case .COPROC_CRM_FIELD: return 1
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// ---- Misc ----
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case .BARRIER_TYPE: return 0xF
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case .PSR_FIELD_MASK: return u32(0xF) << 16
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case .NEON_SHIFT_IMM6: return u32(12) << 16
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case .NEON_SHIFT_IMM3: return u32(1) << 16
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}
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return 0
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}
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