mirror of
https://github.com/odin-lang/Odin.git
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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
264 lines
11 KiB
Odin
264 lines
11 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mips_tests
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// Spot-check that ENCODING_TABLE entries are present and have the
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// known canonical bit patterns. Validates one entry from each major
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// section of the table.
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//
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// Run with: odin run mips/tests
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import "core:fmt"
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import "core:os"
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import mips "../"
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@(private="file") passes := 0
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@(private="file") failures := 0
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check :: proc(name: string, m: mips.Mnemonic, want_bits, want_mask: u32) {
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r := mips.ENCODE_RUNS[u16(m)]
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encs := mips.ENCODE_FORMS[r.start:][:r.count]
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if len(encs) == 0 {
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fmt.printfln(" [FAIL] %s: no encoding in table", name)
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failures += 1
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return
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}
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e := encs[0]
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if e.bits != want_bits || e.mask != want_mask {
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fmt.printfln(" [FAIL] %s: got bits=%08x mask=%08x; want bits=%08x mask=%08x",
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name, e.bits, e.mask, want_bits, want_mask)
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failures += 1
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return
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}
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fmt.printfln(" [ok] %-10s %08x / %08x (feature=%v)", name, e.bits, e.mask, e.feature)
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passes += 1
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}
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main :: proc() {
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fmt.println("=== MIPS encoding-table spot checks ===")
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// MIPS I core
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check("ADD", .ADD, 0x00000020, 0xFC0007FF)
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check("ADDI", .ADDI, 0x20000000, 0xFC000000)
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check("LW", .LW, 0x8C000000, 0xFC000000)
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check("SW", .SW, 0xAC000000, 0xFC000000)
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check("BEQ", .BEQ, 0x10000000, 0xFC000000)
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check("BLTZ", .BLTZ, 0x04000000, 0xFC1F0000)
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check("J", .J, 0x08000000, 0xFC000000)
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check("JR", .JR, 0x00000008, 0xFC1FFFFF)
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check("MULT", .MULT, 0x00000018, 0xFC00FFFF)
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check("MFHI", .MFHI, 0x00000010, 0xFFFF07FF)
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check("SLL", .SLL, 0x00000000, 0xFFE0003F)
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check("NOP", .NOP, 0x00000000, 0xFFFFFFFF)
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check("LUI", .LUI, 0x3C000000, 0xFFE00000)
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check("SYSCALL", .SYSCALL, 0x0000000C, 0xFC00003F)
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// MIPS II
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check("LL", .LL, 0xC0000000, 0xFC000000)
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check("BEQL", .BEQL, 0x50000000, 0xFC000000)
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// MIPS III
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check("DADD", .DADD, 0x0000002C, 0xFC0007FF)
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check("LD", .LD, 0xDC000000, 0xFC000000)
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// MIPS IV
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check("MOVN", .MOVN, 0x0000000B, 0xFC0007FF)
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// MIPS32 R1/R2
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check("MUL", .MUL, 0x70000002, 0xFC0007FF)
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check("CLZ", .CLZ, 0x70000020, 0xFC1F07FF)
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check("EXT", .EXT, 0x7C000000, 0xFC00003F)
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check("SEB", .SEB, 0x7C000420, 0xFFE007FF)
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check("ROTR", .ROTR, 0x00200002, 0xFFE0003F)
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check("ERET", .ERET, 0x42000018, 0xFFFFFFFF)
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// FPU base
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check("ADD.S", .ADD_S, 0x46000000, 0xFFE0003F)
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check("MUL.D", .MUL_D, 0x46200002, 0xFFE0003F)
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check("ABS.S", .ABS_S, 0x46000005, 0xFFFF003F)
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check("SQRT.D", .SQRT_D, 0x46200004, 0xFFFF003F)
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check("CVT.D.S", .CVT_D_S, 0x46000021, 0xFFFF003F)
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check("MFC1", .MFC1, 0x44000000, 0xFFE007FF)
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check("LWC1", .LWC1, 0xC4000000, 0xFC000000)
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check("BC1F", .BC1F, 0x45000000, 0xFFE30000)
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check("BC1T", .BC1T, 0x45010000, 0xFFE30000)
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// FP compares
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check("C.F.S", .C_F_S, 0x46000030, 0xFFE000FF)
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check("C.EQ.S", .C_EQ_S, 0x46000032, 0xFFE000FF)
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check("C.LT.D", .C_LT_D, 0x4620003C, 0xFFE000FF)
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check("C.NGT.S", .C_NGT_S, 0x4600003F, 0xFFE000FF)
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check("C.EQ.PS", .C_EQ_PS, 0x46C00032, 0xFFE000FF)
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// COP0
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check("MFC0", .MFC0, 0x40000000, 0xFFE007F8)
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check("TLBP", .TLBP, 0x42000008, 0xFFFFFFFF)
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check("CACHE", .CACHE, 0xBC000000, 0xFC000000)
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// PS1 GTE
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check("RTPS", .RTPS, 0x4A000001, 0xFE00003F)
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check("NCLIP", .NCLIP, 0x4A000006, 0xFE00003F)
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check("RTPT", .RTPT, 0x4A000030, 0xFE00003F)
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check("AVSZ3", .AVSZ3, 0x4A00002D, 0xFE00003F)
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check("MFC2", .MFC2, 0x48000000, 0xFFE007FF)
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// PS2 MMI
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check("LQ", .LQ, 0x78000000, 0xFC000000)
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check("SQ", .SQ, 0x7C000000, 0xFC000000)
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check("MFHI1", .MFHI1, 0x70000010, 0xFFFF07FF)
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check("PADDB", .PADDB, 0x70000208, 0xFC0007FF)
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check("PADDW", .PADDW, 0x70000008, 0xFC0007FF)
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check("PMULTW", .PMULTW, 0x70000309, 0xFC0007FF)
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check("PMFHI", .PMFHI, 0x70000209, 0xFFFF07FF)
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check("PINTOH", .PINTOH, 0x700002A9, 0xFC0007FF)
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check("MFSA", .MFSA, 0x00000028, 0xFFFF07FF)
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// MIPS32 R6
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check("BC", .BC, 0xC8000000, 0xFC000000)
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check("BALC", .BALC, 0xE8000000, 0xFC000000)
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check("JIC", .JIC, 0xD8000000, 0xFFE00000)
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check("BEQZC", .BEQZC, 0xD8000000, 0xFC000000)
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check("AUI", .AUI, 0x3C000000, 0xFC000000)
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check("MUH", .MUH, 0x000000D8, 0xFC0007FF)
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check("MODU", .MODU, 0x000000DB, 0xFC0007FF)
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check("LSA", .LSA, 0x00000005, 0xFC00071F)
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check("SELEQZ", .SELEQZ, 0x00000035, 0xFC0007FF)
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check("BITSWAP", .BITSWAP, 0x7C000020, 0xFFE007FF)
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check("BC1EQZ", .BC1EQZ, 0x45200000, 0xFFE00000)
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check("CRC32B", .CRC32B, 0x7C00000F, 0xFC00F8FF)
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check("CRC32CD", .CRC32CD, 0x7C00034F, 0xFC00F8FF)
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// MIPS DSP ASE
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check("ADDU.QB", .ADDU_QB, 0x7C000010, 0xFC0007FF)
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check("ADDQ.PH", .ADDQ_PH, 0x7C000290, 0xFC0007FF)
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check("DPAQ.S.W.PH",.DPAQ_S_W_PH,0x7C000130, 0xFC0007FF)
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check("EXTR.W", .EXTR_W, 0x7C000038, 0xFC00073F)
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check("RDDSP", .RDDSP, 0x7C0004B8, 0xFC1F07FF)
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check("BITREV", .BITREV, 0x7C0006D2, 0xFFE007FF)
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check("LWX", .LWX, 0x7C00000A, 0xFC0007FF)
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check("INSV", .INSV, 0x7C00000C, 0xFC00FFFF)
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check("BPOSGE32", .BPOSGE32, 0x041C0000, 0xFFFF0000)
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// ---- MSA (MIPS SIMD Architecture) -----------------------------------
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check("ADDV.B", .ADDV_B, 0x7800000E, 0xFFE0003F)
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check("ADDV.W", .ADDV_W, 0x7840000E, 0xFFE0003F)
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check("SUBV.D", .SUBV_D, 0x78E0000E, 0xFFE0003F)
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check("MULV.W", .MULV_W, 0x78400012, 0xFFE0003F)
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check("AND.V", .AND_V, 0x7800001E, 0xFFE0003F)
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check("XOR.V", .XOR_V, 0x7860001E, 0xFFE0003F)
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check("CEQ.B", .CEQ_B, 0x7800000F, 0xFFE0003F)
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check("MIN_S.W", .MIN_S_W, 0x7A40000E, 0xFFE0003F)
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check("MAX_U.D", .MAX_U_D, 0x79E0000E, 0xFFE0003F)
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check("LD.W", .LD_W, 0x78000022, 0xFC00003F)
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check("ST.D", .ST_D, 0x78000027, 0xFC00003F)
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// ---- VFPU (PSP Allegrex) control / no-operand ops -------------------
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check("VNOP", .VNOP, 0xFFFF0000, 0xFFFFFFFF)
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check("VSYNC", .VSYNC, 0xFFFF0320, 0xFFFFFFFF)
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check("VFLUSH", .VFLUSH, 0xFFFF040D, 0xFFFFFFFF)
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// ---- VFPU arithmetic ------------------------------------------------
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check("VADD.S", .VADD_S, 0x60000000, 0xFF808080)
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check("VADD.P", .VADD_P, 0x60000080, 0xFF808080)
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check("VADD.T", .VADD_T, 0x60008000, 0xFF808080)
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check("VADD.Q", .VADD_Q, 0x60008080, 0xFF808080)
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check("VSUB.S", .VSUB_S, 0x60800000, 0xFF808080)
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check("VMUL.S", .VMUL_S, 0x64000000, 0xFF808080)
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check("VMUL.Q", .VMUL_Q, 0x64008080, 0xFF808080)
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check("VDIV.S", .VDIV_S, 0x63800000, 0xFF808080)
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check("VABS.S", .VABS_S, 0xD0010000, 0xFFFF8080)
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check("VNEG.Q", .VNEG_Q, 0xD0028080, 0xFFFF8080)
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check("VMOV.S", .VMOV_S, 0xD0000000, 0xFFFF8080)
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check("VSQRT.S", .VSQRT_S, 0xD0160000, 0xFFFF8080)
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check("VRCP.P", .VRCP_P, 0xD0100080, 0xFFFF8080)
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check("VRSQ.T", .VRSQ_T, 0xD0118000, 0xFFFF8080)
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check("VMIN.Q", .VMIN_Q, 0x6D008080, 0xFF808080)
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check("VMAX.S", .VMAX_S, 0x6D800000, 0xFF808080)
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check("VSCL.Q", .VSCL_Q, 0x65008080, 0xFF808080)
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check("VDOT.Q", .VDOT_Q, 0x64808080, 0xFF808080)
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// ---- VFPU memory + prefix + GPR-bridge ------------------------------
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check("LV.S", .LV_S, 0xC8000000, 0xFC000000)
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check("LV.Q", .LV_Q, 0xD8000000, 0xFC000000)
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check("SV.S", .SV_S, 0xE8000000, 0xFC000000)
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check("SV.Q", .SV_Q, 0xF8000000, 0xFC000000)
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check("VCST.S", .VCST_S, 0xD0600000, 0xFFE08080)
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check("VPFXS", .VPFXS, 0xDC000000, 0xFFF00000)
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check("VPFXT", .VPFXT, 0xDD000000, 0xFFF00000)
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check("VPFXD", .VPFXD, 0xDE000000, 0xFFF00000)
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check("MFV", .MFV, 0x48600000, 0xFFE00080)
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check("MTV", .MTV, 0x48E00000, 0xFFE00080)
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// ---- VFPU transcendentals -------------------------------------------
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check("VSIN.S", .VSIN_S, 0xD0120000, 0xFFFF8080)
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check("VCOS.S", .VCOS_S, 0xD0130000, 0xFFFF8080)
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check("VEXP2.S", .VEXP2_S, 0xD0140000, 0xFFFF8080)
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check("VLOG2.S", .VLOG2_S, 0xD0150000, 0xFFFF8080)
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check("VASIN.S", .VASIN_S, 0xD0170000, 0xFFFF8080)
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check("VNRCP.S", .VNRCP_S, 0xD0180000, 0xFFFF8080)
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check("VNSIN.S", .VNSIN_S, 0xD01A0000, 0xFFFF8080)
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check("VREXP2.S", .VREXP2_S, 0xD01C0000, 0xFFFF8080)
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check("VSGN.S", .VSGN_S, 0xD04A0000, 0xFFFF8080)
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// ---- VFPU conversions -----------------------------------------------
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check("VF2IN.S", .VF2IN_S, 0xD2000000, 0xFFE08080)
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check("VF2IZ.Q", .VF2IZ_Q, 0xD2208080, 0xFFE08080)
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check("VF2IU.T", .VF2IU_T, 0xD2408000, 0xFFE08080)
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check("VF2ID.P", .VF2ID_P, 0xD2600080, 0xFFE08080)
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check("VI2F.S", .VI2F_S, 0xD2800000, 0xFFE08080)
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check("VF2H.P", .VF2H_P, 0xD0320080, 0xFFFF8080)
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check("VH2F.S", .VH2F_S, 0xD0330000, 0xFFFF8080)
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// ---- VFPU reductions ------------------------------------------------
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check("VFAD.Q", .VFAD_Q, 0xD0468080, 0xFFFF8080)
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check("VAVG.Q", .VAVG_Q, 0xD0478080, 0xFFFF8080)
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check("VHDP.Q", .VHDP_Q, 0x66008080, 0xFF808080)
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// ---- VFPU compare ---------------------------------------------------
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check("VCMP.S", .VCMP_S, 0x6C000000, 0xFF8080F0)
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check("VCMP.Q", .VCMP_Q, 0x6C008080, 0xFF8080F0)
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// ---- VFPU matrix ----------------------------------------------------
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check("VMMUL.P", .VMMUL_P, 0xF0000080, 0xFF808080)
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check("VMMUL.T", .VMMUL_T, 0xF0008000, 0xFF808080)
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check("VMMUL.Q", .VMMUL_Q, 0xF0008080, 0xFF808080)
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check("VTFM2.P", .VTFM2_P, 0xF0800080, 0xFF808080)
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check("VTFM4.Q", .VTFM4_Q, 0xF0808080, 0xFF808080)
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check("VHTFM2.P", .VHTFM2_P, 0xF0800000, 0xFF808080)
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check("VMSCL.Q", .VMSCL_Q, 0xF2008080, 0xFF808080)
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check("VMMOV.Q", .VMMOV_Q, 0xF3808080, 0xFFFF8080)
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check("VMIDT.Q", .VMIDT_Q, 0xF3838080, 0xFFFFFF80)
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check("VMZERO.Q", .VMZERO_Q, 0xF3868080, 0xFFFFFF80)
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check("VMONE.Q", .VMONE_Q, 0xF3878080, 0xFFFFFF80)
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// ---- VFPU cross / quaternion ----------------------------------------
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check("VCRS.T", .VCRS_T, 0x66808000, 0xFF808080)
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check("VQMUL.Q", .VQMUL_Q, 0xF2808080, 0xFF808080)
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// ---- VFPU control + branches ----------------------------------------
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check("MFVC", .MFVC, 0x48400000, 0xFFE00000)
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check("MTVC", .MTVC, 0x48C00000, 0xFFE00000)
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check("BVF", .BVF, 0x49000000, 0xFFE30000)
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check("BVT", .BVT, 0x49010000, 0xFFE30000)
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check("BVFL", .BVFL, 0x49020000, 0xFFE30000)
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check("BVTL", .BVTL, 0x49030000, 0xFFE30000)
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// ---- VFPU unaligned quad memory -------------------------------------
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check("LVL.Q", .LVL_Q, 0xD4000002, 0xFC000002)
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check("LVR.Q", .LVR_Q, 0xD4000000, 0xFC000002)
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check("SVL.Q", .SVL_Q, 0xF4000002, 0xFC000002)
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check("SVR.Q", .SVR_Q, 0xF4000000, 0xFC000002)
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// ---- VFPU integer/float immediate load ------------------------------
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check("VIIM.S", .VIIM_S, 0xDF000000, 0xFF800000)
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check("VFIM.S", .VFIM_S, 0xDF800000, 0xFF800000)
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fmt.println()
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fmt.printfln("==> table: %d passed, %d failed", passes, failures)
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if failures > 0 { os.exit(1) }
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run_encoder_tests()
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run_decoder_tests()
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run_printer_tests()
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}
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