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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
62 lines
1.8 KiB
Odin
62 lines
1.8 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mos65816
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// =============================================================================
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// W65C816S mnemonics
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// =============================================================================
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//
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// Carries over the NMOS 6502 base + the universal 65C02 additions (the
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// Rockwell bit ops RMB/SMB/BBR/BBS are NOT in the stock WDC 65816), plus
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// the ~27 mnemonics that are new to the 65816.
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Mnemonic :: enum u16 {
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INVALID = 0,
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// 6502 core
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ADC, AND, ASL,
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BIT, CMP, CPX, CPY,
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DEC, DEX, DEY, EOR,
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INC, INX, INY,
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LSR, ORA,
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ROL, ROR, SBC,
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LDA, LDX, LDY,
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STA, STX, STY,
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TAX, TAY, TSX, TXA, TXS, TYA,
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PHA, PHP, PLA, PLP,
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JMP, JSR, RTI, RTS,
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BRK, NOP,
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// Branches
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BCC, BCS, BEQ, BMI, BNE, BPL, BVC, BVS,
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// Flags
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CLC, CLD, CLI, CLV, SEC, SED, SEI,
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// 65C02 additions (carry over to 65816)
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BRA,
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STZ, TRB, TSB,
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PHX, PHY, PLX, PLY,
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STP, WAI,
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// 65816 new
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BRL, // 16-bit relative branch
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COP, // co-processor enable (interrupt)
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JML, // jump long (24-bit)
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JSL, // jump-to-subroutine long (24-bit)
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MVN, MVP, // block move negative / positive
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PEA, // push effective absolute address
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PEI, // push effective indirect address
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PER, // push effective PC-relative
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PHB, PHD, PHK, // push DBR / D / PBR
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PLB, PLD, // pull DBR / D
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REP, SEP, // reset / set status bits (immediate mask)
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RTL, // return long
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TCD, TDC, // A <-> D
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TCS, TSC, // A <-> S
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TXY, TYX, // X <-> Y
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WDM, // reserved (assembles as 2-byte no-op)
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XBA, // exchange A halves (B <-> A)
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XCE, // exchange Carry and Emulation flags
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}
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