mirror of
https://github.com/odin-lang/Odin.git
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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
303 lines
11 KiB
Odin
303 lines
11 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_ppc
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import "../isa"
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// =============================================================================
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// PowerPC DECODER
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// =============================================================================
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//
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// PowerPC base instructions are 4 bytes; Power ISA 3.1 prefixed are 8.
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// A prefixed instruction starts with a prefix word whose primary opcode is 1
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// (bits 26..31 LSB = 0b000001 = 0x04 in the top byte BE).
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//
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// Operation per instruction:
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// 1. Read 4 BE bytes -> word
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// 2. Index into DECODE_INDEX by primary opcode (bits 26..31, 6 bits, 64 buckets)
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// 3. For each candidate entry in the bucket, test (word & mask) == bits
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// 4. On match, unpack operands and emit Instruction; branch operands emit
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// RELATIVE with absolute target byte offset.
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Instruction_Info :: struct {
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offset: u32,
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decode_entry: u16, // index into DECODE_ENTRIES (or 0 for no-match)
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_: u16,
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}
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#assert(size_of(Instruction_Info) == 8)
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decode :: proc(
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data: []u8,
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relocs: []Relocation,
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instructions: ^[dynamic]Instruction,
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inst_info: ^[dynamic]Instruction_Info,
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label_defs: ^[dynamic]Label_Definition,
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errors: ^[dynamic]Error,
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mode: Mode = .PPC32,
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) -> Result {
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n_bytes := u32(len(data)) & ~u32(3)
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errors_start := u32(len(errors))
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pending_branches: [dynamic]isa.Branch_Target
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defer delete(pending_branches)
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pc: u32 = 0
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for pc < n_bytes {
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if pc + 4 > n_bytes { break }
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word := read_u32_be(data, pc)
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// Detect prefixed instruction: primary opcode = 1.
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is_prefixed := (word >> 26) == 0x01
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ilen: u32 = 4
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suffix: u32 = 0
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if is_prefixed {
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if pc + 8 > n_bytes { break }
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suffix = read_u32_be(data, pc + 4)
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ilen = 8
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}
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inst: Instruction
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info: Instruction_Info
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info.offset = pc
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match_word := is_prefixed ? suffix : word
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prefix_word := is_prefixed ? word : 0
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if !find_and_decode(match_word, prefix_word, is_prefixed, mode, &inst, &info) {
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append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE})
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inst = Instruction{mnemonic = .INVALID, length = u8(ilen), mode = mode}
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} else {
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inst.length = u8(ilen)
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inst.mode = mode
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inst_idx := u32(len(instructions))
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for slot in 0..<inst.operand_count {
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op := &inst.ops[slot]
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if op.kind == .RELATIVE && op.relative >= 0 {
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// The unpacker stores PC-relative byte offsets; convert
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// to absolute target = pc + relative.
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target := u32(i32(pc) + i32(op.relative))
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append(&pending_branches, isa.Branch_Target{
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inst_idx = inst_idx,
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op_idx = slot,
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target = target,
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})
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}
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}
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}
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append(instructions, inst)
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append(inst_info, info)
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pc += ilen
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}
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isa.infer_labels_from_branches(pending_branches[:], pc, label_defs, relocs)
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return Result{byte_count = pc, success = u32(len(errors)) == errors_start}
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}
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// =============================================================================
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// Decode dispatch via two-level (primary, primary*256+xo) bucket tables
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// =============================================================================
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@(private="file")
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find_and_decode :: proc(word, prefix: u32, prefixed: bool, mode: Mode, inst: ^Instruction, info: ^Instruction_Info) -> bool {
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primary := (word >> 26) & 0x3F
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sub_key := primary * DECODE_SUB_BUCKETS + ((word >> 1) & 0xFF)
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sub_range := DECODE_INDEX_SUB[sub_key]
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if sub_range.count > 0 {
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if try_bucket(word, prefix, prefixed, mode, sub_range, inst, info) { return true }
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}
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primary_range := DECODE_INDEX_PRIMARY[primary]
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if primary_range.count > 0 {
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if try_bucket(word, prefix, prefixed, mode, primary_range, inst, info) { return true }
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}
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return false
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}
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@(private="file")
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try_bucket :: proc(word, prefix: u32, prefixed: bool, mode: Mode, r: Decode_Index, inst: ^Instruction, info: ^Instruction_Info) -> bool {
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base := int(r.start)
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cnt := int(r.count)
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for i in 0..<cnt {
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entry_idx := DECODE_BUCKET_LIST[base + i]
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e := &DECODE_ENTRIES[entry_idx]
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if (word & e.mask) != (e.bits & e.mask) { continue }
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if e.flags.prefixed != prefixed { continue }
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if e.mode == .PPC64 && mode == .PPC32 { continue }
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// For prefixed instructions, the PREFIX_BITS_TABLE entry must match
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// the prefix word's fixed bits (top 6 bits = primary opcode 1, plus
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// the 8-bit template at bits 24..21 LSB). Only the IMM18+R fields
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// (bits 0..18 LSB) are variable in the prefix.
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if prefixed {
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expected_prefix := PREFIX_BITS_TABLE[u16(e.mnemonic)]
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// Mask covers primary (bits 26..31) and template/R (bits 19..25).
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// IMM18 occupies bits 0..17 — leave those free.
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prefix_mask: u32 = 0xFFFC0000
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if (prefix & prefix_mask) != (expected_prefix & prefix_mask) { continue }
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}
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inst.mnemonic = e.mnemonic
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inst.operand_count = 0
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inst.form_id = DECODE_FORM_IDX[entry_idx] + 1
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info.decode_entry = u16(entry_idx)
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if e.flags.sets_cr0 && (word & 1) != 0 { inst.flags.sets_cr0 = true }
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if e.flags.has_oe && ((word >> 10) & 1) != 0 { inst.flags.has_oe = true }
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for k in 0..<4 {
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if e.enc[k] == .NONE && e.ops[k] == .NONE { break }
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if e.enc[k] == .NONE {
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inst.ops[k] = default_operand_for(e.ops[k])
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} else {
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inst.ops[k] = unpack_operand(word, e.enc[k], e.ops[k])
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}
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inst.operand_count = u8(k + 1)
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}
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return true
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}
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return false
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}
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@(private="file")
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default_operand_for :: proc(ot: Operand_Type) -> Operand {
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#partial switch ot {
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case .GPR, .GPR_OR_ZERO: return op_reg(R0)
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case .FPR: return op_reg(F0)
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case .VR: return op_reg(V0)
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case .VR128: return op_reg(vr128_reg(0))
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case .VSR: return op_reg(vs_reg(0))
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case .CR_FIELD, .CR_BIT: return op_reg(CR0)
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case .SPR: return op_reg(spr_reg(0))
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case .MEM: return op_mem(mem_d(R0, 0))
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case .REL: return op_rel_offset(0)
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case .IMM, .SIMM, .UIMM, .BO, .BH: return op_imm(0)
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}
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return op_imm(0)
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}
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// =============================================================================
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// Operand un-packers (inverse of pack_operand in encoder.odin)
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// =============================================================================
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@(private="file")
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unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Operand {
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#partial switch enc {
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// ---- Integer registers ----
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case .RT, .RS: return op_reg(Register(REG_GPR | u16((word >> 21) & 0x1F)))
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case .RA: return op_reg(Register(REG_GPR | u16((word >> 16) & 0x1F)))
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case .RB: return op_reg(Register(REG_GPR | u16((word >> 11) & 0x1F)))
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case .RC: return op_reg(Register(REG_GPR | u16((word >> 6) & 0x1F)))
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// ---- Floating-point ----
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case .FRT: return op_reg(Register(REG_FPR | u16((word >> 21) & 0x1F)))
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case .FRA: return op_reg(Register(REG_FPR | u16((word >> 16) & 0x1F)))
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case .FRB: return op_reg(Register(REG_FPR | u16((word >> 11) & 0x1F)))
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case .FRC: return op_reg(Register(REG_FPR | u16((word >> 6) & 0x1F)))
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// ---- AltiVec ----
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case .VRT: return op_reg(Register(REG_VR | u16((word >> 21) & 0x1F)))
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case .VRA: return op_reg(Register(REG_VR | u16((word >> 16) & 0x1F)))
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case .VRB: return op_reg(Register(REG_VR | u16((word >> 11) & 0x1F)))
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case .VRC: return op_reg(Register(REG_VR | u16((word >> 6) & 0x1F)))
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// ---- VSX ----
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case .XT:
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n := ((word >> 21) & 0x1F) | ((word & 1) << 5)
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return op_reg(vs_reg(u8(n)))
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case .XA:
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n := ((word >> 16) & 0x1F) | (((word >> 2) & 1) << 5)
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return op_reg(vs_reg(u8(n)))
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case .XB:
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n := ((word >> 11) & 0x1F) | (((word >> 1) & 1) << 5)
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return op_reg(vs_reg(u8(n)))
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case .XC:
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n := ((word >> 6) & 0x1F) | (((word >> 3) & 1) << 5)
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return op_reg(vs_reg(u8(n)))
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// ---- VMX128 (5-bit subset — see encoder for why we don't unpack VDh/VBh) ----
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case .VRT128: return op_reg(vr128_reg(u8((word >> 21) & 0x1F)))
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case .VRA128: return op_reg(vr128_reg(u8((word >> 16) & 0x1F)))
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case .VRB128: return op_reg(vr128_reg(u8((word >> 11) & 0x1F)))
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case .VRC128: return op_reg(vr128_reg(u8((word >> 6) & 0x1F)))
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// ---- Condition register fields ----
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case .BF: return op_reg(Register(REG_CR | u16((word >> 23) & 0x7)))
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case .BFA: return op_reg(Register(REG_CR | u16((word >> 18) & 0x7)))
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case .BT: return op_reg(Register(REG_CR | u16((word >> 21) & 0x1F)))
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case .BA: return op_reg(Register(REG_CR | u16((word >> 16) & 0x1F)))
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case .BB: return op_reg(Register(REG_CR | u16((word >> 11) & 0x1F)))
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case .BO_FIELD:
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n := (word >> 21) & 0x1F
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if ot == .CR_BIT { return op_reg(Register(REG_CR | u16(n))) }
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return op_imm(i64(n))
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case .BI_FIELD:
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n := (word >> 16) & 0x1F
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if ot == .CR_BIT { return op_reg(Register(REG_CR | u16(n))) }
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return op_imm(i64(n))
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case .BH_FIELD:
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n := (word >> 11) & 0x3
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if ot == .CR_BIT { return op_reg(Register(REG_CR | u16(n))) }
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return op_imm(i64(n))
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// ---- SPR (10-bit split with halves swapped) ----
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case .SPR_FIELD:
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n := ((word >> 11) & 0x1F) | (((word >> 16) & 0x1F) << 5)
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return op_reg(spr_reg(u16(n)))
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// ---- Immediates ----
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case .D16: return op_imm(i64(i16(word & 0xFFFF)))
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case .UI16: return op_imm(i64(u16(word & 0xFFFF)))
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case .DS14: return op_imm(i64(i16(word & 0xFFFC)))
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case .DQ12: return op_imm(i64(i16(word & 0xFFF0)))
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case .SH5: return op_imm(i64((word >> 11) & 0x1F))
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case .SH6:
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v := ((word >> 11) & 0x1F) | (((word >> 1) & 1) << 5)
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return op_imm(i64(v))
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case .MB5: return op_imm(i64((word >> 6) & 0x1F))
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case .ME5: return op_imm(i64((word >> 1) & 0x1F))
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case .MB6:
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v := ((word >> 6) & 0x1F) | (((word >> 5) & 1) << 5)
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return op_imm(i64(v))
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case .SIMM_5: return op_imm(i64(i32((word >> 16) & 0x1F) - i32((word >> 16) & 0x10) * 2))
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case .UIMM_5: return op_imm(i64((word >> 16) & 0x1F))
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case .UIMM_4: return op_imm(i64((word >> 16) & 0xF))
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case .UIMM_2: return op_imm(i64((word >> 16) & 0x3))
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case .FXM: return op_imm(i64((word >> 12) & 0xFF))
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case .L_FIELD: return op_imm(i64((word >> 21) & 0x1))
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case .TO_FIELD: return op_imm(i64((word >> 21) & 0x1F))
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case .NB_FIELD: return op_imm(i64((word >> 11) & 0x1F))
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case .SR_FIELD: return op_imm(i64((word >> 16) & 0xF))
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case .CRM: return op_imm(i64((word >> 12) & 0xFF))
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case .DCMX: return op_imm(i64((word >> 16) & 0x7F))
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// ---- Memory composites ----
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case .OFFSET_BASE_D:
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return op_mem(mem_d(Register(REG_GPR | u16((word >> 16) & 0x1F)),
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i64(i16(word & 0xFFFF))))
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case .OFFSET_BASE_DS:
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return op_mem(mem_d(Register(REG_GPR | u16((word >> 16) & 0x1F)),
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i64(i16(word & 0xFFFC))))
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case .OFFSET_BASE_DQ:
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return op_mem(mem_d(Register(REG_GPR | u16((word >> 16) & 0x1F)),
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i64(i16(word & 0xFFF0))))
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case .OFFSET_BASE_X, .OFFSET_VSX_X:
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return op_mem(mem_x(Register(REG_GPR | u16((word >> 16) & 0x1F)),
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Register(REG_GPR | u16((word >> 11) & 0x1F))))
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// ---- PC-relative ----
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case .BRANCH_LI:
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// 24-bit signed << 2 at bits 2..25 (sign-extend from bit 25).
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u := word & 0x03FFFFFC
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v := i32(u)
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if u & 0x02000000 != 0 { v = i32(u | 0xFC000000) }
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return op_rel_offset(i64(v))
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case .BRANCH_BD:
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// 14-bit signed << 2 at bits 2..15 (sign-extend from bit 15).
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u := word & 0xFFFC
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v := i32(u)
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if u & 0x8000 != 0 { v = i32(u | 0xFFFF0000) }
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return op_rel_offset(i64(v))
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}
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return op_imm(0)
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}
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