mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-19 16:42:33 +00:00
a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
448 lines
16 KiB
Odin
448 lines
16 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_ppc
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// =============================================================================
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// PowerPC ENCODER
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// =============================================================================
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//
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// Two-pass design (mirrors arm32/encoder.odin):
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//
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// PASS 1 - For each Instruction, find the first matching Encoding form
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// (by Mnemonic / mode / operand shape / flags), pack operand bits
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// onto the form's static `bits`, and emit 4 bytes (or 8 for
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// prefixed POWER10 ops). Branch operands emit Relocation entries
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// that PASS 2 resolves.
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// PASS 1.5 - Rewrite label_defs[] from instruction index to byte offset.
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// PASS 2 - Walk pending relocations and patch in scattered branch offsets.
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//
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// PowerPC instructions are big-endian on the wire (traditional). On
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// little-endian PPC64 (ppc64le), the bytes are simply byte-swapped per
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// instruction. The encoder produces BE bytes by default; callers can swap
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// post-hoc for LE targets.
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MAX_INST_SIZE :: 8 // prefixed instructions
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encode_max_code_size :: #force_inline proc "contextless" (n: int) -> int { return n * MAX_INST_SIZE }
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encode_max_relocation_count :: #force_inline proc "contextless" (n: int) -> int { return n }
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encode :: proc(
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instructions: []Instruction,
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label_defs: []Label_Definition,
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code: []u8,
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relocs: ^[dynamic]Relocation,
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errors: ^[dynamic]Error,
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resolve: bool = true,
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base_address: u64 = 0,
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) -> Result {
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n_inst := u32(len(instructions))
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if u32(len(code)) < n_inst * MAX_INST_SIZE {
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append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW})
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return Result{byte_count = 0, success = false}
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}
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errors_start := u32(len(errors))
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pending_start := u32(len(relocs))
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pc: u32 = 0
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inst_pc := make([]u32, n_inst, context.temp_allocator)
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// ---- PASS 1 ------------------------------------------------------------
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for i in 0..<n_inst {
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inst_pc[i] = pc
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inst := &instructions[i]
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ok := encode_one_inline(inst, pc, code, u16(i), relocs, errors)
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if !ok {
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return Result{byte_count = pc, success = false}
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}
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pc += u32(inst.length)
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}
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// ---- PASS 1.5: label instruction-idx -> byte offset --------------------
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for &ld in label_defs {
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if ld != LABEL_UNDEFINED {
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idx := u32(ld)
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if idx < n_inst {
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ld = Label_Definition(inst_pc[idx])
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} else {
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ld = LABEL_UNDEFINED
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}
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}
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}
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if !resolve {
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return Result{byte_count = pc, success = u32(len(errors)) == errors_start}
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}
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// ---- PASS 2: resolve relocations ---------------------------------------
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n_relocs := u32(len(relocs))
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write_idx := pending_start
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for read_idx in pending_start..<n_relocs {
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r := relocs[read_idx]
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if resolve_relocation_inline(code, label_defs, &r, base_address, errors) {
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continue
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}
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if write_idx != read_idx { relocs[write_idx] = r }
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write_idx += 1
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}
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if write_idx != n_relocs { resize(relocs, int(write_idx)) }
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return Result{byte_count = pc, success = u32(len(errors)) == errors_start}
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}
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// =============================================================================
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// Encode one instruction
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// =============================================================================
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@(private="file")
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encode_one_inline :: #force_inline proc(
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inst: ^Instruction,
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pc: u32,
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code: []u8,
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inst_idx: u16,
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relocs: ^[dynamic]Relocation,
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errors: ^[dynamic]Error,
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) -> bool {
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forms := encoding_forms(inst.mnemonic)
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if len(forms) == 0 {
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append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC})
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return false
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}
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form: ^Encoding
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// Form-id hint from the decoder's roundtrip (1-based).
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if inst.form_id != 0 && int(inst.form_id) - 1 < len(forms) {
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f := &forms[inst.form_id - 1]
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if encoding_matches_inline(inst, f) { form = f }
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}
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if form == nil {
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for &f in forms {
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if encoding_matches_inline(inst, &f) { form = &f; break }
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}
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}
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if form == nil {
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append(errors, Error{inst_idx = u32(inst_idx), code = .NO_MATCHING_ENCODING})
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return false
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}
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word := form.bits
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// Pack operand bits.
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for k in 0..<4 {
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if form.enc[k] != .NONE {
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word |= pack_operand_inline(&inst.ops[k], form.enc[k], pc, inst_idx, relocs, form)
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}
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}
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// Apply Rc / OE / LK / AA flag bits if user requested them and the form
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// supports them (the form's flags advertise availability).
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if inst.flags.sets_cr0 && form.flags.sets_cr0 { word |= 1 } // Rc at LSB 0
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if inst.flags.has_oe && form.flags.has_oe { word |= 1 << 10 } // OE at LSB 10
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if inst.flags.lk { word |= 1 } // LK at LSB 0 for branch forms
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if inst.flags.aa { word |= 1 << 1 } // AA at LSB 1 for branches
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// Emit bytes. PowerPC is big-endian on the wire.
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if form.flags.prefixed {
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prefix := PREFIX_BITS_TABLE[u16(inst.mnemonic)]
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write_u32_be(code, pc, prefix)
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write_u32_be(code, pc + 4, word)
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inst.length = 8
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} else {
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write_u32_be(code, pc, word)
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inst.length = 4
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}
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return true
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}
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// =============================================================================
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// Form matching: do the Operand kinds line up with the form's Operand_Type,
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// and does the form's mode + feature gate allow this Instruction?
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// =============================================================================
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@(private="file")
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encoding_matches_inline :: #force_inline proc "contextless" (inst: ^Instruction, form: ^Encoding) -> bool {
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// PPC32 entries are usable in either mode; PPC64 entries require .PPC64.
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if form.mode == .PPC64 && inst.mode == .PPC32 { return false }
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return operand_matches_inline(&inst.ops[0], form.ops[0]) &&
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operand_matches_inline(&inst.ops[1], form.ops[1]) &&
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operand_matches_inline(&inst.ops[2], form.ops[2]) &&
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operand_matches_inline(&inst.ops[3], form.ops[3])
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}
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@(private="file")
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operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Operand_Type) -> bool {
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#partial switch ot {
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case .NONE: return op.kind == .NONE
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case .GPR, .GPR_OR_ZERO:
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return op.kind == .REGISTER && reg_is_gpr(op.reg)
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case .FPR: return op.kind == .REGISTER && reg_is_fpr(op.reg)
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case .VR: return op.kind == .REGISTER && reg_is_vr(op.reg)
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case .VR128: return op.kind == .REGISTER && (reg_is_vr128(op.reg) || reg_is_vr(op.reg))
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case .VSR:
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// VSR slots accept both vs-registers and FPR/VR (they alias).
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return op.kind == .REGISTER && (reg_is_vsr(op.reg) || reg_is_fpr(op.reg) || reg_is_vr(op.reg))
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case .CR_FIELD:
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return op.kind == .REGISTER && reg_is_cr(op.reg)
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case .CR_BIT:
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// CR_BIT is a 5-bit CR-bit selector (0..31). It can be carried as
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// either a Register (REG_CR class, low byte = bit number) or as a
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// plain Immediate (bit number). The decoder always emits Register
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// form, but user code may construct either.
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return (op.kind == .REGISTER && reg_is_cr(op.reg)) || op.kind == .IMMEDIATE
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case .SPR: return op.kind == .REGISTER && reg_is_spr(op.reg)
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case .IMM, .SIMM, .UIMM:
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return op.kind == .IMMEDIATE
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case .REL: return op.kind == .RELATIVE
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case .MEM: return op.kind == .MEMORY
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case .BO, .BH: return op.kind == .IMMEDIATE
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}
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return false
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}
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// =============================================================================
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// Operand packer
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// =============================================================================
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@(private="file")
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pack_operand_inline :: #force_inline proc(
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op: ^Operand,
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enc: Operand_Encoding,
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pc: u32,
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inst_idx: u16,
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relocs: ^[dynamic]Relocation,
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form: ^Encoding,
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) -> u32 {
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#partial switch enc {
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case .NONE, .IMPL: return 0
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// ---- Integer register slots ----
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case .RT, .RS: return (u32(reg_hw(op.reg)) & 0x1F) << 21
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case .RA: return (u32(reg_hw(op.reg)) & 0x1F) << 16
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case .RB: return (u32(reg_hw(op.reg)) & 0x1F) << 11
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case .RC: return (u32(reg_hw(op.reg)) & 0x1F) << 6
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// ---- Floating-point ----
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case .FRT: return (u32(reg_hw(op.reg)) & 0x1F) << 21
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case .FRA: return (u32(reg_hw(op.reg)) & 0x1F) << 16
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case .FRB: return (u32(reg_hw(op.reg)) & 0x1F) << 11
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case .FRC: return (u32(reg_hw(op.reg)) & 0x1F) << 6
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// ---- AltiVec ----
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case .VRT: return (u32(reg_hw(op.reg)) & 0x1F) << 21
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case .VRA: return (u32(reg_hw(op.reg)) & 0x1F) << 16
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case .VRB: return (u32(reg_hw(op.reg)) & 0x1F) << 11
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case .VRC: return (u32(reg_hw(op.reg)) & 0x1F) << 6
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// ---- VSX (split 5+1 register fields) ----
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case .XT:
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n := u32(reg_hw(op.reg)) & 0x3F
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return ((n & 0x1F) << 21) | ((n >> 5) & 1) // TX at bit 0
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case .XA:
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n := u32(reg_hw(op.reg)) & 0x3F
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return ((n & 0x1F) << 16) | (((n >> 5) & 1) << 2) // AX at bit 2
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case .XB:
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n := u32(reg_hw(op.reg)) & 0x3F
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return ((n & 0x1F) << 11) | (((n >> 5) & 1) << 1) // BX at bit 1
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case .XC:
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n := u32(reg_hw(op.reg)) & 0x3F
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return ((n & 0x1F) << 6) | (((n >> 5) & 1) << 3) // CX at bit 3
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// ---- VMX128 (Xbox 360 Xenon — 7-bit register fields) ----
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// VMX128 encodes the extra 2 bits of each 7-bit register index in
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// scattered positions (bits 5..6 for VDh, 3..4 for VBh, etc.). However
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// those positions ALSO carry per-form XO bits, so a generic encoder
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// can't pack the high register bits without breaking opcode resolution.
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// We use 5-bit packing (vr0..vr31) only — matching the AltiVec subset
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// common in real Xbox 360 code. Users targeting vr32..vr127 must edit
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// the form's bake-everything bits directly.
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case .VRT128: return (u32(reg_hw(op.reg)) & 0x1F) << 21
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case .VRA128: return (u32(reg_hw(op.reg)) & 0x1F) << 16
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case .VRB128: return (u32(reg_hw(op.reg)) & 0x1F) << 11
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case .VRC128: return (u32(reg_hw(op.reg)) & 0x1F) << 6
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// ---- Condition register fields ----
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case .BF: return (u32(reg_hw(op.reg)) & 0x7) << 23
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case .BFA: return (u32(reg_hw(op.reg)) & 0x7) << 18
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case .BT: return (u32(reg_hw(op.reg)) & 0x1F) << 21
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case .BA: return (u32(reg_hw(op.reg)) & 0x1F) << 16
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case .BB: return (u32(reg_hw(op.reg)) & 0x1F) << 11
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case .BO_FIELD:
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if op.kind == .REGISTER { return (u32(reg_hw(op.reg)) & 0x1F) << 21 }
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return (u32(op.immediate) & 0x1F) << 21
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case .BI_FIELD:
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if op.kind == .REGISTER { return (u32(reg_hw(op.reg)) & 0x1F) << 16 }
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return (u32(op.immediate) & 0x1F) << 16
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case .BH_FIELD:
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if op.kind == .REGISTER { return (u32(reg_hw(op.reg)) & 0x3) << 11 }
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return (u32(op.immediate) & 0x3) << 11
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// ---- SPR (10-bit split with halves swapped) ----
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case .SPR_FIELD:
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n := u32(reg_hw(op.reg)) & 0x3FF
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return ((n & 0x1F) << 11) | (((n >> 5) & 0x1F) << 16)
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// ---- Immediates ----
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case .D16: return u32(op.immediate) & 0xFFFF
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case .UI16: return u32(op.immediate) & 0xFFFF
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case .DS14: return u32(op.immediate) & 0xFFFC // signed, low 2 zero
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case .DQ12: return u32(op.immediate) & 0xFFF0 // signed, low 4 zero
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case .SH5: return (u32(op.immediate) & 0x1F) << 11
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case .SH6:
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// 6-bit MD-form shift: low 5 at bits 11..15, bit 5 at bit 1
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v := u32(op.immediate) & 0x3F
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return ((v & 0x1F) << 11) | (((v >> 5) & 1) << 1)
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case .MB5: return (u32(op.immediate) & 0x1F) << 6
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case .ME5: return (u32(op.immediate) & 0x1F) << 1
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case .MB6:
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v := u32(op.immediate) & 0x3F
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return ((v & 0x1F) << 6) | (((v >> 5) & 1) << 5)
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case .SIMM_5, .UIMM_5: return (u32(op.immediate) & 0x1F) << 16
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case .UIMM_4: return (u32(op.immediate) & 0xF) << 16
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case .UIMM_2: return (u32(op.immediate) & 0x3) << 16
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case .FXM: return (u32(op.immediate) & 0xFF) << 12
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case .L_FIELD: return (u32(op.immediate) & 0x1) << 21
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case .TO_FIELD: return (u32(op.immediate) & 0x1F) << 21
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case .NB_FIELD: return (u32(op.immediate) & 0x1F) << 11
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case .SR_FIELD: return (u32(op.immediate) & 0xF) << 16
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case .CRM: return (u32(op.immediate) & 0xFF) << 12
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case .DCMX: return (u32(op.immediate) & 0x7F) << 16
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// ---- Memory addressing composites ----
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case .OFFSET_BASE_D:
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return ((u32(reg_hw(op.mem.base)) & 0x1F) << 16) | (u32(op.mem.disp) & 0xFFFF)
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case .OFFSET_BASE_DS:
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return ((u32(reg_hw(op.mem.base)) & 0x1F) << 16) | (u32(op.mem.disp) & 0xFFFC)
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case .OFFSET_BASE_DQ:
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return ((u32(reg_hw(op.mem.base)) & 0x1F) << 16) | (u32(op.mem.disp) & 0xFFF0)
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case .OFFSET_BASE_X, .OFFSET_VSX_X:
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return ((u32(reg_hw(op.mem.base)) & 0x1F) << 16) | ((u32(reg_hw(op.mem.index)) & 0x1F) << 11)
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// ---- PC-relative branches ----
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case .BRANCH_LI:
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// I-form: 24-bit signed << 2 at bits 2..25. Emit relocation; resolver
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// fills in. Word at this stage has 0 in the displacement.
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if op.kind == .RELATIVE {
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append(relocs, Relocation{
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offset = pc,
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label_id = u32(op.relative),
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type = .BRANCH_I_24,
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size = 4,
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inst_idx = inst_idx,
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})
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}
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return 0
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case .BRANCH_BD:
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// B-form: 14-bit signed << 2 at bits 2..15.
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if op.kind == .RELATIVE {
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append(relocs, Relocation{
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offset = pc,
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label_id = u32(op.relative),
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type = .BRANCH_B_14,
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size = 4,
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inst_idx = inst_idx,
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})
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}
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return 0
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// ---- Flag bits packed via packer (the encode_one_inline() flag pass handles
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// these for user-set values; included here for completeness) ----
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case .AA_FLAG: return 0
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case .LK_FLAG: return 0
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case .RC_FLAG: return 0
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case .OE_FLAG: return 0
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}
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return 0
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}
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// =============================================================================
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// Pass 2 — relocation resolver
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// =============================================================================
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@(private="file")
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resolve_relocation_inline :: #force_inline proc(
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code: []u8,
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label_defs: []Label_Definition,
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r: ^Relocation,
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base_address: u64,
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errors: ^[dynamic]Error,
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) -> bool {
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if int(r.label_id) >= len(label_defs) { return false }
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ld := label_defs[r.label_id]
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if ld == LABEL_UNDEFINED { return false }
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target := u32(ld)
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#partial switch r.type {
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case .BRANCH_I_24:
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// PC = address of this instruction (PPC convention).
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rel := i32(target) - i32(r.offset) + r.addend
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if rel & 3 != 0 || rel < -(1 << 25) || rel >= (1 << 25) {
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append(errors, Error{inst_idx = u32(r.inst_idx), code = .LABEL_OUT_OF_RANGE})
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return true
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}
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// 24-bit LI field at bits 2..25 LSB (= 6..29 MSB).
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li := u32(rel) & 0x03FFFFFC
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word := read_u32_be(code, r.offset)
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word = (word & 0xFC000003) | li
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write_u32_be(code, r.offset, word)
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return true
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case .BRANCH_B_14:
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rel := i32(target) - i32(r.offset) + r.addend
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if rel & 3 != 0 || rel < -(1 << 15) || rel >= (1 << 15) {
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append(errors, Error{inst_idx = u32(r.inst_idx), code = .LABEL_OUT_OF_RANGE})
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return true
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}
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// 14-bit BD field at bits 2..15 LSB (= 16..29 MSB).
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bd := u32(rel) & 0xFFFC
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word := read_u32_be(code, r.offset)
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word = (word & 0xFFFF0003) | bd
|
|
write_u32_be(code, r.offset, word)
|
|
return true
|
|
|
|
case .PREFIXED_34:
|
|
// Power ISA 3.1: 34-bit signed at IMM18(prefix)||D(suffix).
|
|
// Prefix occupies bytes r.offset .. r.offset+3 (BE), suffix bytes
|
|
// r.offset+4 .. r.offset+7.
|
|
rel := i64(target) - i64(r.offset) + i64(r.addend)
|
|
if rel < -(i64(1) << 33) || rel >= (i64(1) << 33) {
|
|
append(errors, Error{inst_idx = u32(r.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
v := u64(rel) & ((u64(1) << 34) - 1)
|
|
pfx := read_u32_be(code, r.offset)
|
|
sfx := read_u32_be(code, r.offset + 4)
|
|
// IMM18 = high 18 bits, D = low 16
|
|
imm18 := u32(v >> 16) & 0x3FFFF
|
|
d16 := u32(v) & 0xFFFF
|
|
pfx = (pfx & 0xFFFC0000) | imm18
|
|
sfx = (sfx & 0xFFFF0000) | d16
|
|
write_u32_be(code, r.offset, pfx)
|
|
write_u32_be(code, r.offset + 4, sfx)
|
|
return true
|
|
|
|
case:
|
|
return false
|
|
}
|
|
}
|
|
|
|
// =============================================================================
|
|
// Big-endian word I/O
|
|
// =============================================================================
|
|
|
|
@(private="package")
|
|
write_u32_be :: #force_inline proc "contextless" (code: []u8, offset, word: u32) {
|
|
code[offset+0] = u8(word >> 24)
|
|
code[offset+1] = u8(word >> 16)
|
|
code[offset+2] = u8(word >> 8)
|
|
code[offset+3] = u8(word)
|
|
}
|
|
|
|
@(private="package")
|
|
read_u32_be :: #force_inline proc "contextless" (code: []u8, offset: u32) -> u32 {
|
|
return (u32(code[offset+0]) << 24) |
|
|
(u32(code[offset+1]) << 16) |
|
|
(u32(code[offset+2]) << 8) |
|
|
u32(code[offset+3])
|
|
}
|