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1b72d425d4
Add generated mnemonic_builders.odin (inst_<mnem>/emit_<mnem> typed overload sets) for arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502 and mos65816, matching the existing x86 builders. Each is produced by a per-arch tools/gen_mnemonic_builders.odin that walks ENCODE_FORMS and maps operand types to typed params + op_* constructors. Anchor every generator's output via #directory so regeneration is CWD-independent; previously the bare "mnemonic_builders.odin" path wrote to the current directory and misfired when run from the repo root. Wire a --builders task into build.lua (folded into 'all', covered by --idempotent, enforced by the structural invariants) and document it in the README.
13336 lines
1.9 MiB
13336 lines
1.9 MiB
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_ppc
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// =============================================================================
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// GENERATED FILE - DO NOT EDIT
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// =============================================================================
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//
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// Generated by tools/gen_mnemonic_builders.odin from ENCODE_FORMS.
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// Regenerate with: odin run ppc/tools/gen_mnemonic_builders.odin -file
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//
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// Typed mnemonic builder procedures with overloading. Each mnemonic exposes
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// inst_<mnemonic> (returns an Instruction) and emit_<mnemonic> (appends to a
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// [dynamic]Instruction) overload sets, one variant per encode form.
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//
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// NOTE: PowerPC has no typed register enums; register operands of every class
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// (GPR/FPR/VR/VSR/VR128/CR field and bit/SPR) take the generic Register type.
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// =============================================================================
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// Individual Typed Builder Procedures
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// =============================================================================
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inst_b_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .B, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_b_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_rel(label)) }
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inst_bl_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bl_rel(label)) }
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inst_ba_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BA, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_ba_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_ba_rel(label)) }
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inst_bla_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BLA, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bla_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bla_rel(label)) }
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inst_bc_bo_crb_rel :: #force_inline proc "contextless" (bo: i64, dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BC, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_label(label), {}}} }
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emit_bc_bo_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, label: u32) { append(instructions, inst_bc_bo_crb_rel(bo, dst, label)) }
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inst_bcl_bo_crb_rel :: #force_inline proc "contextless" (bo: i64, dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BCL, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_label(label), {}}} }
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emit_bcl_bo_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, label: u32) { append(instructions, inst_bcl_bo_crb_rel(bo, dst, label)) }
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inst_bca_bo_crb_rel :: #force_inline proc "contextless" (bo: i64, dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BCA, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_label(label), {}}} }
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emit_bca_bo_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, label: u32) { append(instructions, inst_bca_bo_crb_rel(bo, dst, label)) }
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inst_bcla_bo_crb_rel :: #force_inline proc "contextless" (bo: i64, dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BCLA, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_label(label), {}}} }
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emit_bcla_bo_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, label: u32) { append(instructions, inst_bcla_bo_crb_rel(bo, dst, label)) }
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inst_bclr_bo_crb_bh :: #force_inline proc "contextless" (bo: i64, dst: Register, bh: i64) -> Instruction { return Instruction{mnemonic = .BCLR, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_imm(bh), {}}} }
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emit_bclr_bo_crb_bh :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, bh: i64) { append(instructions, inst_bclr_bo_crb_bh(bo, dst, bh)) }
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inst_bclrl_bo_crb_bh :: #force_inline proc "contextless" (bo: i64, dst: Register, bh: i64) -> Instruction { return Instruction{mnemonic = .BCLRL, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_imm(bh), {}}} }
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emit_bclrl_bo_crb_bh :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, bh: i64) { append(instructions, inst_bclrl_bo_crb_bh(bo, dst, bh)) }
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inst_bcctr_bo_crb_bh :: #force_inline proc "contextless" (bo: i64, dst: Register, bh: i64) -> Instruction { return Instruction{mnemonic = .BCCTR, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_imm(bh), {}}} }
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emit_bcctr_bo_crb_bh :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, bh: i64) { append(instructions, inst_bcctr_bo_crb_bh(bo, dst, bh)) }
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inst_bcctrl_bo_crb_bh :: #force_inline proc "contextless" (bo: i64, dst: Register, bh: i64) -> Instruction { return Instruction{mnemonic = .BCCTRL, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_imm(bh), {}}} }
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emit_bcctrl_bo_crb_bh :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, bh: i64) { append(instructions, inst_bcctrl_bo_crb_bh(bo, dst, bh)) }
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inst_bctar_bo_crb_bh :: #force_inline proc "contextless" (bo: i64, dst: Register, bh: i64) -> Instruction { return Instruction{mnemonic = .BCTAR, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_imm(bh), {}}} }
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emit_bctar_bo_crb_bh :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, bh: i64) { append(instructions, inst_bctar_bo_crb_bh(bo, dst, bh)) }
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inst_bctarl_bo_crb_bh :: #force_inline proc "contextless" (bo: i64, dst: Register, bh: i64) -> Instruction { return Instruction{mnemonic = .BCTARL, operand_count = 3, length = 4, ops = {op_imm(bo), op_reg(dst), op_imm(bh), {}}} }
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emit_bctarl_bo_crb_bh :: #force_inline proc(instructions: ^[dynamic]Instruction, bo: i64, dst: Register, bh: i64) { append(instructions, inst_bctarl_bo_crb_bh(bo, dst, bh)) }
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inst_sc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SC, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_sc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_sc_imm(imm)) }
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inst_crand_crb_crb_crb :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRAND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crand_crb_crb_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crand_crb_crb_crb(dst, src, src2)) }
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inst_crnand_crb_crb_crb :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRNAND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crnand_crb_crb_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crnand_crb_crb_crb(dst, src, src2)) }
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inst_cror_crb_crb_crb :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CROR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cror_crb_crb_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cror_crb_crb_crb(dst, src, src2)) }
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inst_crnor_crb_crb_crb :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRNOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crnor_crb_crb_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crnor_crb_crb_crb(dst, src, src2)) }
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inst_crxor_crb_crb_crb :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRXOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crxor_crb_crb_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crxor_crb_crb_crb(dst, src, src2)) }
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inst_creqv_crb_crb_crb :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CREQV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_creqv_crb_crb_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_creqv_crb_crb_crb(dst, src, src2)) }
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inst_crandc_crb_crb_crb :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRANDC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crandc_crb_crb_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crandc_crb_crb_crb(dst, src, src2)) }
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inst_crorc_crb_crb_crb :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRORC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_crorc_crb_crb_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crorc_crb_crb_crb(dst, src, src2)) }
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inst_mcrf_crf_crf :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MCRF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mcrf_crf_crf :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mcrf_crf_crf(dst, src)) }
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inst_lbz_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lbz_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lbz_r_mem(dst, addr)) }
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inst_lbzu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LBZU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lbzu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lbzu_r_mem(dst, addr)) }
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inst_lbzx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LBZX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lbzx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lbzx_r_mem(dst, addr)) }
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inst_lbzux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LBZUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lbzux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lbzux_r_mem(dst, addr)) }
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inst_lhz_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lhz_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lhz_r_mem(dst, addr)) }
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inst_lhzu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHZU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lhzu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lhzu_r_mem(dst, addr)) }
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inst_lhzx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHZX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lhzx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lhzx_r_mem(dst, addr)) }
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inst_lhzux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHZUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lhzux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lhzux_r_mem(dst, addr)) }
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inst_lha_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHA, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lha_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lha_r_mem(dst, addr)) }
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inst_lhau_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHAU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lhau_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lhau_r_mem(dst, addr)) }
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inst_lhax_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHAX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lhax_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lhax_r_mem(dst, addr)) }
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inst_lhaux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHAUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lhaux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lhaux_r_mem(dst, addr)) }
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inst_lwz_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LWZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lwz_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lwz_r_mem(dst, addr)) }
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inst_lwzu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LWZU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lwzu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lwzu_r_mem(dst, addr)) }
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inst_lwzx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LWZX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lwzx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lwzx_r_mem(dst, addr)) }
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inst_lwzux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LWZUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lwzux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lwzux_r_mem(dst, addr)) }
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inst_lwa_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LWA, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lwa_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lwa_r_mem(dst, addr)) }
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inst_lwax_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LWAX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lwax_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lwax_r_mem(dst, addr)) }
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inst_lwaux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LWAUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lwaux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lwaux_r_mem(dst, addr)) }
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inst_ld_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_ld_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_ld_r_mem(dst, addr)) }
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inst_ldu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LDU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_ldu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_ldu_r_mem(dst, addr)) }
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inst_ldx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LDX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_ldx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_ldx_r_mem(dst, addr)) }
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inst_ldux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LDUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_ldux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_ldux_r_mem(dst, addr)) }
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inst_lq_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lq_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lq_r_mem(dst, addr)) }
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inst_lhbrx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHBRX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lhbrx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lhbrx_r_mem(dst, addr)) }
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inst_lwbrx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LWBRX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lwbrx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lwbrx_r_mem(dst, addr)) }
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inst_ldbrx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LDBRX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_ldbrx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_ldbrx_r_mem(dst, addr)) }
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inst_lmw_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LMW, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lmw_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lmw_r_mem(dst, addr)) }
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inst_lswi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_lswi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lswi_r_r_imm(dst, src, imm)) }
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inst_lswx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LSWX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lswx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lswx_r_mem(dst, addr)) }
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inst_stb_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STB, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stb_r_mem(dst, addr)) }
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inst_stbu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STBU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stbu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stbu_r_mem(dst, addr)) }
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inst_stbx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STBX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stbx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stbx_r_mem(dst, addr)) }
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inst_stbux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STBUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stbux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stbux_r_mem(dst, addr)) }
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inst_sth_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STH, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_sth_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_sth_r_mem(dst, addr)) }
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inst_sthu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STHU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_sthu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_sthu_r_mem(dst, addr)) }
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inst_sthx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STHX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_sthx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_sthx_r_mem(dst, addr)) }
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inst_sthux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STHUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_sthux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_sthux_r_mem(dst, addr)) }
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inst_stw_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STW, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stw_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stw_r_mem(dst, addr)) }
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inst_stwu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STWU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stwu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stwu_r_mem(dst, addr)) }
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inst_stwx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STWX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stwx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stwx_r_mem(dst, addr)) }
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inst_stwux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STWUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stwux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stwux_r_mem(dst, addr)) }
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inst_std_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_std_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_std_r_mem(dst, addr)) }
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inst_stdu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STDU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stdu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stdu_r_mem(dst, addr)) }
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inst_stdx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STDX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stdx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stdx_r_mem(dst, addr)) }
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inst_stdux_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STDUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stdux_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stdux_r_mem(dst, addr)) }
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inst_stq_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stq_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stq_r_mem(dst, addr)) }
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inst_sthbrx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STHBRX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_sthbrx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_sthbrx_r_mem(dst, addr)) }
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inst_stwbrx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STWBRX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stwbrx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stwbrx_r_mem(dst, addr)) }
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inst_stdbrx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STDBRX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stdbrx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stdbrx_r_mem(dst, addr)) }
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inst_stmw_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STMW, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stmw_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stmw_r_mem(dst, addr)) }
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inst_stswi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .STSWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_stswi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_stswi_r_r_imm(dst, src, imm)) }
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inst_stswx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STSWX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stswx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stswx_r_mem(dst, addr)) }
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inst_lbarx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LBARX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lbarx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lbarx_r_mem(dst, addr)) }
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inst_lharx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LHARX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lharx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lharx_r_mem(dst, addr)) }
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inst_lwarx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LWARX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lwarx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lwarx_r_mem(dst, addr)) }
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inst_ldarx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LDARX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_ldarx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_ldarx_r_mem(dst, addr)) }
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inst_lqarx_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LQARX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lqarx_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lqarx_r_mem(dst, addr)) }
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inst_stbcx_dot_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STBCX_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stbcx_dot_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stbcx_dot_r_mem(dst, addr)) }
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inst_sthcx_dot_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STHCX_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_sthcx_dot_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_sthcx_dot_r_mem(dst, addr)) }
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inst_stwcx_dot_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STWCX_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stwcx_dot_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stwcx_dot_r_mem(dst, addr)) }
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inst_stdcx_dot_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STDCX_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stdcx_dot_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stdcx_dot_r_mem(dst, addr)) }
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inst_stqcx_dot_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STQCX_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stqcx_dot_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stqcx_dot_r_mem(dst, addr)) }
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inst_addi_r_rz_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_addi_r_rz_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_addi_r_rz_simm(dst, src, imm)) }
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inst_addis_r_rz_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADDIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_addis_r_rz_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_addis_r_rz_simm(dst, src, imm)) }
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inst_addic_r_r_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADDIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_addic_r_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_addic_r_r_simm(dst, src, imm)) }
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inst_addic_dot_r_r_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADDIC_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_addic_dot_r_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_addic_dot_r_r_simm(dst, src, imm)) }
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inst_subfic_r_r_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUBFIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_subfic_r_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subfic_r_r_simm(dst, src, imm)) }
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inst_addpcis_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADDPCIS, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_addpcis_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_addpcis_r_simm(dst, imm)) }
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inst_add_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_add_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_r_r_r(dst, src, src2)) }
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inst_add_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_add_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_dot_r_r_r(dst, src, src2)) }
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inst_add_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_add_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_o_r_r_r(dst, src, src2)) }
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inst_add_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_add_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_o_dot_r_r_r(dst, src, src2)) }
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inst_addc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addc_r_r_r(dst, src, src2)) }
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inst_addc_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDC_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addc_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addc_dot_r_r_r(dst, src, src2)) }
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inst_addc_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDC_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addc_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addc_o_r_r_r(dst, src, src2)) }
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inst_addc_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDC_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addc_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addc_o_dot_r_r_r(dst, src, src2)) }
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inst_adde_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_adde_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adde_r_r_r(dst, src, src2)) }
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inst_adde_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_adde_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adde_dot_r_r_r(dst, src, src2)) }
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inst_adde_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDE_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_adde_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adde_o_r_r_r(dst, src, src2)) }
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inst_adde_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDE_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_adde_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adde_o_dot_r_r_r(dst, src, src2)) }
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inst_addme_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDME, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_addme_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addme_r_r(dst, src)) }
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inst_addme_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDME_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_addme_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addme_dot_r_r(dst, src)) }
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inst_addme_o_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDME_O, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_addme_o_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addme_o_r_r(dst, src)) }
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inst_addme_o_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDME_O_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_addme_o_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addme_o_dot_r_r(dst, src)) }
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inst_addze_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDZE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_addze_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addze_r_r(dst, src)) }
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inst_addze_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDZE_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_addze_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addze_dot_r_r(dst, src)) }
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inst_addze_o_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDZE_O, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_addze_o_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addze_o_r_r(dst, src)) }
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inst_addze_o_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDZE_O_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_addze_o_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addze_o_dot_r_r(dst, src)) }
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inst_addex_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDEX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addex_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addex_r_r_r(dst, src, src2)) }
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inst_subf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subf_r_r_r(dst, src, src2)) }
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inst_subf_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBF_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subf_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subf_dot_r_r_r(dst, src, src2)) }
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inst_subf_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBF_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subf_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subf_o_r_r_r(dst, src, src2)) }
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inst_subf_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBF_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subf_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subf_o_dot_r_r_r(dst, src, src2)) }
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inst_subfc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfc_r_r_r(dst, src, src2)) }
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inst_subfc_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFC_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfc_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfc_dot_r_r_r(dst, src, src2)) }
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inst_subfc_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFC_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfc_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfc_o_r_r_r(dst, src, src2)) }
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inst_subfc_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFC_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfc_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfc_o_dot_r_r_r(dst, src, src2)) }
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inst_subfe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfe_r_r_r(dst, src, src2)) }
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inst_subfe_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfe_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfe_dot_r_r_r(dst, src, src2)) }
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inst_subfe_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFE_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfe_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfe_o_r_r_r(dst, src, src2)) }
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inst_subfe_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFE_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfe_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfe_o_dot_r_r_r(dst, src, src2)) }
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inst_subfme_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SUBFME, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_subfme_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_subfme_r_r(dst, src)) }
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inst_subfme_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SUBFME_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_subfme_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_subfme_dot_r_r(dst, src)) }
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inst_subfme_o_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SUBFME_O, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_subfme_o_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_subfme_o_r_r(dst, src)) }
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inst_subfme_o_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SUBFME_O_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_subfme_o_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_subfme_o_dot_r_r(dst, src)) }
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inst_subfze_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SUBFZE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_subfze_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_subfze_r_r(dst, src)) }
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inst_subfze_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SUBFZE_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_subfze_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_subfze_dot_r_r(dst, src)) }
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inst_subfze_o_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SUBFZE_O, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_subfze_o_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_subfze_o_r_r(dst, src)) }
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inst_subfze_o_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SUBFZE_O_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_subfze_o_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_subfze_o_dot_r_r(dst, src)) }
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inst_neg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_neg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_r_r(dst, src)) }
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inst_neg_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_neg_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_dot_r_r(dst, src)) }
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inst_neg_o_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG_O, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_neg_o_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_o_r_r(dst, src)) }
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inst_neg_o_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG_O_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_neg_o_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_o_dot_r_r(dst, src)) }
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inst_mulli_r_rz_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MULLI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_mulli_r_rz_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_mulli_r_rz_simm(dst, src, imm)) }
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inst_mulhw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhw_r_r_r(dst, src, src2)) }
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inst_mulhw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhw_dot_r_r_r(dst, src, src2)) }
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inst_mulhwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhwu_r_r_r(dst, src, src2)) }
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inst_mulhwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhwu_dot_r_r_r(dst, src, src2)) }
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inst_mullw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullw_r_r_r(dst, src, src2)) }
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inst_mullw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullw_dot_r_r_r(dst, src, src2)) }
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inst_mullw_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLW_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullw_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullw_o_r_r_r(dst, src, src2)) }
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inst_mullw_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLW_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullw_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullw_o_dot_r_r_r(dst, src, src2)) }
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inst_mulld_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulld_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulld_r_r_r(dst, src, src2)) }
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inst_mulld_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulld_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulld_dot_r_r_r(dst, src, src2)) }
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inst_mulld_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLD_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulld_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulld_o_r_r_r(dst, src, src2)) }
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inst_mulld_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLD_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulld_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulld_o_dot_r_r_r(dst, src, src2)) }
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inst_mulhd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhd_r_r_r(dst, src, src2)) }
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inst_mulhd_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhd_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhd_dot_r_r_r(dst, src, src2)) }
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inst_mulhdu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHDU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhdu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhdu_r_r_r(dst, src, src2)) }
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inst_mulhdu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHDU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhdu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhdu_dot_r_r_r(dst, src, src2)) }
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inst_maddld_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MADDLD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_maddld_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_maddld_r_r_r_r(dst, src, src2, src3)) }
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inst_maddhd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MADDHD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_maddhd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_maddhd_r_r_r_r(dst, src, src2, src3)) }
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inst_maddhdu_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MADDHDU, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_maddhdu_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_maddhdu_r_r_r_r(dst, src, src2, src3)) }
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inst_divw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divw_r_r_r(dst, src, src2)) }
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inst_divw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divw_dot_r_r_r(dst, src, src2)) }
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inst_divw_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVW_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divw_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divw_o_r_r_r(dst, src, src2)) }
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inst_divw_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVW_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divw_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divw_o_dot_r_r_r(dst, src, src2)) }
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inst_divwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwu_r_r_r(dst, src, src2)) }
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inst_divwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwu_dot_r_r_r(dst, src, src2)) }
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inst_divwu_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWU_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwu_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwu_o_r_r_r(dst, src, src2)) }
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inst_divwu_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWU_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwu_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwu_o_dot_r_r_r(dst, src, src2)) }
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inst_divd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divd_r_r_r(dst, src, src2)) }
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inst_divd_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divd_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divd_dot_r_r_r(dst, src, src2)) }
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inst_divd_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVD_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divd_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divd_o_r_r_r(dst, src, src2)) }
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inst_divd_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVD_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divd_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divd_o_dot_r_r_r(dst, src, src2)) }
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inst_divdu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdu_r_r_r(dst, src, src2)) }
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inst_divdu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdu_dot_r_r_r(dst, src, src2)) }
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inst_divdu_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDU_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdu_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdu_o_r_r_r(dst, src, src2)) }
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inst_divdu_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDU_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdu_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdu_o_dot_r_r_r(dst, src, src2)) }
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inst_divwe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwe_r_r_r(dst, src, src2)) }
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inst_divwe_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwe_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwe_dot_r_r_r(dst, src, src2)) }
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inst_divwe_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWE_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwe_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwe_o_r_r_r(dst, src, src2)) }
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inst_divwe_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWE_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwe_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwe_o_dot_r_r_r(dst, src, src2)) }
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inst_divweu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWEU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divweu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divweu_r_r_r(dst, src, src2)) }
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inst_divweu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWEU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divweu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divweu_dot_r_r_r(dst, src, src2)) }
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inst_divweu_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWEU_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divweu_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divweu_o_r_r_r(dst, src, src2)) }
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inst_divweu_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWEU_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divweu_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divweu_o_dot_r_r_r(dst, src, src2)) }
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inst_divde_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divde_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divde_r_r_r(dst, src, src2)) }
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inst_divde_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divde_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divde_dot_r_r_r(dst, src, src2)) }
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inst_divde_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDE_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divde_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divde_o_r_r_r(dst, src, src2)) }
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inst_divde_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDE_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divde_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divde_o_dot_r_r_r(dst, src, src2)) }
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inst_divdeu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDEU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdeu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdeu_r_r_r(dst, src, src2)) }
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inst_divdeu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDEU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdeu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdeu_dot_r_r_r(dst, src, src2)) }
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inst_divdeu_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDEU_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdeu_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdeu_o_r_r_r(dst, src, src2)) }
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inst_divdeu_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDEU_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdeu_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdeu_o_dot_r_r_r(dst, src, src2)) }
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inst_modsw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MODSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_modsw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_modsw_r_r_r(dst, src, src2)) }
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inst_moduw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MODUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_moduw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_moduw_r_r_r(dst, src, src2)) }
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inst_modsd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MODSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_modsd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_modsd_r_r_r(dst, src, src2)) }
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inst_modud_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MODUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_modud_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_modud_r_r_r(dst, src, src2)) }
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inst_twi_imm_r_simm :: #force_inline proc "contextless" (imm: i64, dst: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .TWI, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_imm(imm2), {}}} }
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emit_twi_imm_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, imm2: i64) { append(instructions, inst_twi_imm_r_simm(imm, dst, imm2)) }
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inst_tw_imm_r_r :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TW, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_tw_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_tw_imm_r_r(imm, dst, src)) }
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inst_tdi_imm_r_simm :: #force_inline proc "contextless" (imm: i64, dst: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .TDI, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_imm(imm2), {}}} }
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emit_tdi_imm_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, imm2: i64) { append(instructions, inst_tdi_imm_r_simm(imm, dst, imm2)) }
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inst_td_imm_r_r :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TD, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_td_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_td_imm_r_r(imm, dst, src)) }
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inst_andi_dot_r_r_uimm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ANDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_andi_dot_r_r_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_andi_dot_r_r_uimm(dst, src, imm)) }
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inst_andis_dot_r_r_uimm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ANDIS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_andis_dot_r_r_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_andis_dot_r_r_uimm(dst, src, imm)) }
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inst_ori_r_r_uimm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ORI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_ori_r_r_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ori_r_r_uimm(dst, src, imm)) }
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inst_oris_r_r_uimm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ORIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_oris_r_r_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_oris_r_r_uimm(dst, src, imm)) }
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inst_xori_r_r_uimm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XORI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xori_r_r_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xori_r_r_uimm(dst, src, imm)) }
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inst_xoris_r_r_uimm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XORIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xoris_r_r_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xoris_r_r_uimm(dst, src, imm)) }
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inst_and_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_and_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_r_r_r(dst, src, src2)) }
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inst_and_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_and_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_dot_r_r_r(dst, src, src2)) }
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inst_or_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .OR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_or_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_or_r_r_r(dst, src, src2)) }
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inst_or_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .OR_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_or_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_or_dot_r_r_r(dst, src, src2)) }
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inst_xor_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xor_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xor_r_r_r(dst, src, src2)) }
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inst_xor_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XOR_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xor_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xor_dot_r_r_r(dst, src, src2)) }
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inst_nand_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nand_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nand_r_r_r(dst, src, src2)) }
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inst_nand_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NAND_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nand_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nand_dot_r_r_r(dst, src, src2)) }
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inst_nor_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nor_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nor_r_r_r(dst, src, src2)) }
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inst_nor_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NOR_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nor_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nor_dot_r_r_r(dst, src, src2)) }
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inst_eqv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EQV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_eqv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eqv_r_r_r(dst, src, src2)) }
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inst_eqv_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EQV_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_eqv_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eqv_dot_r_r_r(dst, src, src2)) }
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inst_andc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ANDC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_andc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_andc_r_r_r(dst, src, src2)) }
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inst_andc_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ANDC_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_andc_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_andc_dot_r_r_r(dst, src, src2)) }
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inst_orc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_orc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orc_r_r_r(dst, src, src2)) }
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inst_orc_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORC_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_orc_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orc_dot_r_r_r(dst, src, src2)) }
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inst_extsb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EXTSB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_extsb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_extsb_r_r(dst, src)) }
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inst_extsb_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EXTSB_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_extsb_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_extsb_dot_r_r(dst, src)) }
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inst_extsh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EXTSH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_extsh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_extsh_r_r(dst, src)) }
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inst_extsh_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EXTSH_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_extsh_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_extsh_dot_r_r(dst, src)) }
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inst_extsw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EXTSW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_extsw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_extsw_r_r(dst, src)) }
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inst_extsw_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EXTSW_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_extsw_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_extsw_dot_r_r(dst, src)) }
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inst_cntlzw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNTLZW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cntlzw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cntlzw_r_r(dst, src)) }
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inst_cntlzw_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNTLZW_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cntlzw_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cntlzw_dot_r_r(dst, src)) }
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inst_cntlzd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNTLZD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cntlzd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cntlzd_r_r(dst, src)) }
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inst_cntlzd_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNTLZD_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cntlzd_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cntlzd_dot_r_r(dst, src)) }
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inst_cnttzw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNTTZW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cnttzw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnttzw_r_r(dst, src)) }
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inst_cnttzw_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNTTZW_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cnttzw_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnttzw_dot_r_r(dst, src)) }
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inst_cnttzd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNTTZD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cnttzd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnttzd_r_r(dst, src)) }
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inst_cnttzd_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNTTZD_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cnttzd_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnttzd_dot_r_r(dst, src)) }
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inst_popcntb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .POPCNTB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_popcntb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_popcntb_r_r(dst, src)) }
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inst_popcntw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .POPCNTW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_popcntw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_popcntw_r_r(dst, src)) }
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inst_popcntd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .POPCNTD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_popcntd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_popcntd_r_r(dst, src)) }
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inst_prtyw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PRTYW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_prtyw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_prtyw_r_r(dst, src)) }
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inst_prtyd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PRTYD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_prtyd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_prtyd_r_r(dst, src)) }
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inst_bpermd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BPERMD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_bpermd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bpermd_r_r_r(dst, src, src2)) }
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inst_cmpb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMPB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cmpb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmpb_r_r_r(dst, src, src2)) }
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inst_slw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_slw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_slw_r_r_r(dst, src, src2)) }
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inst_slw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_slw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_slw_dot_r_r_r(dst, src, src2)) }
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inst_srw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srw_r_r_r(dst, src, src2)) }
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inst_srw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srw_dot_r_r_r(dst, src, src2)) }
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inst_sraw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sraw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sraw_r_r_r(dst, src, src2)) }
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inst_sraw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sraw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sraw_dot_r_r_r(dst, src, src2)) }
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inst_srawi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRAWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_srawi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srawi_r_r_imm(dst, src, imm)) }
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inst_srawi_dot_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRAWI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_srawi_dot_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srawi_dot_r_r_imm(dst, src, imm)) }
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inst_sld_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sld_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sld_r_r_r(dst, src, src2)) }
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inst_sld_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sld_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sld_dot_r_r_r(dst, src, src2)) }
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inst_srd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srd_r_r_r(dst, src, src2)) }
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inst_srd_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srd_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srd_dot_r_r_r(dst, src, src2)) }
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inst_srad_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srad_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srad_r_r_r(dst, src, src2)) }
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inst_srad_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srad_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srad_dot_r_r_r(dst, src, src2)) }
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inst_sradi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRADI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_sradi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sradi_r_r_imm(dst, src, imm)) }
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inst_sradi_dot_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRADI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_sradi_dot_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sradi_dot_r_r_imm(dst, src, imm)) }
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inst_rlwinm_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLWINM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rlwinm_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rlwinm_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rlwinm_dot_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLWINM_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rlwinm_dot_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rlwinm_dot_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rlwnm_r_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RLWNM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_rlwnm_r_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_rlwnm_r_r_r_imm(dst, src, src2, imm)) }
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inst_rlwnm_dot_r_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RLWNM_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_rlwnm_dot_r_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_rlwnm_dot_r_r_r_imm(dst, src, src2, imm)) }
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inst_rlwimi_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLWIMI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rlwimi_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rlwimi_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rlwimi_dot_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLWIMI_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rlwimi_dot_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rlwimi_dot_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rldicl_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLDICL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rldicl_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rldicl_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rldicl_dot_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLDICL_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rldicl_dot_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rldicl_dot_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rldicr_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLDICR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rldicr_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rldicr_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rldicr_dot_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLDICR_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rldicr_dot_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rldicr_dot_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rldic_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLDIC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rldic_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rldic_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rldic_dot_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLDIC_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rldic_dot_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rldic_dot_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rldimi_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLDIMI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rldimi_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rldimi_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rldimi_dot_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .RLDIMI_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_rldimi_dot_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_rldimi_dot_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rldcl_r_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RLDCL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_rldcl_r_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_rldcl_r_r_r_imm(dst, src, src2, imm)) }
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inst_rldcl_dot_r_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RLDCL_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_rldcl_dot_r_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_rldcl_dot_r_r_r_imm(dst, src, src2, imm)) }
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inst_rldcr_r_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RLDCR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_rldcr_r_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_rldcr_r_r_r_imm(dst, src, src2, imm)) }
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inst_rldcr_dot_r_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RLDCR_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_rldcr_dot_r_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_rldcr_dot_r_r_r_imm(dst, src, src2, imm)) }
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inst_cmpi_crf_imm_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CMPI, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_imm(imm2)}} }
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emit_cmpi_crf_imm_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cmpi_crf_imm_r_simm(dst, imm, src, imm2)) }
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inst_cmpli_crf_imm_r_uimm :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CMPLI, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_imm(imm2)}} }
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emit_cmpli_crf_imm_r_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cmpli_crf_imm_r_uimm(dst, imm, src, imm2)) }
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inst_cmp_crf_imm_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_cmp_crf_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cmp_crf_imm_r_r(dst, imm, src, src2)) }
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inst_cmpl_crf_imm_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMPL, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_cmpl_crf_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cmpl_crf_imm_r_r(dst, imm, src, src2)) }
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inst_cmprb_crf_imm_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMPRB, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} }
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emit_cmprb_crf_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cmprb_crf_imm_r_r(dst, imm, src, src2)) }
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inst_cmpeqb_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMPEQB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cmpeqb_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmpeqb_crf_r_r(dst, src, src2)) }
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inst_fadd_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fadd_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_fr_fr_fr(dst, src, src2)) }
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inst_fadd_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fadd_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_dot_fr_fr_fr(dst, src, src2)) }
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inst_fadds_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fadds_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadds_fr_fr_fr(dst, src, src2)) }
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inst_fadds_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fadds_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadds_dot_fr_fr_fr(dst, src, src2)) }
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inst_fsub_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fsub_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_fr_fr_fr(dst, src, src2)) }
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inst_fsub_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fsub_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_dot_fr_fr_fr(dst, src, src2)) }
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inst_fsubs_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fsubs_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsubs_fr_fr_fr(dst, src, src2)) }
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inst_fsubs_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUBS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fsubs_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsubs_dot_fr_fr_fr(dst, src, src2)) }
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inst_fmul_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fmul_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_fr_fr_fr(dst, src, src2)) }
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inst_fmul_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fmul_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_dot_fr_fr_fr(dst, src, src2)) }
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inst_fmuls_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fmuls_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmuls_fr_fr_fr(dst, src, src2)) }
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inst_fmuls_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fmuls_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmuls_dot_fr_fr_fr(dst, src, src2)) }
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inst_fdiv_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fdiv_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_fr_fr_fr(dst, src, src2)) }
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inst_fdiv_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fdiv_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_dot_fr_fr_fr(dst, src, src2)) }
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inst_fdivs_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIVS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fdivs_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdivs_fr_fr_fr(dst, src, src2)) }
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inst_fdivs_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIVS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fdivs_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdivs_dot_fr_fr_fr(dst, src, src2)) }
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inst_fsqrt_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fsqrt_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_fr_fr(dst, src)) }
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inst_fsqrt_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fsqrt_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_dot_fr_fr(dst, src)) }
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inst_fsqrts_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRTS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fsqrts_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrts_fr_fr(dst, src)) }
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inst_fsqrts_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRTS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fsqrts_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrts_dot_fr_fr(dst, src)) }
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inst_fre_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fre_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fre_fr_fr(dst, src)) }
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inst_fre_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRE_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fre_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fre_dot_fr_fr(dst, src)) }
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inst_fres_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRES, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fres_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fres_fr_fr(dst, src)) }
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inst_fres_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRES_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fres_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fres_dot_fr_fr(dst, src)) }
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inst_frsqrte_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frsqrte_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_fr_fr(dst, src)) }
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inst_frsqrte_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frsqrte_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_dot_fr_fr(dst, src)) }
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inst_frsqrtes_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTES, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frsqrtes_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrtes_fr_fr(dst, src)) }
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inst_frsqrtes_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTES_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frsqrtes_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrtes_dot_fr_fr(dst, src)) }
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inst_fmadd_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FMADD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fmadd_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fmadd_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FMADD_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fmadd_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fmadds_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FMADDS, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fmadds_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadds_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fmadds_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FMADDS_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fmadds_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadds_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fmsub_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FMSUB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fmsub_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fmsub_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FMSUB_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fmsub_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fmsubs_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FMSUBS, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fmsubs_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsubs_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fmsubs_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FMSUBS_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fmsubs_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsubs_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fnmadd_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FNMADD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fnmadd_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fnmadd_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FNMADD_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fnmadd_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fnmadds_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FNMADDS, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fnmadds_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadds_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fnmadds_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FNMADDS_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fnmadds_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadds_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fnmsub_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FNMSUB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fnmsub_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fnmsub_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FNMSUB_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fnmsub_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fnmsubs_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FNMSUBS, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fnmsubs_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsubs_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fnmsubs_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FNMSUBS_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fnmsubs_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsubs_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fsel_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fsel_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fsel_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fsel_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .FSEL_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_fsel_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fsel_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_fcpsgn_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCPSGN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fcpsgn_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcpsgn_fr_fr_fr(dst, src, src2)) }
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inst_fcpsgn_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCPSGN_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fcpsgn_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcpsgn_dot_fr_fr_fr(dst, src, src2)) }
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inst_fneg_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fneg_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_fr_fr(dst, src)) }
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inst_fneg_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fneg_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_dot_fr_fr(dst, src)) }
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inst_fabs_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fabs_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_fr_fr(dst, src)) }
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inst_fabs_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fabs_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_dot_fr_fr(dst, src)) }
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inst_fnabs_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fnabs_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fnabs_fr_fr(dst, src)) }
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inst_fnabs_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNABS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fnabs_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fnabs_dot_fr_fr(dst, src)) }
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inst_fmr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fmr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmr_fr_fr(dst, src)) }
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inst_fmr_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMR_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fmr_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmr_dot_fr_fr(dst, src)) }
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inst_frsp_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frsp_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsp_fr_fr(dst, src)) }
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inst_frsp_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSP_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frsp_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsp_dot_fr_fr(dst, src)) }
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inst_fctid_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTID, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctid_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctid_fr_fr(dst, src)) }
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inst_fctid_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTID_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctid_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctid_dot_fr_fr(dst, src)) }
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inst_fctidu_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIDU, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctidu_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctidu_fr_fr(dst, src)) }
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inst_fctidu_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIDU_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctidu_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctidu_dot_fr_fr(dst, src)) }
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inst_fctidz_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIDZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctidz_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctidz_fr_fr(dst, src)) }
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inst_fctidz_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIDZ_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctidz_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctidz_dot_fr_fr(dst, src)) }
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inst_fctiduz_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIDUZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiduz_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiduz_fr_fr(dst, src)) }
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inst_fctiduz_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIDUZ_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiduz_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiduz_dot_fr_fr(dst, src)) }
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inst_fctiw_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiw_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiw_fr_fr(dst, src)) }
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inst_fctiw_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIW_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiw_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiw_dot_fr_fr(dst, src)) }
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inst_fctiwu_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIWU, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiwu_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiwu_fr_fr(dst, src)) }
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inst_fctiwu_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIWU_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiwu_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiwu_dot_fr_fr(dst, src)) }
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inst_fctiwz_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIWZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiwz_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiwz_fr_fr(dst, src)) }
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inst_fctiwz_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIWZ_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiwz_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiwz_dot_fr_fr(dst, src)) }
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inst_fctiwuz_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIWUZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiwuz_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiwuz_fr_fr(dst, src)) }
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inst_fctiwuz_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCTIWUZ_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fctiwuz_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fctiwuz_dot_fr_fr(dst, src)) }
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inst_fcfid_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCFID, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fcfid_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcfid_fr_fr(dst, src)) }
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inst_fcfid_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCFID_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fcfid_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcfid_dot_fr_fr(dst, src)) }
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inst_fcfidu_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCFIDU, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fcfidu_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcfidu_fr_fr(dst, src)) }
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inst_fcfidu_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCFIDU_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fcfidu_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcfidu_dot_fr_fr(dst, src)) }
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inst_fcfids_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCFIDS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fcfids_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcfids_fr_fr(dst, src)) }
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inst_fcfids_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCFIDS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fcfids_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcfids_dot_fr_fr(dst, src)) }
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inst_fcfidus_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCFIDUS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fcfidus_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcfidus_fr_fr(dst, src)) }
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inst_fcfidus_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCFIDUS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_fcfidus_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcfidus_dot_fr_fr(dst, src)) }
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inst_frin_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRIN, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frin_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frin_fr_fr(dst, src)) }
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inst_frin_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRIN_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frin_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frin_dot_fr_fr(dst, src)) }
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inst_friz_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_friz_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_friz_fr_fr(dst, src)) }
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inst_friz_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRIZ_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_friz_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_friz_dot_fr_fr(dst, src)) }
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inst_frip_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRIP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frip_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frip_fr_fr(dst, src)) }
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inst_frip_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRIP_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frip_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frip_dot_fr_fr(dst, src)) }
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inst_frim_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRIM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frim_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frim_fr_fr(dst, src)) }
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inst_frim_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRIM_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_frim_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frim_dot_fr_fr(dst, src)) }
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inst_fcmpu_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMPU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fcmpu_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmpu_crf_fr_fr(dst, src, src2)) }
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inst_fcmpo_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fcmpo_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmpo_crf_fr_fr(dst, src, src2)) }
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inst_ftdiv_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FTDIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ftdiv_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ftdiv_crf_fr_fr(dst, src, src2)) }
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inst_ftsqrt_crf_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FTSQRT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ftsqrt_crf_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ftsqrt_crf_fr(dst, src)) }
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inst_fmrgew_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMRGEW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fmrgew_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmrgew_fr_fr_fr(dst, src, src2)) }
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inst_fmrgow_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMRGOW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_fmrgow_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmrgow_fr_fr_fr(dst, src, src2)) }
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inst_lfs_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFS, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfs_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfs_fr_mem(dst, addr)) }
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inst_lfsu_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFSU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfsu_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfsu_fr_mem(dst, addr)) }
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inst_lfsx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFSX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfsx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfsx_fr_mem(dst, addr)) }
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inst_lfsux_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFSUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfsux_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfsux_fr_mem(dst, addr)) }
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inst_lfd_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfd_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfd_fr_mem(dst, addr)) }
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inst_lfdu_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFDU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfdu_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfdu_fr_mem(dst, addr)) }
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inst_lfdx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFDX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfdx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfdx_fr_mem(dst, addr)) }
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inst_lfdux_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFDUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfdux_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfdux_fr_mem(dst, addr)) }
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inst_lfiwax_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFIWAX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfiwax_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfiwax_fr_mem(dst, addr)) }
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inst_lfiwzx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFIWZX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfiwzx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfiwzx_fr_mem(dst, addr)) }
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inst_lfdp_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfdp_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfdp_fr_mem(dst, addr)) }
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inst_lfdpx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFDPX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfdpx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfdpx_fr_mem(dst, addr)) }
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inst_stfs_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFS, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfs_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfs_fr_mem(dst, addr)) }
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inst_stfsu_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFSU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfsu_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfsu_fr_mem(dst, addr)) }
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inst_stfsx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFSX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfsx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfsx_fr_mem(dst, addr)) }
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inst_stfsux_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFSUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfsux_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfsux_fr_mem(dst, addr)) }
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inst_stfd_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfd_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfd_fr_mem(dst, addr)) }
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inst_stfdu_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFDU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfdu_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfdu_fr_mem(dst, addr)) }
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inst_stfdx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFDX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfdx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfdx_fr_mem(dst, addr)) }
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inst_stfdux_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFDUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfdux_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfdux_fr_mem(dst, addr)) }
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inst_stfiwx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFIWX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfiwx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfiwx_fr_mem(dst, addr)) }
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inst_stfdp_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfdp_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfdp_fr_mem(dst, addr)) }
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inst_stfdpx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFDPX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfdpx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfdpx_fr_mem(dst, addr)) }
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inst_mffs_fr :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFFS, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mffs_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mffs_fr(dst)) }
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inst_mffs_dot_fr :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFFS_DOT, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mffs_dot_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mffs_dot_fr(dst)) }
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inst_mcrfs_crf_crf :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MCRFS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mcrfs_crf_crf :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mcrfs_crf_crf(dst, src)) }
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inst_mtfsb0_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTFSB0, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtfsb0_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtfsb0_crb(dst)) }
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inst_mtfsb0_dot_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTFSB0_DOT, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtfsb0_dot_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtfsb0_dot_crb(dst)) }
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inst_mtfsb1_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTFSB1, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtfsb1_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtfsb1_crb(dst)) }
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inst_mtfsb1_dot_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTFSB1_DOT, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtfsb1_dot_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtfsb1_dot_crb(dst)) }
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inst_mtfsfi_crf_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MTFSFI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_mtfsfi_crf_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mtfsfi_crf_imm(dst, imm)) }
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inst_mtfsfi_dot_crf_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MTFSFI_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_mtfsfi_dot_crf_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mtfsfi_dot_crf_imm(dst, imm)) }
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inst_mtfsf_imm_fr :: #force_inline proc "contextless" (imm: i64, dst: Register) -> Instruction { return Instruction{mnemonic = .MTFSF, operand_count = 2, length = 4, ops = {op_imm(imm), op_reg(dst), {}, {}}} }
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emit_mtfsf_imm_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register) { append(instructions, inst_mtfsf_imm_fr(imm, dst)) }
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inst_mtfsf_dot_imm_fr :: #force_inline proc "contextless" (imm: i64, dst: Register) -> Instruction { return Instruction{mnemonic = .MTFSF_DOT, operand_count = 2, length = 4, ops = {op_imm(imm), op_reg(dst), {}, {}}} }
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emit_mtfsf_dot_imm_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register) { append(instructions, inst_mtfsf_dot_imm_fr(imm, dst)) }
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inst_mfspr_r_spr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFSPR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mfspr_r_spr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mfspr_r_spr(dst, src)) }
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inst_mtspr_spr_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTSPR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtspr_spr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtspr_spr_r(dst, src)) }
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inst_mftb_r_spr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFTB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mftb_r_spr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mftb_r_spr(dst, src)) }
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inst_mfcr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfcr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfcr_r(dst)) }
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inst_mtcrf_imm_r :: #force_inline proc "contextless" (imm: i64, dst: Register) -> Instruction { return Instruction{mnemonic = .MTCRF, operand_count = 2, length = 4, ops = {op_imm(imm), op_reg(dst), {}, {}}} }
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emit_mtcrf_imm_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register) { append(instructions, inst_mtcrf_imm_r(imm, dst)) }
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inst_mtocrf_imm_r :: #force_inline proc "contextless" (imm: i64, dst: Register) -> Instruction { return Instruction{mnemonic = .MTOCRF, operand_count = 2, length = 4, ops = {op_imm(imm), op_reg(dst), {}, {}}} }
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emit_mtocrf_imm_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register) { append(instructions, inst_mtocrf_imm_r(imm, dst)) }
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inst_mfocrf_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MFOCRF, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_mfocrf_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mfocrf_r_imm(dst, imm)) }
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inst_mtmsr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTMSR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtmsr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtmsr_r(dst)) }
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inst_mfmsr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFMSR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfmsr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfmsr_r(dst)) }
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inst_mtmsrd_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTMSRD, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtmsrd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtmsrd_r(dst)) }
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inst_sc_hv_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SC_HV, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_sc_hv_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_sc_hv_imm(imm)) }
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inst_rfi_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .RFI, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_rfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rfi_none()) }
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inst_rfid_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .RFID, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_rfid_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rfid_none()) }
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inst_hrfid_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .HRFID, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_hrfid_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_hrfid_none()) }
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inst_sync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SYNC, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_sync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sync_none()) }
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inst_lwsync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .LWSYNC, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_lwsync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lwsync_none()) }
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inst_ptesync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PTESYNC, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_ptesync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ptesync_none()) }
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inst_eieio_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .EIEIO, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_eieio_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eieio_none()) }
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inst_isync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ISYNC, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_isync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_isync_none()) }
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inst_dcbt_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .DCBT, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_dcbt_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_dcbt_mem(addr)) }
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inst_dcbtst_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .DCBTST, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_dcbtst_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_dcbtst_mem(addr)) }
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inst_dcba_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .DCBA, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_dcba_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_dcba_mem(addr)) }
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inst_dcbf_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .DCBF, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_dcbf_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_dcbf_mem(addr)) }
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inst_dcbz_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .DCBZ, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_dcbz_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_dcbz_mem(addr)) }
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inst_dcbzl_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .DCBZL, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_dcbzl_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_dcbzl_mem(addr)) }
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inst_icbi_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .ICBI, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_icbi_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_icbi_mem(addr)) }
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inst_icbt_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .ICBT, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_icbt_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_icbt_mem(addr)) }
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inst_nap_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .NAP, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_nap_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nap_none()) }
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inst_wait_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WAIT, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_wait_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wait_none()) }
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inst_msync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .MSYNC, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_msync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_msync_none()) }
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inst_tlbie_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TLBIE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tlbie_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tlbie_r_r(dst, src)) }
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inst_tlbiel_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .TLBIEL, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_tlbiel_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbiel_r(dst)) }
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inst_tlbsync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TLBSYNC, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_tlbsync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbsync_none()) }
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inst_slbie_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .SLBIE, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_slbie_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_slbie_r(dst)) }
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inst_slbia_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SLBIA, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_slbia_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_slbia_none()) }
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inst_slbmte_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SLBMTE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_slbmte_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_slbmte_r_r(dst, src)) }
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inst_slbmfee_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SLBMFEE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_slbmfee_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_slbmfee_r_r(dst, src)) }
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inst_slbmfev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SLBMFEV, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_slbmfev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_slbmfev_r_r(dst, src)) }
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inst_slbsync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SLBSYNC, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_slbsync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_slbsync_none()) }
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inst_slbieg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SLBIEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_slbieg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_slbieg_r_r(dst, src)) }
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inst_darn_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DARN, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_darn_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_darn_r_imm(dst, imm)) }
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inst_vand_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vand_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vand_v_v_v(dst, src, src2)) }
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inst_vandc_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VANDC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vandc_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vandc_v_v_v(dst, src, src2)) }
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inst_vor_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vor_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vor_v_v_v(dst, src, src2)) }
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inst_vorc_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vorc_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorc_v_v_v(dst, src, src2)) }
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inst_vnor_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vnor_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnor_v_v_v(dst, src, src2)) }
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inst_vxor_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VXOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vxor_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vxor_v_v_v(dst, src, src2)) }
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inst_veqv_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEQV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_veqv_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_veqv_v_v_v(dst, src, src2)) }
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inst_vnand_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNAND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vnand_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnand_v_v_v(dst, src, src2)) }
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inst_vsel_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vsel_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vsel_v_v_v_v(dst, src, src2, src3)) }
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inst_vaddubm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDUBM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddubm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddubm_v_v_v(dst, src, src2)) }
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inst_vadduhm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDUHM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vadduhm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadduhm_v_v_v(dst, src, src2)) }
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inst_vadduwm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDUWM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vadduwm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadduwm_v_v_v(dst, src, src2)) }
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inst_vaddudm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDUDM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddudm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddudm_v_v_v(dst, src, src2)) }
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inst_vaddfp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddfp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddfp_v_v_v(dst, src, src2)) }
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inst_vsububm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBUBM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsububm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsububm_v_v_v(dst, src, src2)) }
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inst_vsubuhm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBUHM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubuhm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubuhm_v_v_v(dst, src, src2)) }
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inst_vsubuwm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBUWM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubuwm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubuwm_v_v_v(dst, src, src2)) }
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inst_vsubudm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBUDM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubudm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubudm_v_v_v(dst, src, src2)) }
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inst_vsubfp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubfp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubfp_v_v_v(dst, src, src2)) }
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inst_vaddcuw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDCUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddcuw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddcuw_v_v_v(dst, src, src2)) }
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inst_vaddcuq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDCUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddcuq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddcuq_v_v_v(dst, src, src2)) }
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inst_vaddecuq_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VADDECUQ, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vaddecuq_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vaddecuq_v_v_v_v(dst, src, src2, src3)) }
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inst_vaddeuqm_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VADDEUQM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vaddeuqm_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vaddeuqm_v_v_v_v(dst, src, src2, src3)) }
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inst_vsubcuw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBCUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubcuw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubcuw_v_v_v(dst, src, src2)) }
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inst_vsubcuq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBCUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubcuq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubcuq_v_v_v(dst, src, src2)) }
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inst_vsubecuq_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VSUBECUQ, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vsubecuq_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vsubecuq_v_v_v_v(dst, src, src2, src3)) }
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inst_vsubeuqm_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VSUBEUQM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vsubeuqm_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vsubeuqm_v_v_v_v(dst, src, src2, src3)) }
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inst_vaddubs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddubs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddubs_v_v_v(dst, src, src2)) }
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inst_vadduhs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDUHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vadduhs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadduhs_v_v_v(dst, src, src2)) }
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inst_vadduws_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDUWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vadduws_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadduws_v_v_v(dst, src, src2)) }
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inst_vaddsbs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDSBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddsbs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddsbs_v_v_v(dst, src, src2)) }
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inst_vaddshs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDSHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddshs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddshs_v_v_v(dst, src, src2)) }
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inst_vaddsws_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDSWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddsws_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddsws_v_v_v(dst, src, src2)) }
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inst_vsububs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsububs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsububs_v_v_v(dst, src, src2)) }
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inst_vsubuhs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBUHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubuhs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubuhs_v_v_v(dst, src, src2)) }
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inst_vsubuws_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBUWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubuws_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubuws_v_v_v(dst, src, src2)) }
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inst_vsubsbs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBSBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubsbs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubsbs_v_v_v(dst, src, src2)) }
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inst_vsubshs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBSHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubshs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubshs_v_v_v(dst, src, src2)) }
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inst_vsubsws_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBSWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubsws_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubsws_v_v_v(dst, src, src2)) }
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inst_vmulesb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULESB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulesb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulesb_v_v_v(dst, src, src2)) }
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inst_vmulesh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULESH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulesh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulesh_v_v_v(dst, src, src2)) }
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inst_vmulesw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULESW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulesw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulesw_v_v_v(dst, src, src2)) }
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inst_vmuleub_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULEUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmuleub_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmuleub_v_v_v(dst, src, src2)) }
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inst_vmuleuh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULEUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmuleuh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmuleuh_v_v_v(dst, src, src2)) }
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inst_vmuleuw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULEUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmuleuw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmuleuw_v_v_v(dst, src, src2)) }
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inst_vmulosb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULOSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulosb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulosb_v_v_v(dst, src, src2)) }
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inst_vmulosh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULOSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulosh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulosh_v_v_v(dst, src, src2)) }
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inst_vmulosw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULOSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulosw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulosw_v_v_v(dst, src, src2)) }
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inst_vmuloub_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULOUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmuloub_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmuloub_v_v_v(dst, src, src2)) }
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inst_vmulouh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULOUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulouh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulouh_v_v_v(dst, src, src2)) }
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inst_vmulouw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULOUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulouw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulouw_v_v_v(dst, src, src2)) }
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inst_vmuluwm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULUWM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmuluwm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmuluwm_v_v_v(dst, src, src2)) }
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inst_vmsumubm_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUMUBM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsumubm_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsumubm_v_v_v_v(dst, src, src2, src3)) }
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inst_vmsummbm_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUMMBM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsummbm_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsummbm_v_v_v_v(dst, src, src2, src3)) }
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inst_vmsumuhm_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUMUHM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsumuhm_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsumuhm_v_v_v_v(dst, src, src2, src3)) }
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inst_vmsumshm_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUMSHM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsumshm_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsumshm_v_v_v_v(dst, src, src2, src3)) }
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inst_vmsumuhs_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUMUHS, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsumuhs_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsumuhs_v_v_v_v(dst, src, src2, src3)) }
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inst_vmsumshs_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUMSHS, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsumshs_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsumshs_v_v_v_v(dst, src, src2, src3)) }
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inst_vmsumudm_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUMUDM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsumudm_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsumudm_v_v_v_v(dst, src, src2, src3)) }
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inst_vcmpequb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequb_v_v_v(dst, src, src2)) }
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inst_vcmpequb_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequb_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequb_dot_v_v_v(dst, src, src2)) }
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inst_vcmpequh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequh_v_v_v(dst, src, src2)) }
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inst_vcmpequh_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUH_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequh_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequh_dot_v_v_v(dst, src, src2)) }
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inst_vcmpequw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequw_v_v_v(dst, src, src2)) }
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inst_vcmpequw_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequw_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequw_dot_v_v_v(dst, src, src2)) }
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inst_vcmpequd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequd_v_v_v(dst, src, src2)) }
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inst_vcmpequd_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequd_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequd_dot_v_v_v(dst, src, src2)) }
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inst_vcmpneb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpneb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpneb_v_v_v(dst, src, src2)) }
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inst_vcmpneb_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpneb_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpneb_dot_v_v_v(dst, src, src2)) }
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inst_vcmpneh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpneh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpneh_v_v_v(dst, src, src2)) }
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inst_vcmpneh_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEH_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpneh_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpneh_dot_v_v_v(dst, src, src2)) }
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inst_vcmpnew_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpnew_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpnew_v_v_v(dst, src, src2)) }
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inst_vcmpnew_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpnew_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpnew_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgtsb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsb_v_v_v(dst, src, src2)) }
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inst_vcmpgtsb_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsb_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsb_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgtsh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsh_v_v_v(dst, src, src2)) }
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inst_vcmpgtsh_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSH_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsh_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsh_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgtsw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsw_v_v_v(dst, src, src2)) }
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inst_vcmpgtsw_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsw_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsw_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgtsd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsd_v_v_v(dst, src, src2)) }
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inst_vcmpgtsd_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsd_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsd_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgtub_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtub_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtub_v_v_v(dst, src, src2)) }
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inst_vcmpgtub_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtub_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtub_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgtuh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtuh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtuh_v_v_v(dst, src, src2)) }
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inst_vcmpgtuh_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUH_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtuh_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtuh_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgtuw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtuw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtuw_v_v_v(dst, src, src2)) }
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inst_vcmpgtuw_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtuw_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtuw_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgtud_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtud_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtud_v_v_v(dst, src, src2)) }
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inst_vcmpgtud_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtud_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtud_dot_v_v_v(dst, src, src2)) }
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inst_vcmpeqfp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpeqfp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpeqfp_v_v_v(dst, src, src2)) }
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inst_vcmpeqfp_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQFP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpeqfp_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpeqfp_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgefp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGEFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgefp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgefp_v_v_v(dst, src, src2)) }
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inst_vcmpgefp_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGEFP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgefp_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgefp_dot_v_v_v(dst, src, src2)) }
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inst_vcmpgtfp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtfp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtfp_v_v_v(dst, src, src2)) }
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inst_vcmpgtfp_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTFP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtfp_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtfp_dot_v_v_v(dst, src, src2)) }
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inst_vcmpbfp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPBFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpbfp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpbfp_v_v_v(dst, src, src2)) }
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inst_vcmpbfp_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPBFP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpbfp_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpbfp_dot_v_v_v(dst, src, src2)) }
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inst_vmaxsb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxsb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxsb_v_v_v(dst, src, src2)) }
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inst_vmaxsh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxsh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxsh_v_v_v(dst, src, src2)) }
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inst_vmaxsw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxsw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxsw_v_v_v(dst, src, src2)) }
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inst_vmaxsd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxsd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxsd_v_v_v(dst, src, src2)) }
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inst_vmaxub_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxub_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxub_v_v_v(dst, src, src2)) }
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inst_vmaxuh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxuh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxuh_v_v_v(dst, src, src2)) }
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inst_vmaxuw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxuw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxuw_v_v_v(dst, src, src2)) }
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inst_vmaxud_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxud_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxud_v_v_v(dst, src, src2)) }
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inst_vmaxfp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxfp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxfp_v_v_v(dst, src, src2)) }
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inst_vminsb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminsb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminsb_v_v_v(dst, src, src2)) }
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inst_vminsh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminsh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminsh_v_v_v(dst, src, src2)) }
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inst_vminsw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminsw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminsw_v_v_v(dst, src, src2)) }
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inst_vminsd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminsd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminsd_v_v_v(dst, src, src2)) }
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inst_vminub_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminub_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminub_v_v_v(dst, src, src2)) }
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inst_vminuh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminuh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminuh_v_v_v(dst, src, src2)) }
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inst_vminuw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminuw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminuw_v_v_v(dst, src, src2)) }
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inst_vminud_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminud_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminud_v_v_v(dst, src, src2)) }
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inst_vminfp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminfp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminfp_v_v_v(dst, src, src2)) }
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inst_vavgsb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAVGSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vavgsb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vavgsb_v_v_v(dst, src, src2)) }
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inst_vavgsh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAVGSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vavgsh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vavgsh_v_v_v(dst, src, src2)) }
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inst_vavgsw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAVGSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vavgsw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vavgsw_v_v_v(dst, src, src2)) }
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inst_vavgub_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAVGUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vavgub_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vavgub_v_v_v(dst, src, src2)) }
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inst_vavguh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAVGUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vavguh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vavguh_v_v_v(dst, src, src2)) }
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inst_vavguw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAVGUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vavguw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vavguw_v_v_v(dst, src, src2)) }
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inst_vsl_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsl_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsl_v_v_v(dst, src, src2)) }
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inst_vsr_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsr_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsr_v_v_v(dst, src, src2)) }
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inst_vslo_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSLO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vslo_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vslo_v_v_v(dst, src, src2)) }
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inst_vsro_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsro_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsro_v_v_v(dst, src, src2)) }
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inst_vslb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSLB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vslb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vslb_v_v_v(dst, src, src2)) }
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inst_vslh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSLH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vslh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vslh_v_v_v(dst, src, src2)) }
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inst_vslw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vslw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vslw_v_v_v(dst, src, src2)) }
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inst_vsld_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSLD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsld_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsld_v_v_v(dst, src, src2)) }
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inst_vsrb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrb_v_v_v(dst, src, src2)) }
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inst_vsrh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrh_v_v_v(dst, src, src2)) }
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inst_vsrw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrw_v_v_v(dst, src, src2)) }
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inst_vsrd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrd_v_v_v(dst, src, src2)) }
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inst_vsrab_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRAB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrab_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrab_v_v_v(dst, src, src2)) }
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inst_vsrah_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrah_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrah_v_v_v(dst, src, src2)) }
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inst_vsraw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsraw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsraw_v_v_v(dst, src, src2)) }
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inst_vsrad_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRAD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrad_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrad_v_v_v(dst, src, src2)) }
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inst_vrlb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrlb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrlb_v_v_v(dst, src, src2)) }
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inst_vrlh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrlh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrlh_v_v_v(dst, src, src2)) }
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inst_vrlw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrlw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrlw_v_v_v(dst, src, src2)) }
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inst_vrld_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrld_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrld_v_v_v(dst, src, src2)) }
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inst_vperm_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VPERM, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vperm_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vperm_v_v_v_v(dst, src, src2, src3)) }
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inst_vpermr_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VPERMR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vpermr_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vpermr_v_v_v_v(dst, src, src2, src3)) }
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inst_vsldoi_v_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSLDOI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vsldoi_v_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vsldoi_v_v_v_imm(dst, src, src2, imm)) }
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inst_vbpermq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBPERMQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vbpermq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbpermq_v_v_v(dst, src, src2)) }
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inst_vbpermd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBPERMD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vbpermd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbpermd_v_v_v(dst, src, src2)) }
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inst_vmrghb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGHB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrghb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrghb_v_v_v(dst, src, src2)) }
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inst_vmrghh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGHH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrghh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrghh_v_v_v(dst, src, src2)) }
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inst_vmrghw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrghw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrghw_v_v_v(dst, src, src2)) }
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inst_vmrglb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGLB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrglb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrglb_v_v_v(dst, src, src2)) }
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inst_vmrglh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGLH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrglh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrglh_v_v_v(dst, src, src2)) }
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inst_vmrglw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrglw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrglw_v_v_v(dst, src, src2)) }
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inst_vmrgew_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGEW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrgew_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrgew_v_v_v(dst, src, src2)) }
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inst_vmrgow_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGOW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrgow_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrgow_v_v_v(dst, src, src2)) }
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inst_vspltb_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSPLTB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vspltb_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vspltb_v_v_imm(dst, src, imm)) }
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inst_vsplth_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSPLTH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vsplth_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsplth_v_v_imm(dst, src, imm)) }
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inst_vspltw_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSPLTW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vspltw_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vspltw_v_v_imm(dst, src, imm)) }
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inst_vspltisb_v_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSPLTISB, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_vspltisb_v_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vspltisb_v_simm(dst, imm)) }
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inst_vspltish_v_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSPLTISH, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_vspltish_v_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vspltish_v_simm(dst, imm)) }
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inst_vspltisw_v_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSPLTISW, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_vspltisw_v_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vspltisw_v_simm(dst, imm)) }
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inst_vpkpx_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkpx_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkpx_v_v_v(dst, src, src2)) }
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inst_vpkuhum_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKUHUM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkuhum_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkuhum_v_v_v(dst, src, src2)) }
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inst_vpkuwum_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKUWUM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkuwum_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkuwum_v_v_v(dst, src, src2)) }
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inst_vpkudum_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKUDUM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkudum_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkudum_v_v_v(dst, src, src2)) }
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inst_vpkuhus_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKUHUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkuhus_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkuhus_v_v_v(dst, src, src2)) }
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inst_vpkuwus_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKUWUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkuwus_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkuwus_v_v_v(dst, src, src2)) }
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inst_vpkudus_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKUDUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkudus_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkudus_v_v_v(dst, src, src2)) }
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inst_vpkshus_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKSHUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkshus_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkshus_v_v_v(dst, src, src2)) }
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inst_vpkswus_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKSWUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkswus_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkswus_v_v_v(dst, src, src2)) }
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inst_vpksdus_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKSDUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpksdus_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpksdus_v_v_v(dst, src, src2)) }
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inst_vpkshss_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKSHSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkshss_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkshss_v_v_v(dst, src, src2)) }
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inst_vpkswss_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKSWSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpkswss_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpkswss_v_v_v(dst, src, src2)) }
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inst_vpksdss_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPKSDSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpksdss_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpksdss_v_v_v(dst, src, src2)) }
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inst_vupkhsb_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUPKHSB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vupkhsb_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vupkhsb_v_v(dst, src)) }
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inst_vupkhsh_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUPKHSH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vupkhsh_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vupkhsh_v_v(dst, src)) }
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inst_vupkhsw_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUPKHSW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vupkhsw_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vupkhsw_v_v(dst, src)) }
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inst_vupklsb_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUPKLSB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vupklsb_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vupklsb_v_v(dst, src)) }
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inst_vupklsh_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUPKLSH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vupklsh_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vupklsh_v_v(dst, src)) }
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inst_vupklsw_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUPKLSW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vupklsw_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vupklsw_v_v(dst, src)) }
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inst_vupkhpx_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUPKHPX, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vupkhpx_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vupkhpx_v_v(dst, src)) }
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inst_vupklpx_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUPKLPX, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vupklpx_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vupklpx_v_v(dst, src)) }
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inst_vcipher_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCIPHER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcipher_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcipher_v_v_v(dst, src, src2)) }
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inst_vcipherlast_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCIPHERLAST, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcipherlast_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcipherlast_v_v_v(dst, src, src2)) }
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inst_vncipher_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNCIPHER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vncipher_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vncipher_v_v_v(dst, src, src2)) }
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inst_vncipherlast_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNCIPHERLAST, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vncipherlast_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vncipherlast_v_v_v(dst, src, src2)) }
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inst_vsbox_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSBOX, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vsbox_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vsbox_v_v(dst, src)) }
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inst_vshasigmaw_v_v_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .VSHASIGMAW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_vshasigmaw_v_v_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_vshasigmaw_v_v_imm_imm(dst, src, imm, imm2)) }
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inst_vshasigmad_v_v_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .VSHASIGMAD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_vshasigmad_v_v_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_vshasigmad_v_v_imm_imm(dst, src, imm, imm2)) }
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inst_vpmsumb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMSUMB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpmsumb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmsumb_v_v_v(dst, src, src2)) }
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inst_vpmsumh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMSUMH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpmsumh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmsumh_v_v_v(dst, src, src2)) }
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inst_vpmsumw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMSUMW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpmsumw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmsumw_v_v_v(dst, src, src2)) }
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inst_vpmsumd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMSUMD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpmsumd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmsumd_v_v_v(dst, src, src2)) }
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inst_vrfim_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRFIM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrfim_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrfim_v_v(dst, src)) }
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inst_vrfin_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRFIN, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrfin_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrfin_v_v(dst, src)) }
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inst_vrfip_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRFIP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrfip_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrfip_v_v(dst, src)) }
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inst_vrfiz_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRFIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrfiz_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrfiz_v_v(dst, src)) }
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inst_vexptefp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXPTEFP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vexptefp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vexptefp_v_v(dst, src)) }
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inst_vlogefp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VLOGEFP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vlogefp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vlogefp_v_v(dst, src)) }
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inst_vrefp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREFP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrefp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrefp_v_v(dst, src)) }
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inst_vrsqrtefp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTEFP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrsqrtefp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrtefp_v_v(dst, src)) }
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inst_vmaddfp_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMADDFP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmaddfp_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmaddfp_v_v_v_v(dst, src, src2, src3)) }
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inst_vnmsubfp_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VNMSUBFP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vnmsubfp_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vnmsubfp_v_v_v_v(dst, src, src2, src3)) }
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inst_vcfsx_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCFSX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vcfsx_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcfsx_v_v_imm(dst, src, imm)) }
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inst_vcfux_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCFUX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vcfux_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcfux_v_v_imm(dst, src, imm)) }
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inst_vctsxs_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCTSXS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vctsxs_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vctsxs_v_v_imm(dst, src, imm)) }
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inst_vctuxs_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCTUXS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vctuxs_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vctuxs_v_v_imm(dst, src, imm)) }
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inst_lvx_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LVX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lvx_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lvx_v_mem(dst, addr)) }
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inst_lvxl_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LVXL, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lvxl_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lvxl_v_mem(dst, addr)) }
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inst_lvebx_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LVEBX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lvebx_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lvebx_v_mem(dst, addr)) }
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inst_lvehx_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LVEHX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lvehx_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lvehx_v_mem(dst, addr)) }
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inst_lvewx_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LVEWX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lvewx_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lvewx_v_mem(dst, addr)) }
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inst_lvsl_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LVSL, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lvsl_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lvsl_v_mem(dst, addr)) }
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inst_lvsr_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LVSR, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lvsr_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lvsr_v_mem(dst, addr)) }
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inst_stvx_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STVX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stvx_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stvx_v_mem(dst, addr)) }
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inst_stvxl_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STVXL, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stvxl_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stvxl_v_mem(dst, addr)) }
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inst_stvebx_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STVEBX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stvebx_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stvebx_v_mem(dst, addr)) }
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inst_stvehx_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STVEHX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stvehx_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stvehx_v_mem(dst, addr)) }
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inst_stvewx_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STVEWX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stvewx_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stvewx_v_mem(dst, addr)) }
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inst_mfvscr_v :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFVSCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfvscr_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfvscr_v(dst)) }
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inst_mtvscr_v :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTVSCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtvscr_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtvscr_v(dst)) }
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inst_vabsdub_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABSDUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vabsdub_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabsdub_v_v_v(dst, src, src2)) }
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inst_vabsduh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABSDUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vabsduh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabsduh_v_v_v(dst, src, src2)) }
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inst_vabsduw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABSDUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vabsduw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabsduw_v_v_v(dst, src, src2)) }
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inst_vextsb2w_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTSB2W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextsb2w_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextsb2w_v_v(dst, src)) }
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inst_vextsh2w_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTSH2W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextsh2w_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextsh2w_v_v(dst, src)) }
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inst_vextsb2d_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTSB2D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextsb2d_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextsb2d_v_v(dst, src)) }
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inst_vextsh2d_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTSH2D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextsh2d_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextsh2d_v_v(dst, src)) }
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inst_vextsw2d_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTSW2D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextsw2d_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextsw2d_v_v(dst, src)) }
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inst_vprtybw_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPRTYBW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vprtybw_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vprtybw_v_v(dst, src)) }
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inst_vprtybd_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPRTYBD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vprtybd_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vprtybd_v_v(dst, src)) }
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inst_vprtybq_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPRTYBQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vprtybq_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vprtybq_v_v(dst, src)) }
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inst_vrlwnm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLWNM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrlwnm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrlwnm_v_v_v(dst, src, src2)) }
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inst_vrldnm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLDNM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrldnm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrldnm_v_v_v(dst, src, src2)) }
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inst_vrlwmi_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLWMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrlwmi_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrlwmi_v_v_v(dst, src, src2)) }
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inst_vrldmi_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLDMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrldmi_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrldmi_v_v_v(dst, src, src2)) }
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inst_vcmpnezb_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEZB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpnezb_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpnezb_v_v_v(dst, src, src2)) }
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inst_vcmpnezb_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEZB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpnezb_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpnezb_dot_v_v_v(dst, src, src2)) }
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inst_vcmpnezh_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEZH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpnezh_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpnezh_v_v_v(dst, src, src2)) }
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inst_vcmpnezh_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEZH_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpnezh_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpnezh_dot_v_v_v(dst, src, src2)) }
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inst_vcmpnezw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEZW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpnezw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpnezw_v_v_v(dst, src, src2)) }
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inst_vcmpnezw_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPNEZW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpnezw_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpnezw_dot_v_v_v(dst, src, src2)) }
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inst_vclzb_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vclzb_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclzb_v_v(dst, src)) }
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inst_vclzh_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vclzh_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclzh_v_v(dst, src)) }
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inst_vclzw_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vclzw_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclzw_v_v(dst, src)) }
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inst_vclzd_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vclzd_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclzd_v_v(dst, src)) }
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inst_vctzb_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCTZB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vctzb_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vctzb_v_v(dst, src)) }
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inst_vctzh_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCTZH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vctzh_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vctzh_v_v(dst, src)) }
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inst_vctzw_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCTZW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vctzw_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vctzw_v_v(dst, src)) }
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inst_vctzd_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCTZD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vctzd_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vctzd_v_v(dst, src)) }
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inst_vpopcntb_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPOPCNTB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vpopcntb_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpopcntb_v_v(dst, src)) }
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inst_vpopcnth_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPOPCNTH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vpopcnth_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpopcnth_v_v(dst, src)) }
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inst_vpopcntw_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPOPCNTW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vpopcntw_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpopcntw_v_v(dst, src)) }
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inst_vpopcntd_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPOPCNTD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vpopcntd_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpopcntd_v_v(dst, src)) }
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inst_vextractub_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXTRACTUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vextractub_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vextractub_v_v_imm(dst, src, imm)) }
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inst_vextractuh_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXTRACTUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vextractuh_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vextractuh_v_v_imm(dst, src, imm)) }
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inst_vextractuw_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXTRACTUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vextractuw_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vextractuw_v_v_imm(dst, src, imm)) }
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inst_vextractd_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXTRACTD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vextractd_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vextractd_v_v_imm(dst, src, imm)) }
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inst_vinsertb_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VINSERTB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vinsertb_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vinsertb_v_v_imm(dst, src, imm)) }
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inst_vinserth_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VINSERTH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vinserth_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vinserth_v_v_imm(dst, src, imm)) }
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inst_vinsertw_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VINSERTW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vinsertw_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vinsertw_v_v_imm(dst, src, imm)) }
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inst_vinsertd_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VINSERTD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vinsertd_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vinsertd_v_v_imm(dst, src, imm)) }
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inst_vslv_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSLV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vslv_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vslv_v_v_v(dst, src, src2)) }
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inst_vsrv_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrv_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrv_v_v_v(dst, src, src2)) }
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inst_vmul10uq_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMUL10UQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmul10uq_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmul10uq_v_v(dst, src)) }
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inst_vmul10cuq_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMUL10CUQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vmul10cuq_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmul10cuq_v_v(dst, src)) }
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inst_vmul10euq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMUL10EUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmul10euq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmul10euq_v_v_v(dst, src, src2)) }
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inst_vmul10ecuq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMUL10ECUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmul10ecuq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmul10ecuq_v_v_v(dst, src, src2)) }
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inst_lxsdx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXSDX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxsdx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxsdx_vs_mem(dst, addr)) }
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inst_lxsiwax_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXSIWAX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxsiwax_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxsiwax_vs_mem(dst, addr)) }
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inst_lxsiwzx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXSIWZX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxsiwzx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxsiwzx_vs_mem(dst, addr)) }
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inst_lxvd2x_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXVD2X, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxvd2x_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxvd2x_vs_mem(dst, addr)) }
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inst_lxvdsx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXVDSX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxvdsx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxvdsx_vs_mem(dst, addr)) }
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inst_lxvw4x_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXVW4X, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxvw4x_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxvw4x_vs_mem(dst, addr)) }
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inst_stxsdx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXSDX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxsdx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxsdx_vs_mem(dst, addr)) }
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inst_stxsiwx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXSIWX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxsiwx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxsiwx_vs_mem(dst, addr)) }
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inst_stxvd2x_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXVD2X, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxvd2x_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxvd2x_vs_mem(dst, addr)) }
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inst_stxvw4x_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXVW4X, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxvw4x_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxvw4x_vs_mem(dst, addr)) }
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inst_lxsspx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXSSPX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxsspx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxsspx_vs_mem(dst, addr)) }
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inst_stxsspx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXSSPX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxsspx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxsspx_vs_mem(dst, addr)) }
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inst_lxv_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxv_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxv_vs_mem(dst, addr)) }
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inst_stxv_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxv_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxv_vs_mem(dst, addr)) }
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inst_lxvh8x_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXVH8X, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxvh8x_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxvh8x_vs_mem(dst, addr)) }
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inst_lxvb16x_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXVB16X, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxvb16x_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxvb16x_vs_mem(dst, addr)) }
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inst_lxvl_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvl_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvl_vs_r_r(dst, src, src2)) }
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inst_lxvll_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVLL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvll_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvll_vs_r_r(dst, src, src2)) }
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inst_stxvh8x_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXVH8X, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxvh8x_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxvh8x_vs_mem(dst, addr)) }
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inst_stxvb16x_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXVB16X, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxvb16x_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxvb16x_vs_mem(dst, addr)) }
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inst_stxvl_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvl_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvl_vs_r_r(dst, src, src2)) }
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inst_stxvll_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVLL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvll_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvll_vs_r_r(dst, src, src2)) }
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inst_lxvx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXVX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxvx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxvx_vs_mem(dst, addr)) }
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inst_stxvx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXVX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxvx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxvx_vs_mem(dst, addr)) }
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inst_lxsibzx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXSIBZX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxsibzx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxsibzx_vs_mem(dst, addr)) }
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inst_lxsihzx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXSIHZX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxsihzx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxsihzx_vs_mem(dst, addr)) }
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inst_stxsibx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXSIBX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxsibx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxsibx_vs_mem(dst, addr)) }
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inst_stxsihx_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXSIHX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxsihx_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxsihx_vs_mem(dst, addr)) }
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inst_lxsd_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXSD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxsd_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxsd_v_mem(dst, addr)) }
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inst_stxsd_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXSD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxsd_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxsd_v_mem(dst, addr)) }
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inst_lxssp_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXSSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxssp_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxssp_v_mem(dst, addr)) }
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inst_stxssp_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXSSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxssp_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxssp_v_mem(dst, addr)) }
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inst_xsaddsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSADDSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsaddsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsaddsp_vs_vs_vs(dst, src, src2)) }
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inst_xsadddp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSADDDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsadddp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsadddp_vs_vs_vs(dst, src, src2)) }
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inst_xssubsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSSUBSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xssubsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xssubsp_vs_vs_vs(dst, src, src2)) }
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inst_xssubdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSSUBDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xssubdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xssubdp_vs_vs_vs(dst, src, src2)) }
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inst_xsmulsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMULSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmulsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmulsp_vs_vs_vs(dst, src, src2)) }
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inst_xsmuldp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMULDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmuldp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmuldp_vs_vs_vs(dst, src, src2)) }
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inst_xsdivsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSDIVSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsdivsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsdivsp_vs_vs_vs(dst, src, src2)) }
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inst_xsdivdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSDIVDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsdivdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsdivdp_vs_vs_vs(dst, src, src2)) }
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inst_xssqrtsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSSQRTSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xssqrtsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xssqrtsp_vs_vs(dst, src)) }
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inst_xssqrtdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSSQRTDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xssqrtdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xssqrtdp_vs_vs(dst, src)) }
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inst_xsresp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSRESP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsresp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsresp_vs_vs(dst, src)) }
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inst_xsredp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSREDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsredp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsredp_vs_vs(dst, src)) }
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inst_xsrsqrtesp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSRSQRTESP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsrsqrtesp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsrsqrtesp_vs_vs(dst, src)) }
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inst_xsrsqrtedp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSRSQRTEDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsrsqrtedp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsrsqrtedp_vs_vs(dst, src)) }
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inst_xsmaddasp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMADDASP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaddasp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaddasp_vs_vs_vs(dst, src, src2)) }
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inst_xsmaddadp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMADDADP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaddadp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaddadp_vs_vs_vs(dst, src, src2)) }
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inst_xsmaddmsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMADDMSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaddmsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaddmsp_vs_vs_vs(dst, src, src2)) }
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inst_xsmaddmdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMADDMDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaddmdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaddmdp_vs_vs_vs(dst, src, src2)) }
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inst_xsmsubasp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMSUBASP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmsubasp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmsubasp_vs_vs_vs(dst, src, src2)) }
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inst_xsmsubadp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMSUBADP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmsubadp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmsubadp_vs_vs_vs(dst, src, src2)) }
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inst_xsmsubmsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMSUBMSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmsubmsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmsubmsp_vs_vs_vs(dst, src, src2)) }
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inst_xsmsubmdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMSUBMDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmsubmdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmsubmdp_vs_vs_vs(dst, src, src2)) }
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inst_xsnmaddasp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMADDASP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmaddasp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmaddasp_vs_vs_vs(dst, src, src2)) }
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inst_xsnmaddadp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMADDADP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmaddadp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmaddadp_vs_vs_vs(dst, src, src2)) }
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inst_xsnmaddmsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMADDMSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmaddmsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmaddmsp_vs_vs_vs(dst, src, src2)) }
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inst_xsnmaddmdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMADDMDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmaddmdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmaddmdp_vs_vs_vs(dst, src, src2)) }
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inst_xsnmsubasp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMSUBASP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmsubasp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmsubasp_vs_vs_vs(dst, src, src2)) }
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inst_xsnmsubadp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMSUBADP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmsubadp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmsubadp_vs_vs_vs(dst, src, src2)) }
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inst_xsnmsubmsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMSUBMSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmsubmsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmsubmsp_vs_vs_vs(dst, src, src2)) }
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inst_xsnmsubmdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMSUBMDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmsubmdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmsubmdp_vs_vs_vs(dst, src, src2)) }
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inst_xsmaxdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMAXDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaxdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaxdp_vs_vs_vs(dst, src, src2)) }
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inst_xsmindp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMINDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmindp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmindp_vs_vs_vs(dst, src, src2)) }
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inst_xsmaxcdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMAXCDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaxcdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaxcdp_vs_vs_vs(dst, src, src2)) }
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inst_xsmincdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMINCDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmincdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmincdp_vs_vs_vs(dst, src, src2)) }
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inst_xsmaxjdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMAXJDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaxjdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaxjdp_vs_vs_vs(dst, src, src2)) }
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inst_xsminjdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMINJDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsminjdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsminjdp_vs_vs_vs(dst, src, src2)) }
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inst_xscmpodp_crf_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPODP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpodp_crf_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpodp_crf_vs_vs(dst, src, src2)) }
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inst_xscmpudp_crf_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPUDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpudp_crf_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpudp_crf_vs_vs(dst, src, src2)) }
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inst_xscmpeqdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPEQDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpeqdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpeqdp_vs_vs_vs(dst, src, src2)) }
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inst_xscmpgtdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPGTDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpgtdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpgtdp_vs_vs_vs(dst, src, src2)) }
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inst_xscmpgedp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPGEDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpgedp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpgedp_vs_vs_vs(dst, src, src2)) }
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inst_xscpsgndp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCPSGNDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscpsgndp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscpsgndp_vs_vs_vs(dst, src, src2)) }
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inst_xsabsdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSABSDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsabsdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsabsdp_vs_vs(dst, src)) }
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inst_xsnabsdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSNABSDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsnabsdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsnabsdp_vs_vs(dst, src)) }
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inst_xsnegdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSNEGDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsnegdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsnegdp_vs_vs(dst, src)) }
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inst_xscvdpsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVDPSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvdpsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvdpsp_vs_vs(dst, src)) }
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inst_xscvspdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVSPDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvspdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvspdp_vs_vs(dst, src)) }
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inst_xscvdpsxds_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVDPSXDS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvdpsxds_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvdpsxds_vs_vs(dst, src)) }
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inst_xscvdpuxds_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVDPUXDS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvdpuxds_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvdpuxds_vs_vs(dst, src)) }
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inst_xscvsxddp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVSXDDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvsxddp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvsxddp_vs_vs(dst, src)) }
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inst_xscvuxddp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVUXDDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvuxddp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvuxddp_vs_vs(dst, src)) }
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inst_xscvdpsxws_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVDPSXWS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvdpsxws_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvdpsxws_vs_vs(dst, src)) }
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inst_xscvdpuxws_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVDPUXWS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvdpuxws_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvdpuxws_vs_vs(dst, src)) }
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inst_xscvdphp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVDPHP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvdphp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvdphp_vs_vs(dst, src)) }
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inst_xscvhpdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVHPDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvhpdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvhpdp_vs_vs(dst, src)) }
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inst_xscvspdpn_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVSPDPN, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvspdpn_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvspdpn_vs_vs(dst, src)) }
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inst_xscvdpspn_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVDPSPN, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvdpspn_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvdpspn_vs_vs(dst, src)) }
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inst_xsrdpi_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSRDPI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsrdpi_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsrdpi_vs_vs(dst, src)) }
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inst_xsrdpim_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSRDPIM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsrdpim_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsrdpim_vs_vs(dst, src)) }
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inst_xsrdpip_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSRDPIP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsrdpip_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsrdpip_vs_vs(dst, src)) }
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inst_xsrdpiz_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSRDPIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsrdpiz_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsrdpiz_vs_vs(dst, src)) }
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inst_xsrdpic_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSRDPIC, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsrdpic_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsrdpic_vs_vs(dst, src)) }
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inst_xsrsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSRSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsrsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsrsp_vs_vs(dst, src)) }
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inst_xsiexpdp_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSIEXPDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsiexpdp_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsiexpdp_vs_r_r(dst, src, src2)) }
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inst_xsxexpdp_r_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSXEXPDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsxexpdp_r_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsxexpdp_r_vs(dst, src)) }
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inst_xsxsigdp_r_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSXSIGDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsxsigdp_r_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsxsigdp_r_vs(dst, src)) }
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inst_xvaddsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVADDSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvaddsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvaddsp_vs_vs_vs(dst, src, src2)) }
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inst_xvadddp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVADDDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvadddp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvadddp_vs_vs_vs(dst, src, src2)) }
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inst_xvsubsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVSUBSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvsubsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvsubsp_vs_vs_vs(dst, src, src2)) }
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inst_xvsubdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVSUBDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvsubdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvsubdp_vs_vs_vs(dst, src, src2)) }
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inst_xvmulsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMULSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmulsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmulsp_vs_vs_vs(dst, src, src2)) }
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inst_xvmuldp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMULDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmuldp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmuldp_vs_vs_vs(dst, src, src2)) }
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inst_xvdivsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVDIVSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvdivsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvdivsp_vs_vs_vs(dst, src, src2)) }
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inst_xvdivdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVDIVDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvdivdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvdivdp_vs_vs_vs(dst, src, src2)) }
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inst_xvsqrtsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVSQRTSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvsqrtsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvsqrtsp_vs_vs(dst, src)) }
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inst_xvsqrtdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVSQRTDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvsqrtdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvsqrtdp_vs_vs(dst, src)) }
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inst_xvresp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRESP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvresp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvresp_vs_vs(dst, src)) }
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inst_xvredp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVREDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvredp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvredp_vs_vs(dst, src)) }
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inst_xvrsqrtesp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRSQRTESP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrsqrtesp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrsqrtesp_vs_vs(dst, src)) }
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inst_xvrsqrtedp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRSQRTEDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrsqrtedp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrsqrtedp_vs_vs(dst, src)) }
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inst_xvmaddasp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMADDASP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmaddasp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmaddasp_vs_vs_vs(dst, src, src2)) }
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inst_xvmaddadp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMADDADP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmaddadp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmaddadp_vs_vs_vs(dst, src, src2)) }
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inst_xvmaddmsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMADDMSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmaddmsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmaddmsp_vs_vs_vs(dst, src, src2)) }
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inst_xvmaddmdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMADDMDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmaddmdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmaddmdp_vs_vs_vs(dst, src, src2)) }
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inst_xvmsubasp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMSUBASP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmsubasp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmsubasp_vs_vs_vs(dst, src, src2)) }
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inst_xvmsubadp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMSUBADP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmsubadp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmsubadp_vs_vs_vs(dst, src, src2)) }
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inst_xvmsubmsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMSUBMSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmsubmsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmsubmsp_vs_vs_vs(dst, src, src2)) }
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inst_xvmsubmdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMSUBMDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmsubmdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmsubmdp_vs_vs_vs(dst, src, src2)) }
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inst_xvnmaddasp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVNMADDASP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvnmaddasp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvnmaddasp_vs_vs_vs(dst, src, src2)) }
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inst_xvnmaddadp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVNMADDADP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvnmaddadp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvnmaddadp_vs_vs_vs(dst, src, src2)) }
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inst_xvnmaddmsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVNMADDMSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvnmaddmsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvnmaddmsp_vs_vs_vs(dst, src, src2)) }
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inst_xvnmaddmdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVNMADDMDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvnmaddmdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvnmaddmdp_vs_vs_vs(dst, src, src2)) }
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inst_xvnmsubasp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVNMSUBASP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvnmsubasp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvnmsubasp_vs_vs_vs(dst, src, src2)) }
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inst_xvnmsubadp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVNMSUBADP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvnmsubadp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvnmsubadp_vs_vs_vs(dst, src, src2)) }
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inst_xvnmsubmsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVNMSUBMSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvnmsubmsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvnmsubmsp_vs_vs_vs(dst, src, src2)) }
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inst_xvnmsubmdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVNMSUBMDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvnmsubmdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvnmsubmdp_vs_vs_vs(dst, src, src2)) }
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inst_xvmaxsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMAXSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmaxsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmaxsp_vs_vs_vs(dst, src, src2)) }
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inst_xvmaxdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMAXDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmaxdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmaxdp_vs_vs_vs(dst, src, src2)) }
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inst_xvminsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMINSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvminsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvminsp_vs_vs_vs(dst, src, src2)) }
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inst_xvmindp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVMINDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvmindp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvmindp_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpeqsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPEQSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpeqsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpeqsp_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpeqsp_dot_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPEQSP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpeqsp_dot_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpeqsp_dot_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpeqdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPEQDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpeqdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpeqdp_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpeqdp_dot_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPEQDP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpeqdp_dot_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpeqdp_dot_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpgtsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPGTSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpgtsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpgtsp_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpgtsp_dot_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPGTSP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpgtsp_dot_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpgtsp_dot_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpgtdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPGTDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpgtdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpgtdp_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpgtdp_dot_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPGTDP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpgtdp_dot_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpgtdp_dot_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpgesp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPGESP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpgesp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpgesp_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpgesp_dot_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPGESP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpgesp_dot_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpgesp_dot_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpgedp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPGEDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpgedp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpgedp_vs_vs_vs(dst, src, src2)) }
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inst_xvcmpgedp_dot_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCMPGEDP_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcmpgedp_dot_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcmpgedp_dot_vs_vs_vs(dst, src, src2)) }
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inst_xvcpsgnsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCPSGNSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcpsgnsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcpsgnsp_vs_vs_vs(dst, src, src2)) }
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inst_xvcpsgndp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVCPSGNDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvcpsgndp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvcpsgndp_vs_vs_vs(dst, src, src2)) }
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inst_xvabssp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVABSSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvabssp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvabssp_vs_vs(dst, src)) }
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inst_xvabsdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVABSDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvabsdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvabsdp_vs_vs(dst, src)) }
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inst_xvnabssp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVNABSSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvnabssp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvnabssp_vs_vs(dst, src)) }
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inst_xvnabsdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVNABSDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvnabsdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvnabsdp_vs_vs(dst, src)) }
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inst_xvnegsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVNEGSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvnegsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvnegsp_vs_vs(dst, src)) }
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inst_xvnegdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVNEGDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvnegdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvnegdp_vs_vs(dst, src)) }
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inst_xvcvspdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSPDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvspdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvspdp_vs_vs(dst, src)) }
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inst_xvcvdpsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVDPSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvdpsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvdpsp_vs_vs(dst, src)) }
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inst_xvcvspsxds_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSPSXDS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvspsxds_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvspsxds_vs_vs(dst, src)) }
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inst_xvcvspuxds_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSPUXDS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvspuxds_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvspuxds_vs_vs(dst, src)) }
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inst_xvcvdpsxds_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVDPSXDS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvdpsxds_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvdpsxds_vs_vs(dst, src)) }
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inst_xvcvdpuxds_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVDPUXDS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvdpuxds_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvdpuxds_vs_vs(dst, src)) }
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inst_xvcvspsxws_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSPSXWS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvspsxws_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvspsxws_vs_vs(dst, src)) }
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inst_xvcvspuxws_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSPUXWS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvspuxws_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvspuxws_vs_vs(dst, src)) }
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inst_xvcvdpsxws_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVDPSXWS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvdpsxws_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvdpsxws_vs_vs(dst, src)) }
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inst_xvcvdpuxws_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVDPUXWS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvdpuxws_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvdpuxws_vs_vs(dst, src)) }
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inst_xvcvsxdsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSXDSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvsxdsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvsxdsp_vs_vs(dst, src)) }
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inst_xvcvuxdsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVUXDSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvuxdsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvuxdsp_vs_vs(dst, src)) }
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inst_xvcvsxddp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSXDDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvsxddp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvsxddp_vs_vs(dst, src)) }
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inst_xvcvuxddp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVUXDDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvuxddp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvuxddp_vs_vs(dst, src)) }
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inst_xvcvsxwsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSXWSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvsxwsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvsxwsp_vs_vs(dst, src)) }
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inst_xvcvuxwsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVUXWSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvuxwsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvuxwsp_vs_vs(dst, src)) }
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inst_xvcvsxwdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSXWDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvsxwdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvsxwdp_vs_vs(dst, src)) }
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inst_xvcvuxwdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVUXWDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvuxwdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvuxwdp_vs_vs(dst, src)) }
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inst_xvrspi_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRSPI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrspi_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrspi_vs_vs(dst, src)) }
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inst_xvrspim_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRSPIM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrspim_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrspim_vs_vs(dst, src)) }
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inst_xvrspip_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRSPIP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrspip_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrspip_vs_vs(dst, src)) }
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inst_xvrspiz_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRSPIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrspiz_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrspiz_vs_vs(dst, src)) }
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inst_xvrspic_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRSPIC, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrspic_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrspic_vs_vs(dst, src)) }
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inst_xvrdpi_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRDPI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrdpi_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrdpi_vs_vs(dst, src)) }
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inst_xvrdpim_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRDPIM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrdpim_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrdpim_vs_vs(dst, src)) }
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inst_xvrdpip_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRDPIP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrdpip_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrdpip_vs_vs(dst, src)) }
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inst_xvrdpiz_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRDPIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrdpiz_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrdpiz_vs_vs(dst, src)) }
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inst_xvrdpic_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVRDPIC, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvrdpic_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvrdpic_vs_vs(dst, src)) }
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inst_xviexpsp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVIEXPSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xviexpsp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xviexpsp_vs_vs_vs(dst, src, src2)) }
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inst_xviexpdp_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVIEXPDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xviexpdp_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xviexpdp_vs_vs_vs(dst, src, src2)) }
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inst_xvxexpsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVXEXPSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvxexpsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvxexpsp_vs_vs(dst, src)) }
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inst_xvxexpdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVXEXPDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvxexpdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvxexpdp_vs_vs(dst, src)) }
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inst_xvxsigsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVXSIGSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvxsigsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvxsigsp_vs_vs(dst, src)) }
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inst_xvxsigdp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVXSIGDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvxsigdp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvxsigdp_vs_vs(dst, src)) }
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inst_xvtstdcsp_vs_vs_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XVTSTDCSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xvtstdcsp_vs_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xvtstdcsp_vs_vs_imm(dst, src, imm)) }
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inst_xvtstdcdp_vs_vs_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XVTSTDCDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xvtstdcdp_vs_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xvtstdcdp_vs_vs_imm(dst, src, imm)) }
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inst_xststdcsp_crf_vs_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XSTSTDCSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xststdcsp_crf_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xststdcsp_crf_vs_imm(dst, src, imm)) }
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inst_xststdcdp_crf_vs_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XSTSTDCDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xststdcdp_crf_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xststdcdp_crf_vs_imm(dst, src, imm)) }
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inst_xstsqrtdp_crf_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSTSQRTDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xstsqrtdp_crf_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xstsqrtdp_crf_vs(dst, src)) }
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inst_xvtsqrtsp_crf_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVTSQRTSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvtsqrtsp_crf_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvtsqrtsp_crf_vs(dst, src)) }
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inst_xvtsqrtdp_crf_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVTSQRTDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvtsqrtdp_crf_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvtsqrtdp_crf_vs(dst, src)) }
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inst_xstdivdp_crf_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSTDIVDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xstdivdp_crf_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xstdivdp_crf_vs_vs(dst, src, src2)) }
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inst_xvtdivsp_crf_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVTDIVSP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvtdivsp_crf_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvtdivsp_crf_vs_vs(dst, src, src2)) }
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inst_xvtdivdp_crf_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XVTDIVDP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xvtdivdp_crf_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xvtdivdp_crf_vs_vs(dst, src, src2)) }
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inst_xxland_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXLAND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxland_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxland_vs_vs_vs(dst, src, src2)) }
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inst_xxlandc_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXLANDC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxlandc_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxlandc_vs_vs_vs(dst, src, src2)) }
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inst_xxlor_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXLOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxlor_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxlor_vs_vs_vs(dst, src, src2)) }
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inst_xxlxor_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXLXOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxlxor_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxlxor_vs_vs_vs(dst, src, src2)) }
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inst_xxlnor_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXLNOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxlnor_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxlnor_vs_vs_vs(dst, src, src2)) }
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inst_xxleqv_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXLEQV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxleqv_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxleqv_vs_vs_vs(dst, src, src2)) }
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inst_xxlnand_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXLNAND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxlnand_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxlnand_vs_vs_vs(dst, src, src2)) }
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inst_xxlorc_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXLORC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxlorc_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxlorc_vs_vs_vs(dst, src, src2)) }
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inst_xxsel_vs_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .XXSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_xxsel_vs_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_xxsel_vs_vs_vs_vs(dst, src, src2, src3)) }
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inst_xxspltw_vs_vs_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXSPLTW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xxspltw_vs_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xxspltw_vs_vs_imm(dst, src, imm)) }
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inst_xxspltib_vs_uimm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXSPLTIB, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_xxspltib_vs_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_xxspltib_vs_uimm(dst, imm)) }
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inst_xxsldwi_vs_vs_vs_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXSLDWI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_xxsldwi_vs_vs_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xxsldwi_vs_vs_vs_imm(dst, src, src2, imm)) }
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inst_xxpermdi_vs_vs_vs_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXPERMDI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_xxpermdi_vs_vs_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xxpermdi_vs_vs_vs_imm(dst, src, src2, imm)) }
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inst_xxmrghw_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXMRGHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxmrghw_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxmrghw_vs_vs_vs(dst, src, src2)) }
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inst_xxmrglw_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXMRGLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxmrglw_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxmrglw_vs_vs_vs(dst, src, src2)) }
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inst_xxextractuw_vs_vs_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXEXTRACTUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xxextractuw_vs_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xxextractuw_vs_vs_imm(dst, src, imm)) }
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inst_xxinsertw_vs_vs_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXINSERTW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xxinsertw_vs_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xxinsertw_vs_vs_imm(dst, src, imm)) }
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inst_xxspltiw_vs_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXSPLTIW, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_xxspltiw_vs_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_xxspltiw_vs_simm(dst, imm)) }
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inst_xxspltidp_vs_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXSPLTIDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_xxspltidp_vs_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_xxspltidp_vs_simm(dst, imm)) }
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inst_xxsplti32dx_vs_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXSPLTI32DX, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_xxsplti32dx_vs_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_xxsplti32dx_vs_simm(dst, imm)) }
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inst_xscmpeqqp_crf_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPEQQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpeqqp_crf_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpeqqp_crf_v_v(dst, src, src2)) }
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inst_xscmpgtqp_crf_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPGTQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpgtqp_crf_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpgtqp_crf_v_v(dst, src, src2)) }
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inst_xscmpgeqp_crf_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPGEQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpgeqp_crf_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpgeqp_crf_v_v(dst, src, src2)) }
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inst_xsaddqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSADDQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsaddqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsaddqp_v_v_v(dst, src, src2)) }
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inst_xsaddqpo_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSADDQPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsaddqpo_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsaddqpo_v_v_v(dst, src, src2)) }
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inst_xssubqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSSUBQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xssubqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xssubqp_v_v_v(dst, src, src2)) }
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inst_xssubqpo_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSSUBQPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xssubqpo_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xssubqpo_v_v_v(dst, src, src2)) }
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inst_xsmulqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMULQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmulqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmulqp_v_v_v(dst, src, src2)) }
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inst_xsmulqpo_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMULQPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmulqpo_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmulqpo_v_v_v(dst, src, src2)) }
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inst_xsdivqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSDIVQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsdivqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsdivqp_v_v_v(dst, src, src2)) }
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inst_xsdivqpo_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSDIVQPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsdivqpo_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsdivqpo_v_v_v(dst, src, src2)) }
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inst_xssqrtqp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSSQRTQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xssqrtqp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xssqrtqp_v_v(dst, src)) }
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inst_xssqrtqpo_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSSQRTQPO, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xssqrtqpo_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xssqrtqpo_v_v(dst, src)) }
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inst_xsmaddqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMADDQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaddqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaddqp_v_v_v(dst, src, src2)) }
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inst_xsmaddqpo_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMADDQPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaddqpo_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaddqpo_v_v_v(dst, src, src2)) }
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inst_xsmsubqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMSUBQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmsubqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmsubqp_v_v_v(dst, src, src2)) }
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inst_xsmsubqpo_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMSUBQPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmsubqpo_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmsubqpo_v_v_v(dst, src, src2)) }
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inst_xsnmaddqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMADDQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmaddqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmaddqp_v_v_v(dst, src, src2)) }
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inst_xsnmaddqpo_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMADDQPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmaddqpo_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmaddqpo_v_v_v(dst, src, src2)) }
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inst_xsnmsubqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMSUBQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmsubqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmsubqp_v_v_v(dst, src, src2)) }
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inst_xsnmsubqpo_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSNMSUBQPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsnmsubqpo_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsnmsubqpo_v_v_v(dst, src, src2)) }
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inst_xsabsqp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSABSQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsabsqp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsabsqp_v_v(dst, src)) }
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inst_xsnabsqp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSNABSQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsnabsqp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsnabsqp_v_v(dst, src)) }
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inst_xsnegqp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSNEGQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsnegqp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsnegqp_v_v(dst, src)) }
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inst_xscpsgnqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCPSGNQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscpsgnqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscpsgnqp_v_v_v(dst, src, src2)) }
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inst_xscmpoqp_crf_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPOQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpoqp_crf_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpoqp_crf_v_v(dst, src, src2)) }
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inst_xscmpuqp_crf_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSCMPUQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xscmpuqp_crf_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xscmpuqp_crf_v_v(dst, src, src2)) }
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inst_xststdcqp_crf_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XSTSTDCQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xststdcqp_crf_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xststdcqp_crf_v_imm(dst, src, imm)) }
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inst_xsrqpi_imm_v_v_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .XSRQPI, operand_count = 4, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), op_imm(imm2)}} }
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emit_xsrqpi_imm_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register, imm2: i64) { append(instructions, inst_xsrqpi_imm_v_v_imm(imm, dst, src, imm2)) }
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inst_xsrqpix_imm_v_v_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .XSRQPIX, operand_count = 4, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), op_imm(imm2)}} }
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emit_xsrqpix_imm_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register, imm2: i64) { append(instructions, inst_xsrqpix_imm_v_v_imm(imm, dst, src, imm2)) }
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inst_xsrqpxp_imm_v_v_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .XSRQPXP, operand_count = 4, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), op_imm(imm2)}} }
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emit_xsrqpxp_imm_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register, imm2: i64) { append(instructions, inst_xsrqpxp_imm_v_v_imm(imm, dst, src, imm2)) }
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inst_xsxexpqp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSXEXPQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsxexpqp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsxexpqp_v_v(dst, src)) }
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inst_xsxsigqp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSXSIGQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xsxsigqp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xsxsigqp_v_v(dst, src)) }
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inst_xsiexpqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSIEXPQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsiexpqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsiexpqp_v_v_v(dst, src, src2)) }
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inst_xscvqpdp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVQPDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvqpdp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvqpdp_v_v(dst, src)) }
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inst_xscvqpdpo_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVQPDPO, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvqpdpo_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvqpdpo_v_v(dst, src)) }
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inst_xscvdpqp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVDPQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvdpqp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvdpqp_v_v(dst, src)) }
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inst_xscvqpsdz_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVQPSDZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvqpsdz_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvqpsdz_v_v(dst, src)) }
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inst_xscvqpswz_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVQPSWZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvqpswz_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvqpswz_v_v(dst, src)) }
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inst_xscvqpudz_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVQPUDZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvqpudz_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvqpudz_v_v(dst, src)) }
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inst_xscvqpuwz_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVQPUWZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvqpuwz_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvqpuwz_v_v(dst, src)) }
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inst_xscvsdqp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVSDQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvsdqp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvsdqp_v_v(dst, src)) }
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inst_xscvudqp_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVUDQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvudqp_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvudqp_v_v(dst, src)) }
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inst_dadd_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dadd_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dadd_fr_fr_fr(dst, src, src2)) }
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inst_dadd_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DADD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dadd_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dadd_dot_fr_fr_fr(dst, src, src2)) }
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inst_dsub_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dsub_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dsub_fr_fr_fr(dst, src, src2)) }
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inst_dsub_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DSUB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dsub_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dsub_dot_fr_fr_fr(dst, src, src2)) }
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inst_dmul_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DMUL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dmul_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dmul_fr_fr_fr(dst, src, src2)) }
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inst_dmul_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DMUL_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dmul_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dmul_dot_fr_fr_fr(dst, src, src2)) }
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inst_ddiv_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DDIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ddiv_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ddiv_fr_fr_fr(dst, src, src2)) }
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inst_ddiv_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DDIV_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ddiv_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ddiv_dot_fr_fr_fr(dst, src, src2)) }
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inst_dcmpu_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCMPU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcmpu_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcmpu_crf_fr_fr(dst, src, src2)) }
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inst_dcmpo_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCMPO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcmpo_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcmpo_crf_fr_fr(dst, src, src2)) }
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inst_drsp_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DRSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_drsp_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_drsp_fr_fr(dst, src)) }
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inst_drsp_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DRSP_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_drsp_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_drsp_dot_fr_fr(dst, src)) }
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inst_dctdp_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCTDP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dctdp_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dctdp_fr_fr(dst, src)) }
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inst_dctdp_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCTDP_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dctdp_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dctdp_dot_fr_fr(dst, src)) }
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inst_dxex_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DXEX, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dxex_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dxex_fr_fr(dst, src)) }
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inst_dxex_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DXEX_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dxex_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dxex_dot_fr_fr(dst, src)) }
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inst_diex_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIEX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_diex_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_diex_fr_fr_fr(dst, src, src2)) }
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inst_diex_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIEX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_diex_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_diex_dot_fr_fr_fr(dst, src, src2)) }
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inst_drrnd_fr_fr_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DRRND, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_drrnd_fr_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_drrnd_fr_fr_fr_imm(dst, src, src2, imm)) }
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inst_drrnd_dot_fr_fr_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DRRND_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_drrnd_dot_fr_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_drrnd_dot_fr_fr_fr_imm(dst, src, src2, imm)) }
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inst_drintx_imm_fr_fr_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .DRINTX, operand_count = 4, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), op_imm(imm2)}} }
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emit_drintx_imm_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register, imm2: i64) { append(instructions, inst_drintx_imm_fr_fr_imm(imm, dst, src, imm2)) }
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inst_drintx_dot_imm_fr_fr_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .DRINTX_DOT, operand_count = 4, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), op_imm(imm2)}} }
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emit_drintx_dot_imm_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register, imm2: i64) { append(instructions, inst_drintx_dot_imm_fr_fr_imm(imm, dst, src, imm2)) }
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inst_drintn_imm_fr_fr_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .DRINTN, operand_count = 4, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), op_imm(imm2)}} }
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emit_drintn_imm_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register, imm2: i64) { append(instructions, inst_drintn_imm_fr_fr_imm(imm, dst, src, imm2)) }
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inst_drintn_dot_imm_fr_fr_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .DRINTN_DOT, operand_count = 4, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), op_imm(imm2)}} }
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emit_drintn_dot_imm_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register, imm2: i64) { append(instructions, inst_drintn_dot_imm_fr_fr_imm(imm, dst, src, imm2)) }
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inst_dqua_fr_fr_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DQUA, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_dqua_fr_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_dqua_fr_fr_fr_imm(dst, src, src2, imm)) }
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inst_dqua_dot_fr_fr_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DQUA_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_dqua_dot_fr_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_dqua_dot_fr_fr_fr_imm(dst, src, src2, imm)) }
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inst_dquai_imm_fr_fr_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .DQUAI, operand_count = 4, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), op_imm(imm2)}} }
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emit_dquai_imm_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register, imm2: i64) { append(instructions, inst_dquai_imm_fr_fr_imm(imm, dst, src, imm2)) }
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inst_dquai_dot_imm_fr_fr_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .DQUAI_DOT, operand_count = 4, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), op_imm(imm2)}} }
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emit_dquai_dot_imm_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register, imm2: i64) { append(instructions, inst_dquai_dot_imm_fr_fr_imm(imm, dst, src, imm2)) }
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inst_dscli_fr_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DSCLI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dscli_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dscli_fr_fr_imm(dst, src, imm)) }
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inst_dscli_dot_fr_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DSCLI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dscli_dot_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dscli_dot_fr_fr_imm(dst, src, imm)) }
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inst_dscri_fr_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DSCRI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dscri_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dscri_fr_fr_imm(dst, src, imm)) }
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inst_dscri_dot_fr_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DSCRI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dscri_dot_fr_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dscri_dot_fr_fr_imm(dst, src, imm)) }
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inst_dcffix_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCFFIX, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dcffix_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dcffix_fr_fr(dst, src)) }
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inst_dcffix_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCFFIX_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dcffix_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dcffix_dot_fr_fr(dst, src)) }
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inst_dctfix_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCTFIX, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dctfix_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dctfix_fr_fr(dst, src)) }
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inst_dctfix_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCTFIX_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dctfix_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dctfix_dot_fr_fr(dst, src)) }
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inst_dtstdc_crf_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DTSTDC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dtstdc_crf_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dtstdc_crf_fr_imm(dst, src, imm)) }
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inst_dtstdg_crf_fr_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DTSTDG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dtstdg_crf_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dtstdg_crf_fr_imm(dst, src, imm)) }
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inst_dtstex_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DTSTEX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dtstex_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dtstex_crf_fr_fr(dst, src, src2)) }
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inst_dtstsf_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DTSTSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dtstsf_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dtstsf_crf_fr_fr(dst, src, src2)) }
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inst_denbcd_imm_fr_fr :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DENBCD, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_denbcd_imm_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_denbcd_imm_fr_fr(imm, dst, src)) }
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inst_denbcd_dot_imm_fr_fr :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DENBCD_DOT, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_denbcd_dot_imm_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_denbcd_dot_imm_fr_fr(imm, dst, src)) }
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inst_ddedpd_imm_fr_fr :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DDEDPD, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_ddedpd_imm_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_ddedpd_imm_fr_fr(imm, dst, src)) }
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inst_ddedpd_dot_imm_fr_fr :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DDEDPD_DOT, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_ddedpd_dot_imm_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_ddedpd_dot_imm_fr_fr(imm, dst, src)) }
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inst_daddq_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DADDQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_daddq_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_daddq_fr_fr_fr(dst, src, src2)) }
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inst_daddq_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DADDQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_daddq_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_daddq_dot_fr_fr_fr(dst, src, src2)) }
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inst_dsubq_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DSUBQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dsubq_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dsubq_fr_fr_fr(dst, src, src2)) }
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inst_dsubq_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DSUBQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dsubq_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dsubq_dot_fr_fr_fr(dst, src, src2)) }
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inst_dmulq_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DMULQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dmulq_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dmulq_fr_fr_fr(dst, src, src2)) }
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inst_dmulq_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DMULQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dmulq_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dmulq_dot_fr_fr_fr(dst, src, src2)) }
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inst_ddivq_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DDIVQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ddivq_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ddivq_fr_fr_fr(dst, src, src2)) }
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inst_ddivq_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DDIVQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ddivq_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ddivq_dot_fr_fr_fr(dst, src, src2)) }
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inst_dcmpuq_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCMPUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcmpuq_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcmpuq_crf_fr_fr(dst, src, src2)) }
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inst_dcmpoq_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCMPOQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcmpoq_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcmpoq_crf_fr_fr(dst, src, src2)) }
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inst_dctfixq_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCTFIXQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dctfixq_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dctfixq_fr_fr(dst, src)) }
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inst_dctfixq_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCTFIXQ_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dctfixq_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dctfixq_dot_fr_fr(dst, src)) }
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inst_xxmtacc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .XXMTACC, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_xxmtacc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_xxmtacc_imm(imm)) }
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inst_xxmfacc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .XXMFACC, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_xxmfacc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_xxmfacc_imm(imm)) }
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inst_xxsetaccz_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .XXSETACCZ, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_xxsetaccz_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_xxsetaccz_imm(imm)) }
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inst_xvf16ger2_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF16GER2, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf16ger2_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf16ger2_imm_vs_vs(imm, dst, src)) }
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inst_xvf16ger2pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF16GER2PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf16ger2pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf16ger2pp_imm_vs_vs(imm, dst, src)) }
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inst_xvf16ger2pn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF16GER2PN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf16ger2pn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf16ger2pn_imm_vs_vs(imm, dst, src)) }
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inst_xvf16ger2np_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF16GER2NP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf16ger2np_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf16ger2np_imm_vs_vs(imm, dst, src)) }
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inst_xvf16ger2nn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF16GER2NN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf16ger2nn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf16ger2nn_imm_vs_vs(imm, dst, src)) }
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inst_xvf32ger_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF32GER, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf32ger_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf32ger_imm_vs_vs(imm, dst, src)) }
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inst_xvf32gerpp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF32GERPP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf32gerpp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf32gerpp_imm_vs_vs(imm, dst, src)) }
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inst_xvf32gerpn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF32GERPN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf32gerpn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf32gerpn_imm_vs_vs(imm, dst, src)) }
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inst_xvf32gernp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF32GERNP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf32gernp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf32gernp_imm_vs_vs(imm, dst, src)) }
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inst_xvf32gernn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF32GERNN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf32gernn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf32gernn_imm_vs_vs(imm, dst, src)) }
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inst_xvf64ger_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF64GER, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf64ger_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf64ger_imm_vs_vs(imm, dst, src)) }
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inst_xvf64gerpp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF64GERPP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf64gerpp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf64gerpp_imm_vs_vs(imm, dst, src)) }
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inst_xvf64gerpn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF64GERPN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf64gerpn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf64gerpn_imm_vs_vs(imm, dst, src)) }
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inst_xvf64gernp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF64GERNP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf64gernp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf64gernp_imm_vs_vs(imm, dst, src)) }
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inst_xvf64gernn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVF64GERNN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvf64gernn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvf64gernn_imm_vs_vs(imm, dst, src)) }
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inst_xvbf16ger2_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVBF16GER2, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvbf16ger2_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvbf16ger2_imm_vs_vs(imm, dst, src)) }
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inst_xvbf16ger2pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVBF16GER2PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvbf16ger2pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvbf16ger2pp_imm_vs_vs(imm, dst, src)) }
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inst_xvbf16ger2pn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVBF16GER2PN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvbf16ger2pn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvbf16ger2pn_imm_vs_vs(imm, dst, src)) }
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inst_xvbf16ger2np_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVBF16GER2NP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvbf16ger2np_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvbf16ger2np_imm_vs_vs(imm, dst, src)) }
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inst_xvbf16ger2nn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVBF16GER2NN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvbf16ger2nn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvbf16ger2nn_imm_vs_vs(imm, dst, src)) }
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inst_xvi4ger8_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVI4GER8, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvi4ger8_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvi4ger8_imm_vs_vs(imm, dst, src)) }
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inst_xvi4ger8pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVI4GER8PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvi4ger8pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvi4ger8pp_imm_vs_vs(imm, dst, src)) }
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inst_xvi8ger4_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVI8GER4, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvi8ger4_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvi8ger4_imm_vs_vs(imm, dst, src)) }
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inst_xvi8ger4pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVI8GER4PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvi8ger4pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvi8ger4pp_imm_vs_vs(imm, dst, src)) }
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inst_xvi8ger4spp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVI8GER4SPP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvi8ger4spp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvi8ger4spp_imm_vs_vs(imm, dst, src)) }
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inst_xvi16ger2_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVI16GER2, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvi16ger2_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvi16ger2_imm_vs_vs(imm, dst, src)) }
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inst_xvi16ger2pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVI16GER2PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvi16ger2pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvi16ger2pp_imm_vs_vs(imm, dst, src)) }
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inst_xvi16ger2s_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVI16GER2S, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvi16ger2s_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvi16ger2s_imm_vs_vs(imm, dst, src)) }
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inst_xvi16ger2spp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVI16GER2SPP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_xvi16ger2spp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_xvi16ger2spp_imm_vs_vs(imm, dst, src)) }
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inst_vstribl_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSTRIBL, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vstribl_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vstribl_v_v(dst, src)) }
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inst_vstribr_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSTRIBR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vstribr_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vstribr_v_v(dst, src)) }
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inst_vstribl_dot_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSTRIBL_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vstribl_dot_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vstribl_dot_v_v(dst, src)) }
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inst_vstribr_dot_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSTRIBR_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vstribr_dot_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vstribr_dot_v_v(dst, src)) }
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inst_vstrihl_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSTRIHL, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vstrihl_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vstrihl_v_v(dst, src)) }
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inst_vstrihr_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSTRIHR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vstrihr_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vstrihr_v_v(dst, src)) }
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inst_vstrihl_dot_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSTRIHL_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vstrihl_dot_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vstrihl_dot_v_v(dst, src)) }
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inst_vstrihr_dot_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSTRIHR_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vstrihr_dot_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vstrihr_dot_v_v(dst, src)) }
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inst_vmsumcud_v_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUMCUD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsumcud_v_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsumcud_v_v_v_v(dst, src, src2, src3)) }
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inst_vcfuged_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCFUGED, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcfuged_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcfuged_v_v_v(dst, src, src2)) }
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inst_vpdepd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPDEPD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpdepd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpdepd_v_v_v(dst, src, src2)) }
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inst_vpextd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPEXTD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vpextd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpextd_v_v_v(dst, src, src2)) }
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inst_vgnb_r_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VGNB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vgnb_r_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vgnb_r_v_imm(dst, src, imm)) }
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inst_vsldbi_v_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSLDBI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vsldbi_v_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vsldbi_v_v_v_imm(dst, src, src2, imm)) }
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inst_vsrdbi_v_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRDBI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vsrdbi_v_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vsrdbi_v_v_v_imm(dst, src, src2, imm)) }
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inst_vclzdm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCLZDM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vclzdm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vclzdm_v_v_v(dst, src, src2)) }
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inst_vctzdm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCTZDM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vctzdm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vctzdm_v_v_v(dst, src, src2)) }
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inst_vclrlb_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCLRLB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vclrlb_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vclrlb_v_v_r(dst, src, src2)) }
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inst_vclrrb_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCLRRB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vclrrb_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vclrrb_v_v_r(dst, src, src2)) }
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inst_vexpandbm_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXPANDBM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vexpandbm_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vexpandbm_v_v(dst, src)) }
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inst_vexpandhm_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXPANDHM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vexpandhm_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vexpandhm_v_v(dst, src)) }
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inst_vexpandwm_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXPANDWM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vexpandwm_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vexpandwm_v_v(dst, src)) }
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inst_vexpanddm_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXPANDDM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vexpanddm_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vexpanddm_v_v(dst, src)) }
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inst_vexpandqm_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXPANDQM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vexpandqm_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vexpandqm_v_v(dst, src)) }
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inst_vextractbm_r_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTRACTBM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextractbm_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextractbm_r_v(dst, src)) }
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inst_vextracthm_r_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTRACTHM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextracthm_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextracthm_r_v(dst, src)) }
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inst_vextractwm_r_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTRACTWM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextractwm_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextractwm_r_v(dst, src)) }
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inst_vextractdm_r_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTRACTDM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextractdm_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextractdm_r_v(dst, src)) }
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inst_vextractqm_r_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTRACTQM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextractqm_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextractqm_r_v(dst, src)) }
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inst_vcntmbb_r_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCNTMBB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vcntmbb_r_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcntmbb_r_v_imm(dst, src, imm)) }
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inst_vcntmbh_r_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCNTMBH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vcntmbh_r_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcntmbh_r_v_imm(dst, src, imm)) }
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inst_vcntmbw_r_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCNTMBW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vcntmbw_r_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcntmbw_r_v_imm(dst, src, imm)) }
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inst_vcntmbd_r_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCNTMBD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vcntmbd_r_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcntmbd_r_v_imm(dst, src, imm)) }
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inst_mtvsrbm_vs_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTVSRBM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtvsrbm_vs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtvsrbm_vs_r(dst, src)) }
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inst_mtvsrhm_vs_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTVSRHM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtvsrhm_vs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtvsrhm_vs_r(dst, src)) }
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inst_mtvsrwm_vs_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTVSRWM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtvsrwm_vs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtvsrwm_vs_r(dst, src)) }
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inst_mtvsrdm_vs_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTVSRDM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtvsrdm_vs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtvsrdm_vs_r(dst, src)) }
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inst_mtvsrqm_vs_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTVSRQM, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtvsrqm_vs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtvsrqm_vs_r(dst, src)) }
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inst_copy_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .COPY, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_copy_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_copy_r_r(dst, src)) }
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inst_paste_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PASTE_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_paste_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_paste_dot_r_r(dst, src)) }
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inst_lbzcix_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LBZCIX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lbzcix_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lbzcix_r_r_r(dst, src, src2)) }
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inst_lhzcix_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LHZCIX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lhzcix_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lhzcix_r_r_r(dst, src, src2)) }
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inst_lwzcix_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LWZCIX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lwzcix_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lwzcix_r_r_r(dst, src, src2)) }
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inst_ldcix_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LDCIX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ldcix_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ldcix_r_r_r(dst, src, src2)) }
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inst_stbcix_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STBCIX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stbcix_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stbcix_r_r_r(dst, src, src2)) }
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inst_sthcix_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STHCIX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sthcix_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sthcix_r_r_r(dst, src, src2)) }
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inst_stwcix_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STWCIX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stwcix_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stwcix_r_r_r(dst, src, src2)) }
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inst_stdcix_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STDCIX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stdcix_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stdcix_r_r_r(dst, src, src2)) }
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inst_tbegin_dot_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TBEGIN_DOT, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_tbegin_dot_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tbegin_dot_imm(imm)) }
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inst_tend_dot_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TEND_DOT, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_tend_dot_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tend_dot_none()) }
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inst_tabort_dot_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .TABORT_DOT, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_tabort_dot_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tabort_dot_r(dst)) }
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inst_tabortwc_dot_imm_r_r :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TABORTWC_DOT, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_tabortwc_dot_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_tabortwc_dot_imm_r_r(imm, dst, src)) }
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inst_tabortwci_dot_imm_r_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .TABORTWCI_DOT, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_imm(imm2), {}}} }
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emit_tabortwci_dot_imm_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, imm2: i64) { append(instructions, inst_tabortwci_dot_imm_r_imm(imm, dst, imm2)) }
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inst_tabortdc_dot_imm_r_r :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TABORTDC_DOT, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_tabortdc_dot_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_tabortdc_dot_imm_r_r(imm, dst, src)) }
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inst_tabortdci_dot_imm_r_imm :: #force_inline proc "contextless" (imm: i64, dst: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .TABORTDCI_DOT, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_imm(imm2), {}}} }
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emit_tabortdci_dot_imm_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, imm2: i64) { append(instructions, inst_tabortdci_dot_imm_r_imm(imm, dst, imm2)) }
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inst_treclaim_dot_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .TRECLAIM_DOT, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_treclaim_dot_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_treclaim_dot_r(dst)) }
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inst_trechkpt_dot_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TRECHKPT_DOT, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_trechkpt_dot_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_trechkpt_dot_none()) }
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inst_tsuspend_dot_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TSUSPEND_DOT, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_tsuspend_dot_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsuspend_dot_none()) }
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inst_tresume_dot_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TRESUME_DOT, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_tresume_dot_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tresume_dot_none()) }
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inst_tcheck_crf :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .TCHECK, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_tcheck_crf :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tcheck_crf(dst)) }
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inst_addg6s_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDG6S, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addg6s_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addg6s_r_r_r(dst, src, src2)) }
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inst_cbcdtd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CBCDTD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cbcdtd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cbcdtd_r_r(dst, src)) }
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inst_cdtbcd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CDTBCD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_cdtbcd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cdtbcd_r_r(dst, src)) }
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inst_rfebb_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .RFEBB, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_rfebb_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_rfebb_imm(imm)) }
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inst_rfdi_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .RFDI, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_rfdi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rfdi_none()) }
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inst_msgsync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .MSGSYNC, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_msgsync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_msgsync_none()) }
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inst_isel_r_rz_r_crb :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .ISEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_isel_r_rz_r_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_isel_r_rz_r_crb(dst, src, src2, src3)) }
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inst_dcbtt_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .DCBTT, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_dcbtt_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_dcbtt_mem(addr)) }
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inst_dcbtstt_mem :: #force_inline proc "contextless" (addr: Memory) -> Instruction { return Instruction{mnemonic = .DCBTSTT, operand_count = 1, length = 4, ops = {op_mem(addr), {}, {}, {}}} }
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emit_dcbtstt_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, addr: Memory) { append(instructions, inst_dcbtstt_mem(addr)) }
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inst_vextublx_r_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEXTUBLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vextublx_r_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vextublx_r_r_v(dst, src, src2)) }
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inst_vextuhlx_r_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEXTUHLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vextuhlx_r_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vextuhlx_r_r_v(dst, src, src2)) }
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inst_vextuwlx_r_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEXTUWLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vextuwlx_r_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vextuwlx_r_r_v(dst, src, src2)) }
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inst_vextubrx_r_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEXTUBRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vextubrx_r_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vextubrx_r_r_v(dst, src, src2)) }
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inst_vextuhrx_r_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEXTUHRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vextuhrx_r_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vextuhrx_r_r_v(dst, src, src2)) }
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inst_vextuwrx_r_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEXTUWRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vextuwrx_r_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vextuwrx_r_r_v(dst, src, src2)) }
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inst_vinsbvlx_v_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSBVLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinsbvlx_v_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinsbvlx_v_r_v(dst, src, src2)) }
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inst_vinshvlx_v_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSHVLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinshvlx_v_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinshvlx_v_r_v(dst, src, src2)) }
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inst_vinswvlx_v_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSWVLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinswvlx_v_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinswvlx_v_r_v(dst, src, src2)) }
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inst_vinsbvrx_v_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSBVRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinsbvrx_v_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinsbvrx_v_r_v(dst, src, src2)) }
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inst_vinshvrx_v_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSHVRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinshvrx_v_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinshvrx_v_r_v(dst, src, src2)) }
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inst_vinswvrx_v_r_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSWVRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinswvrx_v_r_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinswvrx_v_r_v(dst, src, src2)) }
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inst_vinsblx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSBLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinsblx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinsblx_v_r_r(dst, src, src2)) }
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inst_vinshlx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSHLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinshlx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinshlx_v_r_r(dst, src, src2)) }
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inst_vinswlx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSWLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinswlx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinswlx_v_r_r(dst, src, src2)) }
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inst_vinsdlx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSDLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinsdlx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinsdlx_v_r_r(dst, src, src2)) }
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inst_vinsbrx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSBRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinsbrx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinsbrx_v_r_r(dst, src, src2)) }
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inst_vinshrx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSHRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinshrx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinshrx_v_r_r(dst, src, src2)) }
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inst_vinswrx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSWRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinswrx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinswrx_v_r_r(dst, src, src2)) }
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inst_vinsdrx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VINSDRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vinsdrx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vinsdrx_v_r_r(dst, src, src2)) }
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inst_vinsw_v_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VINSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vinsw_v_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vinsw_v_r_imm(dst, src, imm)) }
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inst_vinsd_v_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VINSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vinsd_v_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vinsd_v_r_imm(dst, src, imm)) }
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inst_vextdubvlx_v_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VEXTDUBVLX, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vextdubvlx_v_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vextdubvlx_v_v_v_r(dst, src, src2, src3)) }
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inst_vextduhvlx_v_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VEXTDUHVLX, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vextduhvlx_v_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vextduhvlx_v_v_v_r(dst, src, src2, src3)) }
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inst_vextduwvlx_v_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VEXTDUWVLX, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vextduwvlx_v_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vextduwvlx_v_v_v_r(dst, src, src2, src3)) }
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inst_vextddvlx_v_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VEXTDDVLX, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vextddvlx_v_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vextddvlx_v_v_v_r(dst, src, src2, src3)) }
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inst_vextdubvrx_v_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VEXTDUBVRX, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vextdubvrx_v_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vextdubvrx_v_v_v_r(dst, src, src2, src3)) }
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inst_vextduhvrx_v_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VEXTDUHVRX, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vextduhvrx_v_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vextduhvrx_v_v_v_r(dst, src, src2, src3)) }
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inst_vextduwvrx_v_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VEXTDUWVRX, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vextduwvrx_v_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vextduwvrx_v_v_v_r(dst, src, src2, src3)) }
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inst_vextddvrx_v_v_v_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VEXTDDVRX, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vextddvrx_v_v_v_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vextddvrx_v_v_v_r(dst, src, src2, src3)) }
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inst_lxvrbx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVRBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvrbx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvrbx_vs_r_r(dst, src, src2)) }
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inst_lxvrhx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVRHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvrhx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvrhx_vs_r_r(dst, src, src2)) }
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inst_lxvrwx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVRWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvrwx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvrwx_vs_r_r(dst, src, src2)) }
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inst_lxvrdx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVRDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvrdx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvrdx_vs_r_r(dst, src, src2)) }
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inst_stxvrbx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVRBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvrbx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvrbx_vs_r_r(dst, src, src2)) }
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inst_stxvrhx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVRHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvrhx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvrhx_vs_r_r(dst, src, src2)) }
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inst_stxvrwx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVRWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvrwx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvrwx_vs_r_r(dst, src, src2)) }
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inst_stxvrdx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVRDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvrdx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvrdx_vs_r_r(dst, src, src2)) }
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inst_lxvkq_vs_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LXVKQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_lxvkq_vs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_lxvkq_vs_imm(dst, imm)) }
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inst_xsmaxcqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMAXCQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmaxcqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmaxcqp_v_v_v(dst, src, src2)) }
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inst_xsmincqp_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XSMINCQP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xsmincqp_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xsmincqp_v_v_v(dst, src, src2)) }
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inst_vrlq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrlq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrlq_v_v_v(dst, src, src2)) }
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inst_vrlqmi_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLQMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrlqmi_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrlqmi_v_v_v(dst, src, src2)) }
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inst_vrlqnm_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLQNM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrlqnm_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrlqnm_v_v_v(dst, src, src2)) }
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inst_vslq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSLQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vslq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vslq_v_v_v(dst, src, src2)) }
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inst_vsrq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrq_v_v_v(dst, src, src2)) }
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inst_vsraq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRAQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsraq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsraq_v_v_v(dst, src, src2)) }
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inst_vmulesd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULESD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulesd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulesd_v_v_v(dst, src, src2)) }
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inst_vmuleud_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULEUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmuleud_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmuleud_v_v_v(dst, src, src2)) }
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inst_vmulosd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULOSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulosd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulosd_v_v_v(dst, src, src2)) }
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inst_vmuloud_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULOUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmuloud_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmuloud_v_v_v(dst, src, src2)) }
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inst_vmulld_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulld_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulld_v_v_v(dst, src, src2)) }
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inst_vmulhsw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULHSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulhsw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulhsw_v_v_v(dst, src, src2)) }
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inst_vmulhsd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULHSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulhsd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulhsd_v_v_v(dst, src, src2)) }
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inst_vmulhuw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULHUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulhuw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulhuw_v_v_v(dst, src, src2)) }
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inst_vmulhud_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULHUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulhud_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulhud_v_v_v(dst, src, src2)) }
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inst_vdivsw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdivsw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdivsw_v_v_v(dst, src, src2)) }
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inst_vdivuw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdivuw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdivuw_v_v_v(dst, src, src2)) }
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inst_vdivsd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdivsd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdivsd_v_v_v(dst, src, src2)) }
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inst_vdivud_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdivud_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdivud_v_v_v(dst, src, src2)) }
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inst_vdivsq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVSQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdivsq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdivsq_v_v_v(dst, src, src2)) }
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inst_vdivuq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdivuq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdivuq_v_v_v(dst, src, src2)) }
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inst_vdivesw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVESW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdivesw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdivesw_v_v_v(dst, src, src2)) }
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inst_vdiveuw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVEUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdiveuw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdiveuw_v_v_v(dst, src, src2)) }
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inst_vdivesd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVESD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdivesd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdivesd_v_v_v(dst, src, src2)) }
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inst_vdiveud_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVEUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdiveud_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdiveud_v_v_v(dst, src, src2)) }
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inst_vdivesq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVESQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdivesq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdivesq_v_v_v(dst, src, src2)) }
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inst_vdiveuq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIVEUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vdiveuq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdiveuq_v_v_v(dst, src, src2)) }
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inst_vmodsw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMODSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmodsw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmodsw_v_v_v(dst, src, src2)) }
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inst_vmoduw_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMODUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmoduw_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmoduw_v_v_v(dst, src, src2)) }
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inst_vmodsd_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMODSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmodsd_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmodsd_v_v_v(dst, src, src2)) }
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inst_vmodud_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMODUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmodud_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmodud_v_v_v(dst, src, src2)) }
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inst_vmodsq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMODSQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmodsq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmodsq_v_v_v(dst, src, src2)) }
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inst_vmoduq_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMODUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmoduq_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmoduq_v_v_v(dst, src, src2)) }
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inst_setb_r_crf :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SETB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_setb_r_crf :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_setb_r_crf(dst, src)) }
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inst_mcrxrx_crf :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MCRXRX, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mcrxrx_crf :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mcrxrx_crf(dst)) }
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inst_xvcvbf16spn_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVBF16SPN, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvbf16spn_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvbf16spn_vs_vs(dst, src)) }
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inst_xvcvspbf16_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSPBF16, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvspbf16_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvspbf16_vs_vs(dst, src)) }
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inst_xxgenpcvbm_vs_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXGENPCVBM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xxgenpcvbm_vs_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xxgenpcvbm_vs_v_imm(dst, src, imm)) }
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inst_xxgenpcvhm_vs_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXGENPCVHM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xxgenpcvhm_vs_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xxgenpcvhm_vs_v_imm(dst, src, imm)) }
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inst_xxgenpcvwm_vs_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXGENPCVWM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xxgenpcvwm_vs_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xxgenpcvwm_vs_v_imm(dst, src, imm)) }
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inst_xxgenpcvdm_vs_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XXGENPCVDM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xxgenpcvdm_vs_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xxgenpcvdm_vs_v_imm(dst, src, imm)) }
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inst_xxblendvb_vs_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .XXBLENDVB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_xxblendvb_vs_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_xxblendvb_vs_vs_vs_vs(dst, src, src2, src3)) }
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inst_xxblendvh_vs_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .XXBLENDVH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_xxblendvh_vs_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_xxblendvh_vs_vs_vs_vs(dst, src, src2, src3)) }
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inst_xxblendvw_vs_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .XXBLENDVW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_xxblendvw_vs_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_xxblendvw_vs_vs_vs_vs(dst, src, src2, src3)) }
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inst_xxblendvd_vs_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .XXBLENDVD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_xxblendvd_vs_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_xxblendvd_vs_vs_vs_vs(dst, src, src2, src3)) }
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inst_xxpermx_vs_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .XXPERMX, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_xxpermx_vs_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_xxpermx_vs_vs_vs_vs(dst, src, src2, src3)) }
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inst_xxeval_vs_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .XXEVAL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_xxeval_vs_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_xxeval_vs_vs_vs_vs(dst, src, src2, src3)) }
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inst_xxperm_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXPERM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxperm_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxperm_vs_vs_vs(dst, src, src2)) }
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inst_pld_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_pld_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_pld_r_mem(dst, addr)) }
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inst_pstd_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSTD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_pstd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_pstd_r_mem(dst, addr)) }
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inst_plwz_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLWZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plwz_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plwz_r_mem(dst, addr)) }
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inst_pstw_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSTW, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_pstw_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_pstw_r_mem(dst, addr)) }
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inst_plbz_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plbz_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plbz_r_mem(dst, addr)) }
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inst_pstb_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSTB, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_pstb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_pstb_r_mem(dst, addr)) }
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inst_plhz_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLHZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plhz_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plhz_r_mem(dst, addr)) }
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inst_psth_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSTH, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_psth_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_psth_r_mem(dst, addr)) }
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inst_plha_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLHA, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plha_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plha_r_mem(dst, addr)) }
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inst_plwa_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLWA, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plwa_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plwa_r_mem(dst, addr)) }
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inst_plfd_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLFD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plfd_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plfd_fr_mem(dst, addr)) }
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inst_pstfd_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSTFD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_pstfd_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_pstfd_fr_mem(dst, addr)) }
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inst_plfs_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLFS, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plfs_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plfs_fr_mem(dst, addr)) }
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inst_pstfs_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSTFS, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_pstfs_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_pstfs_fr_mem(dst, addr)) }
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inst_plxv_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plxv_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plxv_vs_mem(dst, addr)) }
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inst_pstxv_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSTXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_pstxv_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_pstxv_vs_mem(dst, addr)) }
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inst_plxsd_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLXSD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plxsd_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plxsd_v_mem(dst, addr)) }
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inst_pstxsd_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSTXSD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_pstxsd_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_pstxsd_v_mem(dst, addr)) }
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inst_plxssp_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PLXSSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_plxssp_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_plxssp_v_mem(dst, addr)) }
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inst_pstxssp_v_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSTXSSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_pstxssp_v_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_pstxssp_v_mem(dst, addr)) }
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inst_paddi_r_rz_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .PADDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_paddi_r_rz_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_paddi_r_rz_simm(dst, src, imm)) }
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inst_pli_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .PLI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_pli_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_pli_r_simm(dst, imm)) }
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inst_psubi_r_r_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .PSUBI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_psubi_r_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_psubi_r_r_simm(dst, src, imm)) }
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inst_pmxvf32ger_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF32GER, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf32ger_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf32ger_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf64ger_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF64GER, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf64ger_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf64ger_imm_vs_vs(imm, dst, src)) }
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inst_pmxvi4ger8_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVI4GER8, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvi4ger8_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvi4ger8_imm_vs_vs(imm, dst, src)) }
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inst_pmxvi8ger4_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVI8GER4, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvi8ger4_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvi8ger4_imm_vs_vs(imm, dst, src)) }
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inst_pmxvi16ger2_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVI16GER2, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvi16ger2_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvi16ger2_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf16ger2_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF16GER2, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf16ger2_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf16ger2_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf16ger2pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF16GER2PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf16ger2pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf16ger2pp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf16ger2pn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF16GER2PN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf16ger2pn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf16ger2pn_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf16ger2np_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF16GER2NP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf16ger2np_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf16ger2np_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf16ger2nn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF16GER2NN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf16ger2nn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf16ger2nn_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf32gerpp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF32GERPP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf32gerpp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf32gerpp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf32gerpn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF32GERPN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf32gerpn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf32gerpn_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf32gernp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF32GERNP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf32gernp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf32gernp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf32gernn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF32GERNN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf32gernn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf32gernn_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf64gerpp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF64GERPP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf64gerpp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf64gerpp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf64gerpn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF64GERPN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf64gerpn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf64gerpn_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf64gernp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF64GERNP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf64gernp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf64gernp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvf64gernn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVF64GERNN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvf64gernn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvf64gernn_imm_vs_vs(imm, dst, src)) }
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inst_pmxvbf16ger2_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVBF16GER2, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvbf16ger2_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvbf16ger2_imm_vs_vs(imm, dst, src)) }
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inst_pmxvbf16ger2pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVBF16GER2PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvbf16ger2pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvbf16ger2pp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvbf16ger2pn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVBF16GER2PN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvbf16ger2pn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvbf16ger2pn_imm_vs_vs(imm, dst, src)) }
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inst_pmxvbf16ger2np_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVBF16GER2NP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvbf16ger2np_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvbf16ger2np_imm_vs_vs(imm, dst, src)) }
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inst_pmxvbf16ger2nn_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVBF16GER2NN, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvbf16ger2nn_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvbf16ger2nn_imm_vs_vs(imm, dst, src)) }
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inst_pmxvi4ger8pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVI4GER8PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvi4ger8pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvi4ger8pp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvi8ger4pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVI8GER4PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvi8ger4pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvi8ger4pp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvi8ger4spp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVI8GER4SPP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvi8ger4spp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvi8ger4spp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvi16ger2pp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVI16GER2PP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvi16ger2pp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvi16ger2pp_imm_vs_vs(imm, dst, src)) }
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inst_pmxvi16ger2s_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVI16GER2S, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvi16ger2s_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvi16ger2s_imm_vs_vs(imm, dst, src)) }
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inst_pmxvi16ger2spp_imm_vs_vs :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PMXVI16GER2SPP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_pmxvi16ger2spp_imm_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_pmxvi16ger2spp_imm_vs_vs(imm, dst, src)) }
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inst_lxvp_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LXVP, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lxvp_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lxvp_vs_mem(dst, addr)) }
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inst_stxvp_vs_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STXVP, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stxvp_vs_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stxvp_vs_mem(dst, addr)) }
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inst_lxvpx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvpx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvpx_vs_r_r(dst, src, src2)) }
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inst_stxvpx_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvpx_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvpx_vs_r_r(dst, src, src2)) }
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inst_dcbi_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCBI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dcbi_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dcbi_r_r(dst, src)) }
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inst_icbiep_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ICBIEP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_icbiep_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_icbiep_r_r(dst, src)) }
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inst_dcbtep_imm_r_r :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCBTEP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_dcbtep_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_dcbtep_imm_r_r(imm, dst, src)) }
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inst_dcbtstep_imm_r_r :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCBTSTEP, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_dcbtstep_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_dcbtstep_imm_r_r(imm, dst, src)) }
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inst_lbepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LBEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lbepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lbepx_r_r_r(dst, src, src2)) }
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inst_lhepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LHEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lhepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lhepx_r_r_r(dst, src, src2)) }
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inst_lwepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LWEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lwepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lwepx_r_r_r(dst, src, src2)) }
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inst_stbepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STBEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stbepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stbepx_r_r_r(dst, src, src2)) }
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inst_sthepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STHEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sthepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sthepx_r_r_r(dst, src, src2)) }
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inst_stwepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STWEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stwepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stwepx_r_r_r(dst, src, src2)) }
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inst_lfdepx_fr_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LFDEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lfdepx_fr_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lfdepx_fr_r_r(dst, src, src2)) }
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inst_stfdepx_fr_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STFDEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stfdepx_fr_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stfdepx_fr_r_r(dst, src, src2)) }
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inst_tlbsx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TLBSX, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tlbsx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tlbsx_r_r(dst, src)) }
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inst_dccci_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCCCI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dccci_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dccci_r_r(dst, src)) }
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inst_iccci_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ICCCI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_iccci_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_iccci_r_r(dst, src)) }
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inst_wrtee_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .WRTEE, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_wrtee_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wrtee_r(dst)) }
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inst_wrteei_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .WRTEEI, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_wrteei_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_wrteei_imm(imm)) }
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inst_tlbre_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TLBRE, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_tlbre_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbre_none()) }
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inst_tlbwe_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TLBWE, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_tlbwe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbwe_none()) }
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inst_tlbivax_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TLBIVAX, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tlbivax_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tlbivax_r_r(dst, src)) }
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inst_tlbilx_imm_r_r :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TLBILX, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_tlbilx_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_tlbilx_imm_r_r(imm, dst, src)) }
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inst_tlbld_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .TLBLD, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_tlbld_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbld_r(dst)) }
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inst_tlbli_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .TLBLI, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_tlbli_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbli_r(dst)) }
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inst_mfpmr_r_spr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFPMR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mfpmr_r_spr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mfpmr_r_spr(dst, src)) }
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inst_mtpmr_spr_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTPMR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtpmr_spr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtpmr_spr_r(dst, src)) }
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inst_mfsr_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MFSR, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_mfsr_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mfsr_r_imm(dst, imm)) }
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inst_mtsr_imm_r :: #force_inline proc "contextless" (imm: i64, dst: Register) -> Instruction { return Instruction{mnemonic = .MTSR, operand_count = 2, length = 4, ops = {op_imm(imm), op_reg(dst), {}, {}}} }
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emit_mtsr_imm_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register) { append(instructions, inst_mtsr_imm_r(imm, dst)) }
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inst_mfsrin_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFSRIN, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mfsrin_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mfsrin_r_r(dst, src)) }
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inst_mtsrin_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTSRIN, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtsrin_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtsrin_r_r(dst, src)) }
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inst_dst_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DST, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dst_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dst_r_r_imm(dst, src, imm)) }
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inst_dstt_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DSTT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dstt_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dstt_r_r_imm(dst, src, imm)) }
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inst_dstst_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DSTST, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dstst_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dstst_r_r_imm(dst, src, imm)) }
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inst_dststt_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DSTSTT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dststt_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dststt_r_r_imm(dst, src, imm)) }
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inst_dss_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSS, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_dss_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dss_imm(imm)) }
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inst_dssall_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DSSALL, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_dssall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dssall_none()) }
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inst_vsumsws_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUMSWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsumsws_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsumsws_v_v_v(dst, src, src2)) }
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inst_vsum2sws_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUM2SWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsum2sws_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsum2sws_v_v_v(dst, src, src2)) }
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inst_vsum4sbs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUM4SBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsum4sbs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsum4sbs_v_v_v(dst, src, src2)) }
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inst_vsum4shs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUM4SHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsum4shs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsum4shs_v_v_v(dst, src, src2)) }
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inst_vsum4ubs_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUM4UBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsum4ubs_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsum4ubs_v_v_v(dst, src, src2)) }
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inst_mffsce_fr :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFFSCE, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mffsce_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mffsce_fr(dst)) }
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inst_mffscdrn_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFFSCDRN, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mffscdrn_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mffscdrn_fr_fr(dst, src)) }
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inst_mffscdrni_fr_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MFFSCDRNI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_mffscdrni_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mffscdrni_fr_imm(dst, imm)) }
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inst_mffscrn_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFFSCRN, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mffscrn_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mffscrn_fr_fr(dst, src)) }
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inst_mffscrni_fr_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MFFSCRNI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_mffscrni_fr_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mffscrni_fr_imm(dst, imm)) }
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inst_mffsl_fr :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFFSL, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mffsl_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mffsl_fr(dst)) }
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inst_stop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .STOP, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_stop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_stop_none()) }
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inst_cpabort_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CPABORT, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_cpabort_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cpabort_none()) }
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inst_attn_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ATTN, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_attn_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_attn_none()) }
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inst_mtfprd_fr_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTFPRD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtfprd_fr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtfprd_fr_r(dst, src)) }
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inst_mffprd_r_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFFPRD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mffprd_r_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mffprd_r_fr(dst, src)) }
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inst_mtfprwa_fr_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTFPRWA, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtfprwa_fr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtfprwa_fr_r(dst, src)) }
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inst_mtfprwz_fr_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTFPRWZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtfprwz_fr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtfprwz_fr_r(dst, src)) }
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inst_mffprwz_r_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFFPRWZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mffprwz_r_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mffprwz_r_fr(dst, src)) }
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inst_mfvsrld_r_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFVSRLD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mfvsrld_r_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mfvsrld_r_vs(dst, src)) }
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inst_mtvsrdd_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTVSRDD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtvsrdd_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtvsrdd_vs_r_r(dst, src, src2)) }
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inst_mtvsrws_vs_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTVSRWS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtvsrws_vs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtvsrws_vs_r(dst, src)) }
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inst_extswsli_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTSWSLI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_extswsli_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_extswsli_r_r_imm(dst, src, imm)) }
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inst_extswsli_dot_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTSWSLI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_extswsli_dot_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_extswsli_dot_r_r_imm(dst, src, imm)) }
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inst_isellt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ISELLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_isellt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_isellt_r_r_r(dst, src, src2)) }
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inst_iselgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ISELGT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_iselgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_iselgt_r_r_r(dst, src, src2)) }
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inst_iseleq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ISELEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_iseleq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_iseleq_r_r_r(dst, src, src2)) }
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inst_tweq_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TWEQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tweq_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tweq_r_r(dst, src)) }
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inst_twne_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TWNE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_twne_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_twne_r_r(dst, src)) }
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inst_twgt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TWGT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_twgt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_twgt_r_r(dst, src)) }
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inst_twlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TWLT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_twlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_twlt_r_r(dst, src)) }
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inst_twgti_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TWGTI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_twgti_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_twgti_r_simm(dst, imm)) }
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inst_twlti_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TWLTI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_twlti_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_twlti_r_simm(dst, imm)) }
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inst_tweqi_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TWEQI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_tweqi_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tweqi_r_simm(dst, imm)) }
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inst_twnei_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TWNEI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_twnei_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_twnei_r_simm(dst, imm)) }
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inst_twui_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TWUI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_twui_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_twui_r_simm(dst, imm)) }
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inst_tdeq_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TDEQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tdeq_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tdeq_r_r(dst, src)) }
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inst_tdne_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TDNE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tdne_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tdne_r_r(dst, src)) }
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inst_tdgt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TDGT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tdgt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tdgt_r_r(dst, src)) }
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inst_tdlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TDLT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tdlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tdlt_r_r(dst, src)) }
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inst_tdgti_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TDGTI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_tdgti_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tdgti_r_simm(dst, imm)) }
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inst_tdlti_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TDLTI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_tdlti_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tdlti_r_simm(dst, imm)) }
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inst_tdeqi_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TDEQI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_tdeqi_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tdeqi_r_simm(dst, imm)) }
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inst_tdnei_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TDNEI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_tdnei_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tdnei_r_simm(dst, imm)) }
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inst_tdui_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TDUI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_tdui_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tdui_r_simm(dst, imm)) }
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inst_bcdadd_dot_v_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BCDADD_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_bcdadd_dot_v_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_bcdadd_dot_v_v_v_imm(dst, src, src2, imm)) }
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inst_bcdsub_dot_v_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BCDSUB_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_bcdsub_dot_v_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_bcdsub_dot_v_v_v_imm(dst, src, src2, imm)) }
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inst_bcds_dot_v_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BCDS_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_bcds_dot_v_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_bcds_dot_v_v_v_imm(dst, src, src2, imm)) }
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inst_bcdus_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BCDUS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_bcdus_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bcdus_dot_v_v_v(dst, src, src2)) }
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inst_bcdsr_dot_v_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BCDSR_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_bcdsr_dot_v_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_bcdsr_dot_v_v_v_imm(dst, src, src2, imm)) }
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inst_bcdcfn_dot_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BCDCFN_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_bcdcfn_dot_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bcdcfn_dot_v_v_imm(dst, src, imm)) }
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inst_bcdctn_dot_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BCDCTN_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_bcdctn_dot_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bcdctn_dot_v_v(dst, src)) }
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inst_bcdcfz_dot_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BCDCFZ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_bcdcfz_dot_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bcdcfz_dot_v_v_imm(dst, src, imm)) }
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inst_bcdctz_dot_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BCDCTZ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_bcdctz_dot_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bcdctz_dot_v_v_imm(dst, src, imm)) }
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inst_bcdcpsgn_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BCDCPSGN_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_bcdcpsgn_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bcdcpsgn_dot_v_v_v(dst, src, src2)) }
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inst_bcdtrunc_dot_v_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BCDTRUNC_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_bcdtrunc_dot_v_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_bcdtrunc_dot_v_v_v_imm(dst, src, src2, imm)) }
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inst_bcdutrunc_dot_v_v_v :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BCDUTRUNC_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_bcdutrunc_dot_v_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bcdutrunc_dot_v_v_v(dst, src, src2)) }
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inst_bcdcfsq_dot_v_v_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BCDCFSQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_bcdcfsq_dot_v_v_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bcdcfsq_dot_v_v_imm(dst, src, imm)) }
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inst_bcdctsq_dot_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BCDCTSQ_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_bcdctsq_dot_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bcdctsq_dot_v_v(dst, src)) }
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inst_scv_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SCV, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_scv_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_scv_imm(imm)) }
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inst_bdnztl_crb_rel :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BDNZTL, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label), {}, {}}} }
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emit_bdnztl_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_bdnztl_crb_rel(dst, label)) }
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inst_bdztl_crb_rel :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BDZTL, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label), {}, {}}} }
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emit_bdztl_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_bdztl_crb_rel(dst, label)) }
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inst_bdnzfl_crb_rel :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BDNZFL, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label), {}, {}}} }
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emit_bdnzfl_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_bdnzfl_crb_rel(dst, label)) }
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inst_bdzfl_crb_rel :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BDZFL, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label), {}, {}}} }
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emit_bdzfl_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_bdzfl_crb_rel(dst, label)) }
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inst_bdnztlr_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BDNZTLR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bdnztlr_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bdnztlr_crb(dst)) }
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inst_bdztlr_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BDZTLR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bdztlr_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bdztlr_crb(dst)) }
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inst_bdnzflr_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BDNZFLR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bdnzflr_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bdnzflr_crb(dst)) }
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inst_bdzflr_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BDZFLR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bdzflr_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bdzflr_crb(dst)) }
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inst_bdnztlrl_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BDNZTLRL, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bdnztlrl_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bdnztlrl_crb(dst)) }
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inst_bdztlrl_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BDZTLRL, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bdztlrl_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bdztlrl_crb(dst)) }
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inst_bdnzflrl_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BDNZFLRL, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bdnzflrl_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bdnzflrl_crb(dst)) }
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inst_bdzflrl_crb :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BDZFLRL, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_bdzflrl_crb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bdzflrl_crb(dst)) }
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inst_mtcr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtcr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtcr_r(dst)) }
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inst_mfdscr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFDSCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfdscr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfdscr_r(dst)) }
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inst_mtdscr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTDSCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtdscr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtdscr_r(dst)) }
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inst_mfcfar_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFCFAR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfcfar_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfcfar_r(dst)) }
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inst_mtcfar_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTCFAR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtcfar_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtcfar_r(dst)) }
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inst_mfppr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFPPR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfppr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfppr_r(dst)) }
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inst_mtppr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTPPR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtppr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtppr_r(dst)) }
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inst_mfdec_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFDEC, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfdec_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfdec_r(dst)) }
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inst_mtdec_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTDEC, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtdec_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtdec_r(dst)) }
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inst_mfsrr0_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFSRR0, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfsrr0_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfsrr0_r(dst)) }
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inst_mtsrr0_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTSRR0, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtsrr0_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtsrr0_r(dst)) }
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inst_mfsrr1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFSRR1, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfsrr1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfsrr1_r(dst)) }
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inst_mtsrr1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTSRR1, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtsrr1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtsrr1_r(dst)) }
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inst_mfdar_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFDAR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfdar_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfdar_r(dst)) }
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inst_mtdar_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTDAR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtdar_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtdar_r(dst)) }
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inst_mfdsisr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFDSISR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfdsisr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfdsisr_r(dst)) }
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inst_mtdsisr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTDSISR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtdsisr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtdsisr_r(dst)) }
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inst_mfasr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFASR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfasr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfasr_r(dst)) }
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inst_mtasr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTASR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtasr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtasr_r(dst)) }
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inst_mfamr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFAMR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfamr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfamr_r(dst)) }
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inst_mtamr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTAMR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtamr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtamr_r(dst)) }
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inst_mftcr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFTCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mftcr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mftcr_r(dst)) }
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inst_mttcr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTTCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mttcr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mttcr_r(dst)) }
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inst_mfesr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFESR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfesr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfesr_r(dst)) }
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inst_mtesr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTESR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtesr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtesr_r(dst)) }
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inst_mfdccr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFDCCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfdccr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfdccr_r(dst)) }
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inst_mtdccr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTDCCR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtdccr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtdccr_r(dst)) }
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inst_mtbr0_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTBR0, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtbr0_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtbr0_r(dst)) }
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inst_mtbr1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTBR1, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtbr1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtbr1_r(dst)) }
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inst_mttbl_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTTBL, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mttbl_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mttbl_r(dst)) }
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inst_mttbu_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTTBU, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mttbu_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mttbu_r(dst)) }
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inst_lwat_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LWAT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_lwat_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lwat_r_r_imm(dst, src, imm)) }
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inst_ldat_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LDAT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_ldat_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ldat_r_r_imm(dst, src, imm)) }
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inst_stwat_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .STWAT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_stwat_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_stwat_r_r_imm(dst, src, imm)) }
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inst_stdat_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .STDAT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_stdat_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_stdat_r_r_imm(dst, src, imm)) }
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inst_vextsd2q_v_v :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXTSD2Q, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vextsd2q_v_v :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vextsd2q_v_v(dst, src)) }
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inst_lxvprl_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVPRL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvprl_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvprl_vs_r_r(dst, src, src2)) }
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inst_lxvprll_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVPRLL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvprll_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvprll_vs_r_r(dst, src, src2)) }
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inst_stxvprl_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVPRL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvprl_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvprl_vs_r_r(dst, src, src2)) }
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inst_stxvprll_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVPRLL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvprll_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvprll_vs_r_r(dst, src, src2)) }
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inst_lxvrl_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVRL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvrl_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvrl_vs_r_r(dst, src, src2)) }
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inst_lxvrll_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVRLL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvrll_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvrll_vs_r_r(dst, src, src2)) }
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inst_stxvrl_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVRL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvrl_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvrl_vs_r_r(dst, src, src2)) }
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inst_stxvrll_vs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STXVRLL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stxvrll_vs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stxvrll_vs_r_r(dst, src, src2)) }
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inst_rfmci_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .RFMCI, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_rfmci_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rfmci_none()) }
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inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .NOP, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) }
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inst_xnop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .XNOP, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_xnop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xnop_none()) }
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inst_li_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_li_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_li_r_simm(dst, imm)) }
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inst_lis_r_simm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LIS, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_lis_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_lis_r_simm(dst, imm)) }
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inst_la_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LA, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_la_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_la_r_mem(dst, addr)) }
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inst_mr_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mr_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mr_r_r(dst, src)) }
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inst_mr_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MR_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mr_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mr_dot_r_r(dst, src)) }
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inst_not_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_not_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_r_r(dst, src)) }
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inst_not_dot_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_not_dot_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_dot_r_r(dst, src)) }
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inst_blr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BLR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_blr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_blr_none()) }
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inst_blrl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BLRL, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_blrl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_blrl_none()) }
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inst_bctr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BCTR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bctr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bctr_none()) }
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inst_bctrl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BCTRL, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bctrl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bctrl_none()) }
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inst_beq_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BEQ, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_beq_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_beq_rel(label)) }
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inst_bne_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BNE, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bne_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bne_rel(label)) }
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inst_blt_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BLT, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_blt_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_blt_rel(label)) }
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inst_ble_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BLE, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_ble_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_ble_rel(label)) }
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inst_bgt_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BGT, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bgt_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bgt_rel(label)) }
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inst_bge_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BGE, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bge_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bge_rel(label)) }
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inst_bso_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BSO, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bso_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bso_rel(label)) }
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inst_bns_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BNS, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bns_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bns_rel(label)) }
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inst_beql_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BEQL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_beql_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_beql_rel(label)) }
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inst_bnel_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BNEL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bnel_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bnel_rel(label)) }
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inst_bltl_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BLTL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bltl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bltl_rel(label)) }
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inst_blel_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BLEL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_blel_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_blel_rel(label)) }
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inst_bgtl_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BGTL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bgtl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bgtl_rel(label)) }
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inst_bgel_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BGEL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bgel_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bgel_rel(label)) }
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inst_bsol_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BSOL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bsol_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bsol_rel(label)) }
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inst_bnsl_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BNSL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bnsl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bnsl_rel(label)) }
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inst_beqlr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BEQLR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_beqlr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_beqlr_none()) }
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inst_bnelr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BNELR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bnelr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bnelr_none()) }
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inst_bltlr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BLTLR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bltlr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bltlr_none()) }
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inst_blelr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BLELR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_blelr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_blelr_none()) }
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inst_bgtlr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BGTLR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bgtlr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bgtlr_none()) }
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inst_bgelr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BGELR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bgelr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bgelr_none()) }
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inst_bsolr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BSOLR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bsolr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bsolr_none()) }
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inst_bnslr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BNSLR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bnslr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bnslr_none()) }
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inst_beqctr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BEQCTR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_beqctr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_beqctr_none()) }
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inst_bnectr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BNECTR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bnectr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bnectr_none()) }
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inst_bltctr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BLTCTR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bltctr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bltctr_none()) }
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inst_blectr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BLECTR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_blectr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_blectr_none()) }
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inst_bgtctr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BGTCTR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bgtctr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bgtctr_none()) }
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inst_bgectr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BGECTR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bgectr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bgectr_none()) }
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inst_bsoctr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BSOCTR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bsoctr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bsoctr_none()) }
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inst_bnsctr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BNSCTR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bnsctr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bnsctr_none()) }
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inst_bdz_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BDZ, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bdz_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bdz_rel(label)) }
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inst_bdnz_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BDNZ, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bdnz_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bdnz_rel(label)) }
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inst_bdzl_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BDZL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bdzl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bdzl_rel(label)) }
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inst_bdnzl_rel :: #force_inline proc "contextless" (label: u32) -> Instruction { return Instruction{mnemonic = .BDNZL, operand_count = 1, length = 4, ops = {op_label(label), {}, {}, {}}} }
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emit_bdnzl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bdnzl_rel(label)) }
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inst_bdzlr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BDZLR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bdzlr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bdzlr_none()) }
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inst_bdnzlr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BDNZLR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bdnzlr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bdnzlr_none()) }
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inst_bdzlrl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BDZLRL, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bdzlrl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bdzlrl_none()) }
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inst_bdnzlrl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BDNZLRL, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_bdnzlrl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bdnzlrl_none()) }
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inst_bdzf_crb_rel :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BDZF, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label), {}, {}}} }
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emit_bdzf_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_bdzf_crb_rel(dst, label)) }
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inst_bdzt_crb_rel :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BDZT, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label), {}, {}}} }
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emit_bdzt_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_bdzt_crb_rel(dst, label)) }
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inst_bdnzf_crb_rel :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BDNZF, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label), {}, {}}} }
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emit_bdnzf_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_bdnzf_crb_rel(dst, label)) }
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inst_bdnzt_crb_rel :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .BDNZT, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label), {}, {}}} }
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emit_bdnzt_crb_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_bdnzt_crb_rel(dst, label)) }
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inst_trap_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TRAP, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} }
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emit_trap_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_trap_none()) }
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inst_mflr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFLR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mflr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mflr_r(dst)) }
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inst_mtlr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTLR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtlr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtlr_r(dst)) }
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inst_mfctr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFCTR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfctr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfctr_r(dst)) }
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inst_mtctr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTCTR, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtctr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtctr_r(dst)) }
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inst_mfxer_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MFXER, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mfxer_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mfxer_r(dst)) }
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inst_mtxer_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .MTXER, operand_count = 1, length = 4, ops = {op_reg(dst), {}, {}, {}}} }
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emit_mtxer_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_mtxer_r(dst)) }
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inst_slwi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_slwi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_slwi_r_r_imm(dst, src, imm)) }
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inst_srwi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_srwi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srwi_r_r_imm(dst, src, imm)) }
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inst_sldi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_sldi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sldi_r_r_imm(dst, src, imm)) }
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inst_srdi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_srdi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srdi_r_r_imm(dst, src, imm)) }
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inst_clrrwi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CLRRWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_clrrwi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_clrrwi_r_r_imm(dst, src, imm)) }
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inst_clrlwi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CLRLWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_clrlwi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_clrlwi_r_r_imm(dst, src, imm)) }
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inst_clrrdi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CLRRDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_clrrdi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_clrrdi_r_r_imm(dst, src, imm)) }
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inst_clrldi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CLRLDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_clrldi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_clrldi_r_r_imm(dst, src, imm)) }
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inst_extldi_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .EXTLDI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_extldi_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_extldi_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_extrdi_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .EXTRDI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_extrdi_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_extrdi_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_extlwi_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .EXTLWI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_extlwi_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_extlwi_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_extrwi_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .EXTRWI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_extrwi_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_extrwi_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_inslwi_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INSLWI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_inslwi_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_inslwi_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_insrwi_r_r_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INSRWI, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_insrwi_r_r_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_insrwi_r_r_imm_imm(dst, src, imm, imm2)) }
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inst_rotlw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROTLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rotlw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rotlw_r_r_r(dst, src, src2)) }
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inst_rotlwi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ROTLWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_rotlwi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rotlwi_r_r_imm(dst, src, imm)) }
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inst_rotrw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROTRW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rotrw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rotrw_r_r_r(dst, src, src2)) }
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inst_rotld_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROTLD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rotld_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rotld_r_r_r(dst, src, src2)) }
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inst_rotldi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ROTLDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_rotldi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rotldi_r_r_imm(dst, src, imm)) }
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inst_rotrdi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ROTRDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_rotrdi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rotrdi_r_r_imm(dst, src, imm)) }
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inst_sub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_r_r_r(dst, src, src2)) }
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inst_sub_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sub_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_dot_r_r_r(dst, src, src2)) }
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inst_sub_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sub_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_o_r_r_r(dst, src, src2)) }
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inst_sub_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sub_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_o_dot_r_r_r(dst, src, src2)) }
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inst_subc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subc_r_r_r(dst, src, src2)) }
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inst_subc_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBC_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subc_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subc_dot_r_r_r(dst, src, src2)) }
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inst_subc_o_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBC_O, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subc_o_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subc_o_r_r_r(dst, src, src2)) }
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inst_subc_o_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBC_O_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subc_o_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subc_o_dot_r_r_r(dst, src, src2)) }
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inst_cmpw_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMPW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cmpw_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmpw_crf_r_r(dst, src, src2)) }
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inst_cmplw_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMPLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cmplw_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmplw_crf_r_r(dst, src, src2)) }
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inst_cmpd_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMPD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cmpd_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmpd_crf_r_r(dst, src, src2)) }
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inst_cmpld_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMPLD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cmpld_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmpld_crf_r_r(dst, src, src2)) }
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inst_cmpwi_crf_r_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMPWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_cmpwi_crf_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_cmpwi_crf_r_simm(dst, src, imm)) }
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inst_cmplwi_crf_r_uimm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMPLWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_cmplwi_crf_r_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_cmplwi_crf_r_uimm(dst, src, imm)) }
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inst_cmpdi_crf_r_simm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMPDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_cmpdi_crf_r_simm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_cmpdi_crf_r_simm(dst, src, imm)) }
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inst_cmpldi_crf_r_uimm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMPLDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_cmpldi_crf_r_uimm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_cmpldi_crf_r_uimm(dst, src, imm)) }
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inst_evaddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddw_r_r_r(dst, src, src2)) }
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inst_evaddiw_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EVADDIW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_evaddiw_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_evaddiw_r_r_imm(dst, src, imm)) }
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inst_evsubfw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfw_r_r_r(dst, src, src2)) }
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inst_evsubifw_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EVSUBIFW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_evsubifw_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_evsubifw_r_r_imm(dst, src, imm)) }
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inst_evabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evabs_r_r(dst, src)) }
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inst_evextsh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVEXTSH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evextsh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evextsh_r_r(dst, src)) }
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inst_evextsb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVEXTSB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evextsb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evextsb_r_r(dst, src)) }
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inst_evcntlzw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVCNTLZW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evcntlzw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evcntlzw_r_r(dst, src)) }
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inst_evcntlsw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVCNTLSW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evcntlsw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evcntlsw_r_r(dst, src)) }
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inst_evrlw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrlw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrlw_r_r_r(dst, src, src2)) }
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inst_evrlwi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EVRLWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_evrlwi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_evrlwi_r_r_imm(dst, src, imm)) }
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inst_evslw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSLW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evslw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evslw_r_r_r(dst, src, src2)) }
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inst_evslwi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EVSLWI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_evslwi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_evslwi_r_r_imm(dst, src, imm)) }
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inst_evsplati_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EVSPLATI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_evsplati_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_evsplati_r_imm(dst, imm)) }
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inst_evsplatfi_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EVSPLATFI, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_evsplatfi_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_evsplatfi_r_imm(dst, imm)) }
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inst_evsrwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrwu_r_r_r(dst, src, src2)) }
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inst_evsrws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrws_r_r_r(dst, src, src2)) }
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inst_evsrwiu_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EVSRWIU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_evsrwiu_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_evsrwiu_r_r_imm(dst, src, imm)) }
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inst_evsrwis_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EVSRWIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_evsrwis_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_evsrwis_r_r_imm(dst, src, imm)) }
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inst_evand_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evand_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evand_r_r_r(dst, src, src2)) }
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inst_evor_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evor_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evor_r_r_r(dst, src, src2)) }
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inst_evxor_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVXOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evxor_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evxor_r_r_r(dst, src, src2)) }
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inst_evnand_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNAND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnand_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnand_r_r_r(dst, src, src2)) }
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inst_evnor_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnor_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnor_r_r_r(dst, src, src2)) }
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inst_evandc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVANDC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evandc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evandc_r_r_r(dst, src, src2)) }
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inst_evorc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVORC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evorc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evorc_r_r_r(dst, src, src2)) }
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inst_eveqv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVEQV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_eveqv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eveqv_r_r_r(dst, src, src2)) }
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inst_evcmpgts_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPGTS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmpgts_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmpgts_crf_r_r(dst, src, src2)) }
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inst_evcmpgtu_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPGTU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmpgtu_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmpgtu_crf_r_r(dst, src, src2)) }
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inst_evcmplts_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPLTS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmplts_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmplts_crf_r_r(dst, src, src2)) }
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inst_evcmpltu_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPLTU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmpltu_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmpltu_crf_r_r(dst, src, src2)) }
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inst_evcmpeq_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmpeq_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmpeq_crf_r_r(dst, src, src2)) }
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inst_evsel_r_r_r_crf :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EVSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_evsel_r_r_r_crf :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_evsel_r_r_r_crf(dst, src, src2, src3)) }
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inst_evmergehi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMERGEHI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmergehi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmergehi_r_r_r(dst, src, src2)) }
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inst_evmergelo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMERGELO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmergelo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmergelo_r_r_r(dst, src, src2)) }
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inst_evmergehilo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMERGEHILO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmergehilo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmergehilo_r_r_r(dst, src, src2)) }
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inst_evmergelohi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMERGELOHI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmergelohi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmergelohi_r_r_r(dst, src, src2)) }
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inst_evdivws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDIVWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdivws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdivws_r_r_r(dst, src, src2)) }
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inst_evdivwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDIVWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdivwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdivwu_r_r_r(dst, src, src2)) }
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inst_evmra_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVMRA, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evmra_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evmra_r_r(dst, src)) }
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inst_evldd_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLDD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evldd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evldd_r_mem(dst, addr)) }
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inst_evlddx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlddx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlddx_r_r_r(dst, src, src2)) }
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inst_evldw_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLDW, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evldw_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evldw_r_mem(dst, addr)) }
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inst_evldwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldwx_r_r_r(dst, src, src2)) }
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inst_evldh_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLDH, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evldh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evldh_r_mem(dst, addr)) }
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inst_evldhx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldhx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldhx_r_r_r(dst, src, src2)) }
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inst_evstdd_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVSTDD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evstdd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evstdd_r_mem(dst, addr)) }
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inst_evstddx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstddx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstddx_r_r_r(dst, src, src2)) }
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inst_evstdw_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVSTDW, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evstdw_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evstdw_r_mem(dst, addr)) }
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inst_evstdwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdwx_r_r_r(dst, src, src2)) }
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inst_evstdh_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVSTDH, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evstdh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evstdh_r_mem(dst, addr)) }
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inst_evstdhx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdhx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdhx_r_r_r(dst, src, src2)) }
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inst_evlwwsplat_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLWWSPLAT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evlwwsplat_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evlwwsplat_r_mem(dst, addr)) }
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inst_evlwhsplat_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLWHSPLAT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evlwhsplat_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evlwhsplat_r_mem(dst, addr)) }
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inst_evlhhesplat_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLHHESPLAT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evlhhesplat_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evlhhesplat_r_mem(dst, addr)) }
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inst_evlhhossplat_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLHHOSSPLAT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evlhhossplat_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evlhhossplat_r_mem(dst, addr)) }
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inst_evlhhousplat_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLHHOUSPLAT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evlhhousplat_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evlhhousplat_r_mem(dst, addr)) }
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inst_evlwhe_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLWHE, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evlwhe_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evlwhe_r_mem(dst, addr)) }
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inst_evlwhou_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLWHOU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evlwhou_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evlwhou_r_mem(dst, addr)) }
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inst_evlwhos_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVLWHOS, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evlwhos_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evlwhos_r_mem(dst, addr)) }
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inst_evlwhex_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHEX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhex_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhex_r_r_r(dst, src, src2)) }
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inst_evstwwe_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVSTWWE, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evstwwe_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evstwwe_r_mem(dst, addr)) }
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inst_evstwwo_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVSTWWO, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evstwwo_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evstwwo_r_mem(dst, addr)) }
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inst_evstwhe_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVSTWHE, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evstwhe_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evstwhe_r_mem(dst, addr)) }
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inst_evstwho_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .EVSTWHO, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_evstwho_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_evstwho_r_mem(dst, addr)) }
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inst_evstwhex_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWHEX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwhex_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwhex_r_r_r(dst, src, src2)) }
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inst_evfsadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsadd_r_r_r(dst, src, src2)) }
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inst_evfssub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfssub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfssub_r_r_r(dst, src, src2)) }
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inst_evfsabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfsabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfsabs_r_r(dst, src)) }
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inst_evfsnabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSNABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfsnabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfsnabs_r_r(dst, src)) }
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inst_evfsneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSNEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfsneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfsneg_r_r(dst, src)) }
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inst_evfsmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSMUL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsmul_r_r_r(dst, src, src2)) }
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inst_evfsdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSDIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsdiv_r_r_r(dst, src, src2)) }
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inst_evfscmpgt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSCMPGT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfscmpgt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfscmpgt_crf_r_r(dst, src, src2)) }
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inst_evfscmplt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSCMPLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfscmplt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfscmplt_crf_r_r(dst, src, src2)) }
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inst_evfscmpeq_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSCMPEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfscmpeq_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfscmpeq_crf_r_r(dst, src, src2)) }
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inst_evfststgt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSTSTGT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfststgt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfststgt_crf_r_r(dst, src, src2)) }
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inst_evfststlt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSTSTLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfststlt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfststlt_crf_r_r(dst, src, src2)) }
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inst_evfststeq_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSTSTEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfststeq_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfststeq_crf_r_r(dst, src, src2)) }
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inst_evfscfui_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCFUI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfscfui_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfscfui_r_r(dst, src)) }
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inst_evfscfsi_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCFSI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfscfsi_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfscfsi_r_r(dst, src)) }
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inst_evfscfuf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCFUF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfscfuf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfscfuf_r_r(dst, src)) }
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inst_evfscfsf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCFSF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfscfsf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfscfsf_r_r(dst, src)) }
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inst_evfsctui_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCTUI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfsctui_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfsctui_r_r(dst, src)) }
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inst_evfsctsi_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCTSI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfsctsi_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfsctsi_r_r(dst, src)) }
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inst_evfsctuf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCTUF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfsctuf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfsctuf_r_r(dst, src)) }
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inst_evfsctsf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCTSF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfsctsf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfsctsf_r_r(dst, src)) }
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inst_evfsctuiz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCTUIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfsctuiz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfsctuiz_r_r(dst, src)) }
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inst_evfsctsiz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCTSIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfsctsiz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfsctsiz_r_r(dst, src)) }
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inst_efsadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efsadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efsadd_r_r_r(dst, src, src2)) }
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inst_efssub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efssub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efssub_r_r_r(dst, src, src2)) }
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inst_efsabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efsabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efsabs_r_r(dst, src)) }
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inst_efsnabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSNABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efsnabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efsnabs_r_r(dst, src)) }
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inst_efsneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSNEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efsneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efsneg_r_r(dst, src)) }
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inst_efsmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSMUL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efsmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efsmul_r_r_r(dst, src, src2)) }
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inst_efsdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSDIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efsdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efsdiv_r_r_r(dst, src, src2)) }
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inst_efscmpgt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSCMPGT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efscmpgt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efscmpgt_crf_r_r(dst, src, src2)) }
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inst_efscmplt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSCMPLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efscmplt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efscmplt_crf_r_r(dst, src, src2)) }
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inst_efscmpeq_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSCMPEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efscmpeq_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efscmpeq_crf_r_r(dst, src, src2)) }
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inst_efststgt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSTSTGT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efststgt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efststgt_crf_r_r(dst, src, src2)) }
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inst_efststlt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSTSTLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efststlt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efststlt_crf_r_r(dst, src, src2)) }
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inst_efststeq_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSTSTEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efststeq_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efststeq_crf_r_r(dst, src, src2)) }
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inst_efscfui_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCFUI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efscfui_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efscfui_r_r(dst, src)) }
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inst_efscfsi_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCFSI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efscfsi_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efscfsi_r_r(dst, src)) }
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inst_efscfuf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCFUF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efscfuf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efscfuf_r_r(dst, src)) }
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inst_efscfsf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCFSF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efscfsf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efscfsf_r_r(dst, src)) }
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inst_efsctui_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCTUI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efsctui_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efsctui_r_r(dst, src)) }
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inst_efsctsi_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCTSI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efsctsi_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efsctsi_r_r(dst, src)) }
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inst_efsctuf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCTUF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efsctuf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efsctuf_r_r(dst, src)) }
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inst_efsctsf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCTSF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efsctsf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efsctsf_r_r(dst, src)) }
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inst_efsctuiz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCTUIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efsctuiz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efsctuiz_r_r(dst, src)) }
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inst_efsctsiz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCTSIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efsctsiz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efsctsiz_r_r(dst, src)) }
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inst_efscfd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCFD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efscfd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efscfd_r_r(dst, src)) }
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inst_efdadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdadd_r_r_r(dst, src, src2)) }
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inst_efdsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdsub_r_r_r(dst, src, src2)) }
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inst_efdabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdabs_r_r(dst, src)) }
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inst_efdnabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDNABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdnabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdnabs_r_r(dst, src)) }
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inst_efdneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDNEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdneg_r_r(dst, src)) }
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inst_efdmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDMUL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdmul_r_r_r(dst, src, src2)) }
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inst_efddiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDDIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efddiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efddiv_r_r_r(dst, src, src2)) }
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inst_efdcmpgt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDCMPGT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdcmpgt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdcmpgt_crf_r_r(dst, src, src2)) }
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inst_efdcmplt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDCMPLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdcmplt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdcmplt_crf_r_r(dst, src, src2)) }
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inst_efdcmpeq_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDCMPEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdcmpeq_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdcmpeq_crf_r_r(dst, src, src2)) }
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inst_efdtstgt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDTSTGT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdtstgt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdtstgt_crf_r_r(dst, src, src2)) }
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inst_efdtstlt_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDTSTLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdtstlt_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdtstlt_crf_r_r(dst, src, src2)) }
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inst_efdtsteq_crf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDTSTEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdtsteq_crf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdtsteq_crf_r_r(dst, src, src2)) }
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inst_efdcfui_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCFUI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdcfui_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdcfui_r_r(dst, src)) }
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inst_efdcfsi_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCFSI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdcfsi_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdcfsi_r_r(dst, src)) }
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inst_efdcfuf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCFUF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdcfuf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdcfuf_r_r(dst, src)) }
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inst_efdcfsf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCFSF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdcfsf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdcfsf_r_r(dst, src)) }
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inst_efdctui_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCTUI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdctui_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdctui_r_r(dst, src)) }
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inst_efdctsi_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCTSI, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdctsi_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdctsi_r_r(dst, src)) }
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inst_efdctuf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCTUF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdctuf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdctuf_r_r(dst, src)) }
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inst_efdctsf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCTSF, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdctsf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdctsf_r_r(dst, src)) }
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inst_efdctuiz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCTUIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdctuiz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdctuiz_r_r(dst, src)) }
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inst_efdctsiz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCTSIZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdctsiz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdctsiz_r_r(dst, src)) }
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inst_efdcfs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCFS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdcfs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdcfs_r_r(dst, src)) }
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inst_efdcfsid_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCFSID, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdcfsid_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdcfsid_r_r(dst, src)) }
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inst_efdcfuid_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCFUID, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdcfuid_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdcfuid_r_r(dst, src)) }
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inst_efdctsidz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCTSIDZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdctsidz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdctsidz_r_r(dst, src)) }
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inst_efdctuidz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCTUIDZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdctuidz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdctuidz_r_r(dst, src)) }
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inst_evmhossf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhossf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhossf_r_r_r(dst, src, src2)) }
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inst_evmhossfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhossfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhossfa_r_r_r(dst, src, src2)) }
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inst_evmhossfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSSFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhossfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhossfaaw_r_r_r(dst, src, src2)) }
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inst_evmhossfanw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSSFANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhossfanw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhossfanw_r_r_r(dst, src, src2)) }
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inst_evmhossiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhossiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhossiaaw_r_r_r(dst, src, src2)) }
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inst_evmhossianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSSIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhossianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhossianw_r_r_r(dst, src, src2)) }
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inst_evmhosmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosmf_r_r_r(dst, src, src2)) }
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inst_evmhosmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosmfa_r_r_r(dst, src, src2)) }
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inst_evmhosmfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSMFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosmfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosmfaaw_r_r_r(dst, src, src2)) }
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inst_evmhosmfanw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSMFANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosmfanw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosmfanw_r_r_r(dst, src, src2)) }
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inst_evmhosmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosmi_r_r_r(dst, src, src2)) }
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inst_evmhosmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosmia_r_r_r(dst, src, src2)) }
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inst_evmhosmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosmiaaw_r_r_r(dst, src, src2)) }
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inst_evmhosmianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSMIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosmianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosmianw_r_r_r(dst, src, src2)) }
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inst_evmhesmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesmf_r_r_r(dst, src, src2)) }
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inst_evmhesmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesmfa_r_r_r(dst, src, src2)) }
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inst_evmhesmfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESMFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesmfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesmfaaw_r_r_r(dst, src, src2)) }
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inst_evmhesmfanw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESMFANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesmfanw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesmfanw_r_r_r(dst, src, src2)) }
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inst_evmhesmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesmi_r_r_r(dst, src, src2)) }
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inst_evmhesmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesmia_r_r_r(dst, src, src2)) }
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inst_evmhesmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesmiaaw_r_r_r(dst, src, src2)) }
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inst_evmhesmianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESMIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesmianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesmianw_r_r_r(dst, src, src2)) }
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inst_evmhessf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhessf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhessf_r_r_r(dst, src, src2)) }
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inst_evmhessfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhessfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhessfa_r_r_r(dst, src, src2)) }
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inst_evmhessfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESSFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhessfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhessfaaw_r_r_r(dst, src, src2)) }
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inst_evmhessfanw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESSFANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhessfanw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhessfanw_r_r_r(dst, src, src2)) }
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inst_evmhessiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhessiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhessiaaw_r_r_r(dst, src, src2)) }
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inst_evmhessianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESSIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhessianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhessianw_r_r_r(dst, src, src2)) }
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inst_evmheumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmheumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmheumi_r_r_r(dst, src, src2)) }
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inst_evmheumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmheumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmheumia_r_r_r(dst, src, src2)) }
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inst_evmheumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmheumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmheumiaaw_r_r_r(dst, src, src2)) }
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inst_evmheumianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEUMIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmheumianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmheumianw_r_r_r(dst, src, src2)) }
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inst_evmheusiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEUSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmheusiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmheusiaaw_r_r_r(dst, src, src2)) }
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inst_evmheusianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEUSIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmheusianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmheusianw_r_r_r(dst, src, src2)) }
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inst_evmhoumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhoumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhoumi_r_r_r(dst, src, src2)) }
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inst_evmhoumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhoumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhoumia_r_r_r(dst, src, src2)) }
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inst_evmhoumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhoumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhoumiaaw_r_r_r(dst, src, src2)) }
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inst_evmhoumianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOUMIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhoumianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhoumianw_r_r_r(dst, src, src2)) }
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inst_evmhousiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOUSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhousiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhousiaaw_r_r_r(dst, src, src2)) }
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inst_evmhousianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOUSIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhousianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhousianw_r_r_r(dst, src, src2)) }
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inst_evmhogsmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOGSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhogsmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhogsmfaa_r_r_r(dst, src, src2)) }
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inst_evmhogsmfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOGSMFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhogsmfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhogsmfan_r_r_r(dst, src, src2)) }
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inst_evmhogsmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOGSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhogsmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhogsmiaa_r_r_r(dst, src, src2)) }
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inst_evmhogsmian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOGSMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhogsmian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhogsmian_r_r_r(dst, src, src2)) }
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inst_evmhogumiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOGUMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhogumiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhogumiaa_r_r_r(dst, src, src2)) }
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inst_evmhogumian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOGUMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhogumian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhogumian_r_r_r(dst, src, src2)) }
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inst_evmhegsmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEGSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhegsmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhegsmfaa_r_r_r(dst, src, src2)) }
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inst_evmhegsmfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEGSMFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhegsmfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhegsmfan_r_r_r(dst, src, src2)) }
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inst_evmhegsmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEGSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhegsmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhegsmiaa_r_r_r(dst, src, src2)) }
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inst_evmhegsmian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEGSMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhegsmian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhegsmian_r_r_r(dst, src, src2)) }
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inst_evmhegumiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEGUMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhegumiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhegumiaa_r_r_r(dst, src, src2)) }
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inst_evmhegumian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHEGUMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhegumian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhegumian_r_r_r(dst, src, src2)) }
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inst_evmwhssf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssf_r_r_r(dst, src, src2)) }
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inst_evmwhssfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfa_r_r_r(dst, src, src2)) }
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inst_evmwlssiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlssiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlssiaaw_r_r_r(dst, src, src2)) }
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inst_evmwlssianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSSIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlssianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlssianw_r_r_r(dst, src, src2)) }
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inst_evmwhsmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhsmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhsmf_r_r_r(dst, src, src2)) }
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inst_evmwhsmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhsmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhsmfa_r_r_r(dst, src, src2)) }
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inst_evmwhsmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhsmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhsmi_r_r_r(dst, src, src2)) }
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inst_evmwhsmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhsmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhsmia_r_r_r(dst, src, src2)) }
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inst_evmwhumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhumi_r_r_r(dst, src, src2)) }
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inst_evmwhumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhumia_r_r_r(dst, src, src2)) }
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inst_evmwlsmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlsmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlsmiaaw_r_r_r(dst, src, src2)) }
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inst_evmwlsmianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSMIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlsmianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlsmianw_r_r_r(dst, src, src2)) }
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inst_evmwlumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlumi_r_r_r(dst, src, src2)) }
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inst_evmwlumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlumia_r_r_r(dst, src, src2)) }
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inst_evmwlumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlumiaaw_r_r_r(dst, src, src2)) }
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inst_evmwlumianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUMIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlumianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlumianw_r_r_r(dst, src, src2)) }
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inst_evmwlusiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlusiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlusiaaw_r_r_r(dst, src, src2)) }
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inst_evmwlusianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUSIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlusianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlusianw_r_r_r(dst, src, src2)) }
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inst_evmwsmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwsmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwsmf_r_r_r(dst, src, src2)) }
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inst_evmwsmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwsmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwsmfa_r_r_r(dst, src, src2)) }
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inst_evmwsmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwsmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwsmfaa_r_r_r(dst, src, src2)) }
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inst_evmwsmfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSMFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwsmfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwsmfan_r_r_r(dst, src, src2)) }
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inst_evmwsmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwsmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwsmi_r_r_r(dst, src, src2)) }
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inst_evmwsmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwsmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwsmia_r_r_r(dst, src, src2)) }
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inst_evmwsmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwsmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwsmiaa_r_r_r(dst, src, src2)) }
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inst_evmwsmian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwsmian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwsmian_r_r_r(dst, src, src2)) }
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inst_evmwssf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwssf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwssf_r_r_r(dst, src, src2)) }
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inst_evmwssfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwssfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwssfa_r_r_r(dst, src, src2)) }
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inst_evmwssfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSSFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwssfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwssfaa_r_r_r(dst, src, src2)) }
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inst_evmwssfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSSFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwssfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwssfan_r_r_r(dst, src, src2)) }
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inst_evmwumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwumi_r_r_r(dst, src, src2)) }
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inst_evmwumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwumia_r_r_r(dst, src, src2)) }
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inst_evmwumiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWUMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwumiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwumiaa_r_r_r(dst, src, src2)) }
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inst_evmwumian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWUMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwumian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwumian_r_r_r(dst, src, src2)) }
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inst_brinc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BRINC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_brinc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_brinc_r_r_r(dst, src, src2)) }
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inst_evlwhsplatx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHSPLATX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhsplatx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhsplatx_r_r_r(dst, src, src2)) }
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inst_evlwwsplatx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWWSPLATX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwwsplatx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwwsplatx_r_r_r(dst, src, src2)) }
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inst_evlhhesplatx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHESPLATX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhesplatx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhesplatx_r_r_r(dst, src, src2)) }
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inst_evlhhossplatx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHOSSPLATX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhossplatx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhossplatx_r_r_r(dst, src, src2)) }
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inst_evlhhousplatx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHOUSPLATX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhousplatx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhousplatx_r_r_r(dst, src, src2)) }
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inst_evlwhoux_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHOUX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhoux_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhoux_r_r_r(dst, src, src2)) }
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inst_evlwhosx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHOSX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhosx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhosx_r_r_r(dst, src, src2)) }
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inst_evstwwex_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWWEX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwwex_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwwex_r_r_r(dst, src, src2)) }
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inst_evstwwox_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWWOX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwwox_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwwox_r_r_r(dst, src, src2)) }
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inst_evstwhox_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWHOX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwhox_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwhox_r_r_r(dst, src, src2)) }
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inst_icbtls_imm_r_r :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ICBTLS, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_icbtls_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_icbtls_imm_r_r(imm, dst, src)) }
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inst_icblc_imm_r_r :: #force_inline proc "contextless" (imm: i64, dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ICBLC, operand_count = 3, length = 4, ops = {op_imm(imm), op_reg(dst), op_reg(src), {}}} }
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emit_icblc_imm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, dst: Register, src: Register) { append(instructions, inst_icblc_imm_r_r(imm, dst, src)) }
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inst_dcbst_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DCBST, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_dcbst_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dcbst_r_r(dst, src)) }
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inst_mbar_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .MBAR, operand_count = 1, length = 4, ops = {op_imm(imm), {}, {}, {}}} }
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emit_mbar_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_mbar_imm(imm)) }
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inst_mtdcr_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MTDCR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mtdcr_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mtdcr_r_r(dst, src)) }
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inst_mfdcr_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MFDCR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_mfdcr_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mfdcr_r_r(dst, src)) }
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inst_tlbilxva_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TLBILXVA, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_tlbilxva_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tlbilxva_r_r(dst, src)) }
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inst_xscvsxdsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVSXDSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvsxdsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvsxdsp_vs_vs(dst, src)) }
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inst_xscvuxdsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XSCVUXDSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xscvuxdsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xscvuxdsp_vs_vs(dst, src)) }
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inst_xxbrh_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XXBRH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xxbrh_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xxbrh_vs_vs(dst, src)) }
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inst_xxbrw_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XXBRW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xxbrw_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xxbrw_vs_vs(dst, src)) }
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inst_xxbrd_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XXBRD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xxbrd_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xxbrd_vs_vs(dst, src)) }
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inst_xxbrq_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XXBRQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xxbrq_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xxbrq_vs_vs(dst, src)) }
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inst_pdepd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PDEPD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_pdepd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pdepd_r_r_r(dst, src, src2)) }
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inst_pextd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PEXTD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_pextd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pextd_r_r_r(dst, src, src2)) }
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inst_cntlzdm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CNTLZDM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cntlzdm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cntlzdm_r_r_r(dst, src, src2)) }
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inst_cnttzdm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CNTTZDM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cnttzdm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cnttzdm_r_r_r(dst, src, src2)) }
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inst_cfuged_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CFUGED, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cfuged_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cfuged_r_r_r(dst, src, src2)) }
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inst_brh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BRH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_brh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brh_r_r(dst, src)) }
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inst_brw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BRW, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_brw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brw_r_r(dst, src)) }
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inst_brd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BRD, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_brd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brd_r_r(dst, src)) }
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inst_divweo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divweo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divweo_r_r_r(dst, src, src2)) }
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inst_divweuo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWEUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divweuo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divweuo_r_r_r(dst, src, src2)) }
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inst_divdeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdeo_r_r_r(dst, src, src2)) }
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inst_divdeuo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDEUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdeuo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdeuo_r_r_r(dst, src, src2)) }
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inst_xvtlsbb_crf_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVTLSBB, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvtlsbb_crf_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvtlsbb_crf_vs(dst, src)) }
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inst_xvcvhpsp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVHPSP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvhpsp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvhpsp_vs_vs(dst, src)) }
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inst_xvcvsphp_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XVCVSPHP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_xvcvsphp_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xvcvsphp_vs_vs(dst, src)) }
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inst_xxpermr_vs_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XXPERMR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_xxpermr_vs_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xxpermr_vs_vs_vs(dst, src, src2)) }
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inst_evfsmadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSMADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsmadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsmadd_r_r_r(dst, src, src2)) }
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inst_evfsmsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSMSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsmsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsmsub_r_r_r(dst, src, src2)) }
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inst_evfsnmadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSNMADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsnmadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsnmadd_r_r_r(dst, src, src2)) }
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inst_evfsnmsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSNMSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsnmsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsnmsub_r_r_r(dst, src, src2)) }
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inst_efsmadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSMADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efsmadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efsmadd_r_r_r(dst, src, src2)) }
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inst_efsmsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSMSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efsmsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efsmsub_r_r_r(dst, src, src2)) }
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inst_efsnmadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSNMADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efsnmadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efsnmadd_r_r_r(dst, src, src2)) }
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inst_efsnmsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSNMSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efsnmsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efsnmsub_r_r_r(dst, src, src2)) }
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inst_efdmadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDMADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdmadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdmadd_r_r_r(dst, src, src2)) }
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inst_efdmsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDMSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdmsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdmsub_r_r_r(dst, src, src2)) }
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inst_efdnmadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDNMADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdnmadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdnmadd_r_r_r(dst, src, src2)) }
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inst_efdnmsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDNMSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdnmsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdnmsub_r_r_r(dst, src, src2)) }
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inst_evfssqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSSQRT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfssqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfssqrt_r_r(dst, src)) }
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inst_evfsmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSMAX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsmax_r_r_r(dst, src, src2)) }
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inst_evfsmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSMIN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsmin_r_r_r(dst, src, src2)) }
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inst_evfscfh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCFH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfscfh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfscfh_r_r(dst, src)) }
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inst_evfscth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EVFSCTH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_evfscth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_evfscth_r_r(dst, src)) }
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inst_evfsaddsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSADDSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsaddsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsaddsub_r_r_r(dst, src, src2)) }
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inst_evfssubadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSSUBADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfssubadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfssubadd_r_r_r(dst, src, src2)) }
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inst_evfssum_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSSUM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfssum_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfssum_r_r_r(dst, src, src2)) }
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inst_evfsdiff_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSDIFF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsdiff_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsdiff_r_r_r(dst, src, src2)) }
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inst_evfssumdiff_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSSUMDIFF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfssumdiff_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfssumdiff_r_r_r(dst, src, src2)) }
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inst_evfsdiffsum_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSDIFFSUM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsdiffsum_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsdiffsum_r_r_r(dst, src, src2)) }
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inst_evfsaddx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSADDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsaddx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsaddx_r_r_r(dst, src, src2)) }
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inst_evfssubx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSSUBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfssubx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfssubx_r_r_r(dst, src, src2)) }
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inst_evfsaddsubx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSADDSUBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsaddsubx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsaddsubx_r_r_r(dst, src, src2)) }
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inst_evfssubaddx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSSUBADDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfssubaddx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfssubaddx_r_r_r(dst, src, src2)) }
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inst_evfsmulx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSMULX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsmulx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsmulx_r_r_r(dst, src, src2)) }
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inst_evfsmule_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSMULE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsmule_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsmule_r_r_r(dst, src, src2)) }
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inst_evfsmulo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVFSMULO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evfsmulo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evfsmulo_r_r_r(dst, src, src2)) }
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inst_efssqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSSQRT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efssqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efssqrt_r_r(dst, src)) }
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inst_efsmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSMAX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efsmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efsmax_r_r_r(dst, src, src2)) }
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inst_efsmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFSMIN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efsmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efsmin_r_r_r(dst, src, src2)) }
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inst_efscfh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCFH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efscfh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efscfh_r_r(dst, src)) }
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inst_efscth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFSCTH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efscth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efscth_r_r(dst, src)) }
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inst_efdsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDSQRT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdsqrt_r_r(dst, src)) }
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inst_efdmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDMAX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdmax_r_r_r(dst, src, src2)) }
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inst_efdmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EFDMIN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_efdmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_efdmin_r_r_r(dst, src, src2)) }
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inst_efdcfh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCFH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdcfh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdcfh_r_r(dst, src)) }
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inst_efdcth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EFDCTH, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_efdcth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_efdcth_r_r(dst, src)) }
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inst_evsubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubw_r_r_r(dst, src, src2)) }
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inst_evsubiw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBIW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubiw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubiw_r_r_r(dst, src, src2)) }
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inst_evneg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evneg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evneg_r_r_r(dst, src, src2)) }
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inst_evrndw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndw_r_r_r(dst, src, src2)) }
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inst_evmr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmr_r_r_r(dst, src, src2)) }
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inst_evnot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnot_r_r_r(dst, src, src2)) }
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inst_evsadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsadd_r_r_r(dst, src, src2)) }
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inst_evssub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSSUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evssub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evssub_r_r_r(dst, src, src2)) }
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inst_evsabs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSABS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsabs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsabs_r_r_r(dst, src, src2)) }
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inst_evsnabs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSNABS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsnabs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsnabs_r_r_r(dst, src, src2)) }
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inst_evsneg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSNEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsneg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsneg_r_r_r(dst, src, src2)) }
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inst_evsmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSMUL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsmul_r_r_r(dst, src, src2)) }
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inst_evsdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSDIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsdiv_r_r_r(dst, src, src2)) }
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inst_evscmpgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCMPGT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evscmpgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evscmpgt_r_r_r(dst, src, src2)) }
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inst_evsgmplt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSGMPLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsgmplt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsgmplt_r_r_r(dst, src, src2)) }
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inst_evsgmpeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSGMPEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsgmpeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsgmpeq_r_r_r(dst, src, src2)) }
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inst_evscfui_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCFUI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evscfui_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evscfui_r_r_r(dst, src, src2)) }
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inst_evscfsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCFSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evscfsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evscfsi_r_r_r(dst, src, src2)) }
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inst_evscfuf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCFUF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evscfuf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evscfuf_r_r_r(dst, src, src2)) }
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inst_evscfsf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCFSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evscfsf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evscfsf_r_r_r(dst, src, src2)) }
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inst_evsctui_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCTUI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsctui_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsctui_r_r_r(dst, src, src2)) }
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inst_evsctsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCTSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsctsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsctsi_r_r_r(dst, src, src2)) }
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inst_evsctuf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCTUF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsctuf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsctuf_r_r_r(dst, src, src2)) }
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inst_evsctsf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCTSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsctsf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsctsf_r_r_r(dst, src, src2)) }
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inst_evsctuiz_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCTUIZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsctuiz_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsctuiz_r_r_r(dst, src, src2)) }
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inst_evsctsiz_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSCTSIZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsctsiz_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsctsiz_r_r_r(dst, src, src2)) }
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inst_evststgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTSTGT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evststgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evststgt_r_r_r(dst, src, src2)) }
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inst_evststlt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTSTLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evststlt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evststlt_r_r_r(dst, src, src2)) }
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inst_evststeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTSTEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evststeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evststeq_r_r_r(dst, src, src2)) }
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inst_evmwlssf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlssf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlssf_r_r_r(dst, src, src2)) }
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inst_evmwlsmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlsmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlsmf_r_r_r(dst, src, src2)) }
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inst_evmwlssfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlssfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlssfa_r_r_r(dst, src, src2)) }
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inst_evmwlsmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlsmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlsmfa_r_r_r(dst, src, src2)) }
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inst_evaddusiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDUSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddusiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddusiaaw_r_r_r(dst, src, src2)) }
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inst_evaddssiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddssiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddssiaaw_r_r_r(dst, src, src2)) }
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inst_evsubfusiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFUSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfusiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfusiaaw_r_r_r(dst, src, src2)) }
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inst_evsubfssiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFSSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfssiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfssiaaw_r_r_r(dst, src, src2)) }
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inst_evaddumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddumiaaw_r_r_r(dst, src, src2)) }
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inst_evaddsmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsmiaaw_r_r_r(dst, src, src2)) }
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inst_evsubfumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfumiaaw_r_r_r(dst, src, src2)) }
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inst_evsubfsmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFSMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfsmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfsmiaaw_r_r_r(dst, src, src2)) }
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inst_evmwlssfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSSFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlssfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlssfaaw_r_r_r(dst, src, src2)) }
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inst_evmwhusiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHUSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhusiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhusiaa_r_r_r(dst, src, src2)) }
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inst_evmwhssmaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSMAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssmaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssmaa_r_r_r(dst, src, src2)) }
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inst_evmwhssfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfaa_r_r_r(dst, src, src2)) }
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inst_evmwlsmfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSMFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlsmfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlsmfaaw_r_r_r(dst, src, src2)) }
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inst_evmwhumiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHUMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhumiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhumiaa_r_r_r(dst, src, src2)) }
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inst_evmwhsmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhsmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhsmiaa_r_r_r(dst, src, src2)) }
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inst_evmwhsmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhsmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhsmfaa_r_r_r(dst, src, src2)) }
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inst_evmwhgumiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHGUMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhgumiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhgumiaa_r_r_r(dst, src, src2)) }
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inst_evmwhgsmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHGSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhgsmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhgsmiaa_r_r_r(dst, src, src2)) }
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inst_evmwhgssfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHGSSFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhgssfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhgssfaa_r_r_r(dst, src, src2)) }
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inst_evmwhgsmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHGSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhgsmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhgsmfaa_r_r_r(dst, src, src2)) }
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inst_evmwlssfanw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSSFANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlssfanw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlssfanw_r_r_r(dst, src, src2)) }
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inst_evmwhusian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHUSIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhusian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhusian_r_r_r(dst, src, src2)) }
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inst_evmwhssian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssian_r_r_r(dst, src, src2)) }
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inst_evmwhssfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfan_r_r_r(dst, src, src2)) }
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inst_evmwlsmfanw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSMFANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlsmfanw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlsmfanw_r_r_r(dst, src, src2)) }
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inst_evmwhumian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHUMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhumian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhumian_r_r_r(dst, src, src2)) }
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inst_evmwhsmian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhsmian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhsmian_r_r_r(dst, src, src2)) }
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inst_evmwhsmfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSMFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhsmfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhsmfan_r_r_r(dst, src, src2)) }
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inst_evmwhgumian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHGUMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhgumian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhgumian_r_r_r(dst, src, src2)) }
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inst_evmwhgsmian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHGSMIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhgsmian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhgsmian_r_r_r(dst, src, src2)) }
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inst_evmwhgssfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHGSSFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhgssfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhgssfan_r_r_r(dst, src, src2)) }
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inst_evmwhgsmfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHGSMFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhgsmfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhgsmfan_r_r_r(dst, src, src2)) }
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inst_evdotpwcssi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssi_r_r_r(dst, src, src2)) }
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inst_evdotpwcsmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcsmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcsmi_r_r_r(dst, src, src2)) }
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inst_evdotpwcssfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssfr_r_r_r(dst, src, src2)) }
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inst_evdotpwcssf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssf_r_r_r(dst, src, src2)) }
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inst_evdotpwgasmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGASMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgasmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgasmf_r_r_r(dst, src, src2)) }
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inst_evdotpwxgasmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGASMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgasmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgasmf_r_r_r(dst, src, src2)) }
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inst_evdotpwgasmfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGASMFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgasmfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgasmfr_r_r_r(dst, src, src2)) }
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inst_evdotpwxgasmfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGASMFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgasmfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgasmfr_r_r_r(dst, src, src2)) }
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inst_evdotpwgssmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGSSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgssmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgssmf_r_r_r(dst, src, src2)) }
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inst_evdotpwxgssmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGSSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgssmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgssmf_r_r_r(dst, src, src2)) }
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inst_evdotpwgssmfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGSSMFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgssmfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgssmfr_r_r_r(dst, src, src2)) }
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inst_evdotpwxgssmfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGSSMFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgssmfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgssmfr_r_r_r(dst, src, src2)) }
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inst_evdotpwcssiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotpwcsmiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcsmiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcsmiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotpwcssfraaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSFRAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssfraaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssfraaw3_r_r_r(dst, src, src2)) }
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inst_evdotpwcssfaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSFAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssfaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssfaaw3_r_r_r(dst, src, src2)) }
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inst_evdotpwgasmfaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGASMFAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgasmfaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgasmfaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwxgasmfaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGASMFAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgasmfaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgasmfaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwgasmfraa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGASMFRAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgasmfraa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgasmfraa3_r_r_r(dst, src, src2)) }
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inst_evdotpwxgasmfraa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGASMFRAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgasmfraa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgasmfraa3_r_r_r(dst, src, src2)) }
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inst_evdotpwgssmfaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGSSMFAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgssmfaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgssmfaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwxgssmfaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGSSMFAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgssmfaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgssmfaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwgssmfraa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGSSMFRAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgssmfraa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgssmfraa3_r_r_r(dst, src, src2)) }
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inst_evdotpwxgssmfraa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGSSMFRAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgssmfraa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgssmfraa3_r_r_r(dst, src, src2)) }
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inst_evdotpwcssia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssia_r_r_r(dst, src, src2)) }
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inst_evdotpwcsmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcsmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcsmia_r_r_r(dst, src, src2)) }
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inst_evdotpwcssfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssfra_r_r_r(dst, src, src2)) }
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inst_evdotpwcssfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssfa_r_r_r(dst, src, src2)) }
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inst_evdotpwgasmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGASMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgasmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgasmfa_r_r_r(dst, src, src2)) }
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inst_evdotpwxgasmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGASMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgasmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgasmfa_r_r_r(dst, src, src2)) }
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inst_evdotpwgasmfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGASMFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgasmfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgasmfra_r_r_r(dst, src, src2)) }
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inst_evdotpwxgasmfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGASMFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgasmfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgasmfra_r_r_r(dst, src, src2)) }
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inst_evdotpwgssmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGSSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgssmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgssmfa_r_r_r(dst, src, src2)) }
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inst_evdotpwxgssmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGSSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgssmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgssmfa_r_r_r(dst, src, src2)) }
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inst_evdotpwgssmfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGSSMFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgssmfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgssmfra_r_r_r(dst, src, src2)) }
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inst_evdotpwxgssmfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGSSMFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgssmfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgssmfra_r_r_r(dst, src, src2)) }
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inst_evdotpwcssiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssiaaw_r_r_r(dst, src, src2)) }
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inst_evdotpwcsmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcsmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcsmiaaw_r_r_r(dst, src, src2)) }
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inst_evdotpwcssfraaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSFRAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssfraaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssfraaw_r_r_r(dst, src, src2)) }
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inst_evdotpwcssfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWCSSFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwcssfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwcssfaaw_r_r_r(dst, src, src2)) }
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inst_evdotpwgasmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGASMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgasmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgasmfaa_r_r_r(dst, src, src2)) }
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inst_evdotpwxgasmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGASMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgasmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgasmfaa_r_r_r(dst, src, src2)) }
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inst_evdotpwgasmfraa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGASMFRAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgasmfraa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgasmfraa_r_r_r(dst, src, src2)) }
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inst_evdotpwxgasmfraa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGASMFRAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgasmfraa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgasmfraa_r_r_r(dst, src, src2)) }
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inst_evdotpwgssmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGSSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgssmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgssmfaa_r_r_r(dst, src, src2)) }
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inst_evdotpwxgssmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGSSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgssmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgssmfaa_r_r_r(dst, src, src2)) }
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inst_evdotpwgssmfraa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWGSSMFRAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwgssmfraa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwgssmfraa_r_r_r(dst, src, src2)) }
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inst_evdotpwxgssmfraa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWXGSSMFRAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwxgssmfraa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwxgssmfraa_r_r_r(dst, src, src2)) }
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inst_evdotphihcssi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssi_r_r_r(dst, src, src2)) }
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inst_evdotplohcssi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssi_r_r_r(dst, src, src2)) }
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inst_evdotphihcssf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssf_r_r_r(dst, src, src2)) }
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inst_evdotplohcssf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssf_r_r_r(dst, src, src2)) }
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inst_evdotphihcsmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcsmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcsmi_r_r_r(dst, src, src2)) }
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inst_evdotplohcsmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcsmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcsmi_r_r_r(dst, src, src2)) }
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inst_evdotphihcssfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssfr_r_r_r(dst, src, src2)) }
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inst_evdotplohcssfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssfr_r_r_r(dst, src, src2)) }
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inst_evdotphihcssiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotplohcssiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphihcssfaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSFAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssfaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssfaaw3_r_r_r(dst, src, src2)) }
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inst_evdotplohcssfaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSFAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssfaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssfaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphihcsmiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcsmiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcsmiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotplohcsmiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcsmiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcsmiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphihcssfraaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSFRAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssfraaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssfraaw3_r_r_r(dst, src, src2)) }
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inst_evdotplohcssfraaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSFRAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssfraaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssfraaw3_r_r_r(dst, src, src2)) }
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inst_evdotphihcssia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssia_r_r_r(dst, src, src2)) }
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inst_evdotplohcssia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssia_r_r_r(dst, src, src2)) }
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inst_evdotphihcssfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssfa_r_r_r(dst, src, src2)) }
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inst_evdotplohcssfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssfa_r_r_r(dst, src, src2)) }
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inst_evdotphihcsmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcsmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcsmia_r_r_r(dst, src, src2)) }
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inst_evdotplohcsmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcsmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcsmia_r_r_r(dst, src, src2)) }
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inst_evdotphihcssfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssfra_r_r_r(dst, src, src2)) }
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inst_evdotplohcssfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssfra_r_r_r(dst, src, src2)) }
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inst_evdotphihcssiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssiaaw_r_r_r(dst, src, src2)) }
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inst_evdotplohcssiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphihcssfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssfaaw_r_r_r(dst, src, src2)) }
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inst_evdotplohcssfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssfaaw_r_r_r(dst, src, src2)) }
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inst_evdotphihcsmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcsmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcsmiaaw_r_r_r(dst, src, src2)) }
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inst_evdotplohcsmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcsmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcsmiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphihcssfraaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHIHCSSFRAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphihcssfraaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphihcssfraaw_r_r_r(dst, src, src2)) }
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inst_evdotplohcssfraaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPLOHCSSFRAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotplohcssfraaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotplohcssfraaw_r_r_r(dst, src, src2)) }
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inst_evdotphausi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHAUSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphausi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphausi_r_r_r(dst, src, src2)) }
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inst_evdotphassi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassi_r_r_r(dst, src, src2)) }
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inst_evdotphasusi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASUSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasusi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasusi_r_r_r(dst, src, src2)) }
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inst_evdotphassf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassf_r_r_r(dst, src, src2)) }
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inst_evdotphsssf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssf_r_r_r(dst, src, src2)) }
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inst_evdotphaumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHAUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphaumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphaumi_r_r_r(dst, src, src2)) }
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inst_evdotphasmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasmi_r_r_r(dst, src, src2)) }
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inst_evdotphasumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasumi_r_r_r(dst, src, src2)) }
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inst_evdotphassfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassfr_r_r_r(dst, src, src2)) }
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inst_evdotphssmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphssmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphssmi_r_r_r(dst, src, src2)) }
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inst_evdotphsssi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssi_r_r_r(dst, src, src2)) }
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inst_evdotphsssfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssfr_r_r_r(dst, src, src2)) }
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inst_evdotphausiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHAUSIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphausiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphausiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphassiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphasusiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASUSIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasusiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasusiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphassfaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSFAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassfaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassfaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphsssiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphsssfaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSFAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssfaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssfaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphaumiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHAUMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphaumiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphaumiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphasmiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasmiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasmiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphasumiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASUMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasumiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasumiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphassfraaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSFRAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassfraaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassfraaw3_r_r_r(dst, src, src2)) }
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inst_evdotphssmiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphssmiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphssmiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotphsssfraaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSFRAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssfraaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssfraaw3_r_r_r(dst, src, src2)) }
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inst_evdotphausia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHAUSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphausia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphausia_r_r_r(dst, src, src2)) }
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inst_evdotphassia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassia_r_r_r(dst, src, src2)) }
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inst_evdotphasusia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASUSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasusia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasusia_r_r_r(dst, src, src2)) }
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inst_evdotphassfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassfa_r_r_r(dst, src, src2)) }
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inst_evdotphsssfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssfa_r_r_r(dst, src, src2)) }
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inst_evdotphaumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHAUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphaumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphaumia_r_r_r(dst, src, src2)) }
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inst_evdotphasmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasmia_r_r_r(dst, src, src2)) }
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inst_evdotphasumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasumia_r_r_r(dst, src, src2)) }
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inst_evdotphassfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassfra_r_r_r(dst, src, src2)) }
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inst_evdotphssmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphssmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphssmia_r_r_r(dst, src, src2)) }
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inst_evdotphsssia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssia_r_r_r(dst, src, src2)) }
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inst_evdotphsssfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssfra_r_r_r(dst, src, src2)) }
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inst_evdotphausiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHAUSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphausiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphausiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphassiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphasusiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASUSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasusiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasusiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphassfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassfaaw_r_r_r(dst, src, src2)) }
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inst_evdotphsssiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphsssfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssfaaw_r_r_r(dst, src, src2)) }
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inst_evdotphaumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHAUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphaumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphaumiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphasmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasmiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphasumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphasumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphasumiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphassfraaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHASSFRAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphassfraaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphassfraaw_r_r_r(dst, src, src2)) }
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inst_evdotphssmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphssmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphssmiaaw_r_r_r(dst, src, src2)) }
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inst_evdotphsssfraaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPHSSSFRAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotphsssfraaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotphsssfraaw_r_r_r(dst, src, src2)) }
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inst_evdotp4hgaumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGAUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgaumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgaumi_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasmi_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasumi_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasmf_r_r_r(dst, src, src2)) }
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inst_evdotp4hgssmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGSSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgssmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgssmi_r_r_r(dst, src, src2)) }
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inst_evdotp4hgssmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGSSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgssmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgssmf_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgasmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGASMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgasmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgasmi_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgasmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGASMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgasmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgasmf_r_r_r(dst, src, src2)) }
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inst_evdotpbaumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBAUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbaumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbaumi_r_r_r(dst, src, src2)) }
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inst_evdotpbasmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBASMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbasmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbasmi_r_r_r(dst, src, src2)) }
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inst_evdotpbasumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBASUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbasumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbasumi_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgssmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGSSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgssmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgssmi_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgssmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGSSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgssmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgssmf_r_r_r(dst, src, src2)) }
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inst_evdotp4hgaumiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGAUMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgaumiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgaumiaa3_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasmiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasmiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasmiaa3_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasumiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASUMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasumiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasumiaa3_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasmfaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASMFAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasmfaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasmfaa3_r_r_r(dst, src, src2)) }
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inst_evdotp4hgssmiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGSSMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgssmiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgssmiaa3_r_r_r(dst, src, src2)) }
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inst_evdotp4hgssmfaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGSSMFAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgssmfaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgssmfaa3_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgasmiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGASMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgasmiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgasmiaa3_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgasmfaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGASMFAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgasmfaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgasmfaa3_r_r_r(dst, src, src2)) }
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inst_evdotpbaumiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBAUMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbaumiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbaumiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotpbasmiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBASMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbasmiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbasmiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotpbasumiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBASUMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbasumiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbasumiaaw3_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgssmiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGSSMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgssmiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgssmiaa3_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgssmfaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGSSMFAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgssmfaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgssmfaa3_r_r_r(dst, src, src2)) }
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inst_evdotp4hgaumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGAUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgaumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgaumia_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasmia_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasumia_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasmfa_r_r_r(dst, src, src2)) }
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inst_evdotp4hgssmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGSSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgssmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgssmia_r_r_r(dst, src, src2)) }
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inst_evdotp4hgssmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGSSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgssmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgssmfa_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgasmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGASMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgasmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgasmia_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgasmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGASMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgasmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgasmfa_r_r_r(dst, src, src2)) }
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inst_evdotpbaumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBAUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbaumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbaumia_r_r_r(dst, src, src2)) }
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inst_evdotpbasmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBASMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbasmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbasmia_r_r_r(dst, src, src2)) }
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inst_evdotpbasumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBASUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbasumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbasumia_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgssmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGSSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgssmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgssmia_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgssmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGSSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgssmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgssmfa_r_r_r(dst, src, src2)) }
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inst_evdotp4hgaumiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGAUMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgaumiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgaumiaa_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasmiaa_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasumiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASUMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasumiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasumiaa_r_r_r(dst, src, src2)) }
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inst_evdotp4hgasmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGASMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgasmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgasmfaa_r_r_r(dst, src, src2)) }
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inst_evdotp4hgssmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGSSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgssmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgssmiaa_r_r_r(dst, src, src2)) }
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inst_evdotp4hgssmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HGSSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hgssmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hgssmfaa_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgasmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGASMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgasmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgasmiaa_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgasmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGASMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgasmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgasmfaa_r_r_r(dst, src, src2)) }
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inst_evdotpbaumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBAUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbaumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbaumiaaw_r_r_r(dst, src, src2)) }
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inst_evdotpbasmiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBASMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbasmiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbasmiaaw_r_r_r(dst, src, src2)) }
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inst_evdotpbasumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPBASUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpbasumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpbasumiaaw_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgssmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGSSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgssmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgssmiaa_r_r_r(dst, src, src2)) }
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inst_evdotp4hxgssmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTP4HXGSSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotp4hxgssmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotp4hxgssmfaa_r_r_r(dst, src, src2)) }
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inst_evdotpwausi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWAUSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwausi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwausi_r_r_r(dst, src, src2)) }
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inst_evdotpwassi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwassi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwassi_r_r_r(dst, src, src2)) }
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inst_evdotpwasusi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASUSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasusi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasusi_r_r_r(dst, src, src2)) }
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inst_evdotpwaumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWAUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwaumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwaumi_r_r_r(dst, src, src2)) }
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inst_evdotpwasmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasmi_r_r_r(dst, src, src2)) }
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inst_evdotpwasumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasumi_r_r_r(dst, src, src2)) }
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inst_evdotpwssmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWSSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwssmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwssmi_r_r_r(dst, src, src2)) }
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inst_evdotpwsssi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWSSSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwsssi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwsssi_r_r_r(dst, src, src2)) }
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inst_evdotpwausiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWAUSIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwausiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwausiaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwassiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASSIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwassiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwassiaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwasusiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASUSIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasusiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasusiaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwsssiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWSSSIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwsssiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwsssiaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwaumiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWAUMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwaumiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwaumiaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwasmiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasmiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasmiaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwasumiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASUMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasumiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasumiaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwssmiaa3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWSSMIAA3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwssmiaa3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwssmiaa3_r_r_r(dst, src, src2)) }
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inst_evdotpwausia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWAUSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwausia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwausia_r_r_r(dst, src, src2)) }
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inst_evdotpwassia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwassia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwassia_r_r_r(dst, src, src2)) }
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inst_evdotpwasusia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASUSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasusia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasusia_r_r_r(dst, src, src2)) }
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inst_evdotpwaumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWAUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwaumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwaumia_r_r_r(dst, src, src2)) }
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inst_evdotpwasmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasmia_r_r_r(dst, src, src2)) }
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inst_evdotpwasumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasumia_r_r_r(dst, src, src2)) }
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inst_evdotpwssmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWSSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwssmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwssmia_r_r_r(dst, src, src2)) }
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inst_evdotpwsssia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWSSSIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwsssia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwsssia_r_r_r(dst, src, src2)) }
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inst_evdotpwausiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWAUSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwausiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwausiaa_r_r_r(dst, src, src2)) }
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inst_evdotpwassiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwassiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwassiaa_r_r_r(dst, src, src2)) }
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inst_evdotpwasusiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASUSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasusiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasusiaa_r_r_r(dst, src, src2)) }
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inst_evdotpwsssiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWSSSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwsssiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwsssiaa_r_r_r(dst, src, src2)) }
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inst_evdotpwaumiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWAUMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwaumiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwaumiaa_r_r_r(dst, src, src2)) }
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inst_evdotpwasmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasmiaa_r_r_r(dst, src, src2)) }
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inst_evdotpwasumiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWASUMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwasumiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwasumiaa_r_r_r(dst, src, src2)) }
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inst_evdotpwssmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDOTPWSSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdotpwssmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdotpwssmiaa_r_r_r(dst, src, src2)) }
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inst_evaddib_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDIB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddib_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddib_r_r_r(dst, src, src2)) }
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inst_evaddih_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDIH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddih_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddih_r_r_r(dst, src, src2)) }
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inst_evsubifh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBIFH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubifh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubifh_r_r_r(dst, src, src2)) }
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inst_evsubifb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBIFB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubifb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubifb_r_r_r(dst, src, src2)) }
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inst_evabsb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsb_r_r_r(dst, src, src2)) }
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inst_evabsh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsh_r_r_r(dst, src, src2)) }
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inst_evabsd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsd_r_r_r(dst, src, src2)) }
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inst_evabss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabss_r_r_r(dst, src, src2)) }
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inst_evabsbs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsbs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsbs_r_r_r(dst, src, src2)) }
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inst_evabshs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabshs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabshs_r_r_r(dst, src, src2)) }
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inst_evabsds_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsds_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsds_r_r_r(dst, src, src2)) }
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inst_evnegwo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGWO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegwo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegwo_r_r_r(dst, src, src2)) }
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inst_evnegb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegb_r_r_r(dst, src, src2)) }
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inst_evnegbo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGBO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegbo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegbo_r_r_r(dst, src, src2)) }
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inst_evnegh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegh_r_r_r(dst, src, src2)) }
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inst_evnegho_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGHO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegho_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegho_r_r_r(dst, src, src2)) }
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inst_evnegd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegd_r_r_r(dst, src, src2)) }
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inst_evnegs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegs_r_r_r(dst, src, src2)) }
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inst_evnegwos_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGWOS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegwos_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegwos_r_r_r(dst, src, src2)) }
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inst_evnegbs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegbs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegbs_r_r_r(dst, src, src2)) }
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inst_evnegbos_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGBOS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegbos_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegbos_r_r_r(dst, src, src2)) }
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inst_evneghs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evneghs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evneghs_r_r_r(dst, src, src2)) }
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inst_evneghos_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGHOS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evneghos_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evneghos_r_r_r(dst, src, src2)) }
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inst_evnegds_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVNEGDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evnegds_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evnegds_r_r_r(dst, src, src2)) }
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inst_evextzb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVEXTZB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evextzb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evextzb_r_r_r(dst, src, src2)) }
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inst_evextsbh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVEXTSBH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evextsbh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evextsbh_r_r_r(dst, src, src2)) }
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inst_evextsw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVEXTSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evextsw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evextsw_r_r_r(dst, src, src2)) }
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inst_evrndwh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDWH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndwh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndwh_r_r_r(dst, src, src2)) }
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inst_evrndhb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDHB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndhb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndhb_r_r_r(dst, src, src2)) }
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inst_evrnddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDDW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrnddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrnddw_r_r_r(dst, src, src2)) }
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inst_evrndwhus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDWHUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndwhus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndwhus_r_r_r(dst, src, src2)) }
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inst_evrndwhss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDWHSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndwhss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndwhss_r_r_r(dst, src, src2)) }
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inst_evrndhbus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDHBUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndhbus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndhbus_r_r_r(dst, src, src2)) }
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inst_evrndhbss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDHBSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndhbss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndhbss_r_r_r(dst, src, src2)) }
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inst_evrnddwus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDDWUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrnddwus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrnddwus_r_r_r(dst, src, src2)) }
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inst_evrnddwss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDDWSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrnddwss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrnddwss_r_r_r(dst, src, src2)) }
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inst_evrndwnh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDWNH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndwnh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndwnh_r_r_r(dst, src, src2)) }
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inst_evrndhnb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDHNB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndhnb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndhnb_r_r_r(dst, src, src2)) }
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inst_evrnddnw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDDNW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrnddnw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrnddnw_r_r_r(dst, src, src2)) }
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inst_evrndwnhus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDWNHUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndwnhus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndwnhus_r_r_r(dst, src, src2)) }
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inst_evrndwnhss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDWNHSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndwnhss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndwnhss_r_r_r(dst, src, src2)) }
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inst_evrndhnbus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDHNBUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndhnbus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndhnbus_r_r_r(dst, src, src2)) }
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inst_evrndhnbss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDHNBSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrndhnbss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrndhnbss_r_r_r(dst, src, src2)) }
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inst_evrnddnwus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDDNWUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrnddnwus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrnddnwus_r_r_r(dst, src, src2)) }
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inst_evrnddnwss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRNDDNWSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrnddnwss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrnddnwss_r_r_r(dst, src, src2)) }
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inst_evcntlzh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCNTLZH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcntlzh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcntlzh_r_r_r(dst, src, src2)) }
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inst_evcntlsh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCNTLSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcntlsh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcntlsh_r_r_r(dst, src, src2)) }
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inst_evpopcntb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPOPCNTB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpopcntb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpopcntb_r_r_r(dst, src, src2)) }
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inst_circinc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CIRCINC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_circinc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_circinc_r_r_r(dst, src, src2)) }
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inst_evunpkhibui_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKHIBUI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpkhibui_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpkhibui_r_r_r(dst, src, src2)) }
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inst_evunpkhibsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKHIBSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpkhibsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpkhibsi_r_r_r(dst, src, src2)) }
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inst_evunpkhihui_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKHIHUI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpkhihui_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpkhihui_r_r_r(dst, src, src2)) }
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inst_evunpkhihsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKHIHSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpkhihsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpkhihsi_r_r_r(dst, src, src2)) }
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inst_evunpklobui_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKLOBUI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpklobui_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpklobui_r_r_r(dst, src, src2)) }
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inst_evunpklobsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKLOBSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpklobsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpklobsi_r_r_r(dst, src, src2)) }
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inst_evunpklohui_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKLOHUI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpklohui_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpklohui_r_r_r(dst, src, src2)) }
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inst_evunpklohsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKLOHSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpklohsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpklohsi_r_r_r(dst, src, src2)) }
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inst_evunpklohf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKLOHF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpklohf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpklohf_r_r_r(dst, src, src2)) }
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inst_evunpkhihf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKHIHF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpkhihf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpkhihf_r_r_r(dst, src, src2)) }
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inst_evunpklowgsf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKLOWGSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpklowgsf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpklowgsf_r_r_r(dst, src, src2)) }
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inst_evunpkhiwgsf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVUNPKHIWGSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evunpkhiwgsf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evunpkhiwgsf_r_r_r(dst, src, src2)) }
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inst_evsatsduw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSDUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatsduw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatsduw_r_r_r(dst, src, src2)) }
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inst_evsatsdsw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSDSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatsdsw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatsdsw_r_r_r(dst, src, src2)) }
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inst_evsatshub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSHUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatshub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatshub_r_r_r(dst, src, src2)) }
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inst_evsatshsb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSHSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatshsb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatshsb_r_r_r(dst, src, src2)) }
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inst_evsatuwuh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATUWUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatuwuh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatuwuh_r_r_r(dst, src, src2)) }
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inst_evsatswsh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSWSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatswsh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatswsh_r_r_r(dst, src, src2)) }
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inst_evsatswuh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSWUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatswuh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatswuh_r_r_r(dst, src, src2)) }
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inst_evsatuhub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATUHUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatuhub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatuhub_r_r_r(dst, src, src2)) }
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inst_evsatuduw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATUDUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatuduw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatuduw_r_r_r(dst, src, src2)) }
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inst_evsatuwsw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATUWSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatuwsw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatuwsw_r_r_r(dst, src, src2)) }
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inst_evsatshuh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSHUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatshuh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatshuh_r_r_r(dst, src, src2)) }
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inst_evsatuhsh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATUHSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatuhsh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatuhsh_r_r_r(dst, src, src2)) }
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inst_evsatswuw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSWUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatswuw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatswuw_r_r_r(dst, src, src2)) }
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inst_evsatswgsdf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSWGSDF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatswgsdf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatswgsdf_r_r_r(dst, src, src2)) }
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inst_evsatsbub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATSBUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatsbub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatsbub_r_r_r(dst, src, src2)) }
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inst_evsatubsb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSATUBSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsatubsb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsatubsb_r_r_r(dst, src, src2)) }
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inst_evmaxhpuw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXHPUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxhpuw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxhpuw_r_r_r(dst, src, src2)) }
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inst_evmaxhpsw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXHPSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxhpsw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxhpsw_r_r_r(dst, src, src2)) }
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inst_evmaxbpuh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXBPUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxbpuh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxbpuh_r_r_r(dst, src, src2)) }
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inst_evmaxbpsh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXBPSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxbpsh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxbpsh_r_r_r(dst, src, src2)) }
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inst_evmaxwpud_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXWPUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxwpud_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxwpud_r_r_r(dst, src, src2)) }
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inst_evmaxwpsd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXWPSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxwpsd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxwpsd_r_r_r(dst, src, src2)) }
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inst_evminhpuw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINHPUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminhpuw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminhpuw_r_r_r(dst, src, src2)) }
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inst_evminhpsw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINHPSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminhpsw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminhpsw_r_r_r(dst, src, src2)) }
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inst_evminbpuh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINBPUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminbpuh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminbpuh_r_r_r(dst, src, src2)) }
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inst_evminbpsh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINBPSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminbpsh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminbpsh_r_r_r(dst, src, src2)) }
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inst_evminwpud_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINWPUD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminwpud_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminwpud_r_r_r(dst, src, src2)) }
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inst_evminwpsd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINWPSD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminwpsd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminwpsd_r_r_r(dst, src, src2)) }
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inst_evmaxmagws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXMAGWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxmagws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxmagws_r_r_r(dst, src, src2)) }
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inst_evsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsl_r_r_r(dst, src, src2)) }
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inst_evsli_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSLI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsli_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsli_r_r_r(dst, src, src2)) }
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inst_evsplatie_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatie_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatie_r_r_r(dst, src, src2)) }
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inst_evsplatib_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatib_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatib_r_r_r(dst, src, src2)) }
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inst_evsplatibe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIBE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatibe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatibe_r_r_r(dst, src, src2)) }
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inst_evsplatih_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatih_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatih_r_r_r(dst, src, src2)) }
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inst_evsplatihe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIHE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatihe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatihe_r_r_r(dst, src, src2)) }
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inst_evsplatid_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATID, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatid_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatid_r_r_r(dst, src, src2)) }
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inst_evsplatia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatia_r_r_r(dst, src, src2)) }
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inst_evsplatiea_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIEA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatiea_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatiea_r_r_r(dst, src, src2)) }
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inst_evsplatiba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIBA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatiba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatiba_r_r_r(dst, src, src2)) }
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inst_evsplatibea_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIBEA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatibea_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatibea_r_r_r(dst, src, src2)) }
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inst_evsplatiha_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIHA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatiha_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatiha_r_r_r(dst, src, src2)) }
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inst_evsplatihea_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIHEA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatihea_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatihea_r_r_r(dst, src, src2)) }
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inst_evsplatida_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATIDA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatida_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatida_r_r_r(dst, src, src2)) }
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inst_evsplatfio_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfio_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfio_r_r_r(dst, src, src2)) }
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inst_evsplatfib_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfib_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfib_r_r_r(dst, src, src2)) }
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inst_evsplatfibo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIBO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfibo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfibo_r_r_r(dst, src, src2)) }
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inst_evsplatfih_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfih_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfih_r_r_r(dst, src, src2)) }
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inst_evsplatfiho_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIHO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfiho_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfiho_r_r_r(dst, src, src2)) }
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inst_evsplatfid_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFID, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfid_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfid_r_r_r(dst, src, src2)) }
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inst_evsplatfia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfia_r_r_r(dst, src, src2)) }
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inst_evsplatfioa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIOA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfioa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfioa_r_r_r(dst, src, src2)) }
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inst_evsplatfiba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIBA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfiba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfiba_r_r_r(dst, src, src2)) }
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inst_evsplatfiboa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIBOA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfiboa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfiboa_r_r_r(dst, src, src2)) }
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inst_evsplatfiha_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIHA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfiha_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfiha_r_r_r(dst, src, src2)) }
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inst_evsplatfihoa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIHOA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfihoa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfihoa_r_r_r(dst, src, src2)) }
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inst_evsplatfida_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATFIDA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatfida_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatfida_r_r_r(dst, src, src2)) }
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inst_evcmpgtdu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPGTDU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmpgtdu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmpgtdu_r_r_r(dst, src, src2)) }
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inst_evcmpgtds_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPGTDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmpgtds_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmpgtds_r_r_r(dst, src, src2)) }
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inst_evcmpltdu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPLTDU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmpltdu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmpltdu_r_r_r(dst, src, src2)) }
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inst_evcmpltds_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPLTDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmpltds_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmpltds_r_r_r(dst, src, src2)) }
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inst_evcmpeqd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCMPEQD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evcmpeqd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evcmpeqd_r_r_r(dst, src, src2)) }
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inst_evswapbhilo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSWAPBHILO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evswapbhilo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evswapbhilo_r_r_r(dst, src, src2)) }
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inst_evswapblohi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSWAPBLOHI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evswapblohi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evswapblohi_r_r_r(dst, src, src2)) }
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inst_evswaphhilo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSWAPHHILO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evswaphhilo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evswaphhilo_r_r_r(dst, src, src2)) }
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inst_evswaphlohi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSWAPHLOHI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evswaphlohi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evswaphlohi_r_r_r(dst, src, src2)) }
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inst_evswaphe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSWAPHE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evswaphe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evswaphe_r_r_r(dst, src, src2)) }
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inst_evswaphhi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSWAPHHI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evswaphhi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evswaphhi_r_r_r(dst, src, src2)) }
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inst_evswaphlo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSWAPHLO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evswaphlo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evswaphlo_r_r_r(dst, src, src2)) }
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inst_evswapho_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSWAPHO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evswapho_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evswapho_r_r_r(dst, src, src2)) }
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inst_evinsb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVINSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evinsb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evinsb_r_r_r(dst, src, src2)) }
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inst_evxtrb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVXTRB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evxtrb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evxtrb_r_r_r(dst, src, src2)) }
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inst_evsplath_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplath_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplath_r_r_r(dst, src, src2)) }
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inst_evsplatb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSPLATB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsplatb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsplatb_r_r_r(dst, src, src2)) }
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inst_evinsh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVINSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evinsh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evinsh_r_r_r(dst, src, src2)) }
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inst_evclrbe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCLRBE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evclrbe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evclrbe_r_r_r(dst, src, src2)) }
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inst_evclrbo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCLRBO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evclrbo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evclrbo_r_r_r(dst, src, src2)) }
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inst_evclrh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVCLRH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evclrh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evclrh_r_r_r(dst, src, src2)) }
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inst_evxtrh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVXTRH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evxtrh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evxtrh_r_r_r(dst, src, src2)) }
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inst_evselbitm0_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSELBITM0, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evselbitm0_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evselbitm0_r_r_r(dst, src, src2)) }
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inst_evselbitm1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSELBITM1, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evselbitm1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evselbitm1_r_r_r(dst, src, src2)) }
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inst_evselbit_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSELBIT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evselbit_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evselbit_r_r_r(dst, src, src2)) }
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inst_evperm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPERM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evperm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evperm_r_r_r(dst, src, src2)) }
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inst_evperm2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPERM2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evperm2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evperm2_r_r_r(dst, src, src2)) }
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inst_evperm3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPERM3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evperm3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evperm3_r_r_r(dst, src, src2)) }
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inst_evxtrd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVXTRD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evxtrd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evxtrd_r_r_r(dst, src, src2)) }
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inst_evsrbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrbu_r_r_r(dst, src, src2)) }
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inst_evsrbs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrbs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrbs_r_r_r(dst, src, src2)) }
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inst_evsrbiu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRBIU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrbiu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrbiu_r_r_r(dst, src, src2)) }
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inst_evsrbis_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRBIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrbis_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrbis_r_r_r(dst, src, src2)) }
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inst_evslb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSLB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evslb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evslb_r_r_r(dst, src, src2)) }
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inst_evrlb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRLB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrlb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrlb_r_r_r(dst, src, src2)) }
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inst_evslbi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSLBI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evslbi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evslbi_r_r_r(dst, src, src2)) }
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inst_evrlbi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRLBI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrlbi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrlbi_r_r_r(dst, src, src2)) }
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inst_evsrhu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRHU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrhu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrhu_r_r_r(dst, src, src2)) }
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inst_evsrhs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrhs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrhs_r_r_r(dst, src, src2)) }
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inst_evsrhiu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRHIU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrhiu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrhiu_r_r_r(dst, src, src2)) }
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inst_evsrhis_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRHIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrhis_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrhis_r_r_r(dst, src, src2)) }
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inst_evslh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSLH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evslh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evslh_r_r_r(dst, src, src2)) }
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inst_evrlh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRLH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrlh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrlh_r_r_r(dst, src, src2)) }
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inst_evslhi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSLHI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evslhi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evslhi_r_r_r(dst, src, src2)) }
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inst_evrlhi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVRLHI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evrlhi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evrlhi_r_r_r(dst, src, src2)) }
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inst_evsru_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsru_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsru_r_r_r(dst, src, src2)) }
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inst_evsrs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrs_r_r_r(dst, src, src2)) }
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inst_evsriu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRIU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsriu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsriu_r_r_r(dst, src, src2)) }
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inst_evsris_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSRIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsris_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsris_r_r_r(dst, src, src2)) }
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inst_evlvsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLVSL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlvsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlvsl_r_r_r(dst, src, src2)) }
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inst_evlvsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLVSR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlvsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlvsr_r_r_r(dst, src, src2)) }
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inst_evsroiu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSROIU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsroiu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsroiu_r_r_r(dst, src, src2)) }
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inst_evsrois_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSROIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsrois_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsrois_r_r_r(dst, src, src2)) }
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inst_evsloi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSLOI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsloi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsloi_r_r_r(dst, src, src2)) }
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inst_evldbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldbx_r_r_r(dst, src, src2)) }
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inst_evldb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldb_r_r_r(dst, src, src2)) }
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inst_evlhhsplathx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHSPLATHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhsplathx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhsplathx_r_r_r(dst, src, src2)) }
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inst_evlhhsplath_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHSPLATH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhsplath_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhsplath_r_r_r(dst, src, src2)) }
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inst_evlwbsplatwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBSPLATWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbsplatwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbsplatwx_r_r_r(dst, src, src2)) }
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inst_evlwbsplatw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBSPLATW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbsplatw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbsplatw_r_r_r(dst, src, src2)) }
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inst_evlwhsplatwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHSPLATWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhsplatwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhsplatwx_r_r_r(dst, src, src2)) }
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inst_evlwhsplatw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHSPLATW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhsplatw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhsplatw_r_r_r(dst, src, src2)) }
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inst_evlbbsplatbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLBBSPLATBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlbbsplatbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlbbsplatbx_r_r_r(dst, src, src2)) }
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inst_evlbbsplatb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLBBSPLATB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlbbsplatb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlbbsplatb_r_r_r(dst, src, src2)) }
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inst_evstdbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdbx_r_r_r(dst, src, src2)) }
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inst_evstdb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdb_r_r_r(dst, src, src2)) }
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inst_evlwbex_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBEX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbex_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbex_r_r_r(dst, src, src2)) }
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inst_evlwbe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbe_r_r_r(dst, src, src2)) }
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inst_evlwboux_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBOUX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwboux_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwboux_r_r_r(dst, src, src2)) }
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inst_evlwbou_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBOU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbou_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbou_r_r_r(dst, src, src2)) }
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inst_evlwbosx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBOSX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbosx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbosx_r_r_r(dst, src, src2)) }
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inst_evlwbos_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBOS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbos_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbos_r_r_r(dst, src, src2)) }
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inst_evstwbex_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBEX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbex_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbex_r_r_r(dst, src, src2)) }
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inst_evstwbe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbe_r_r_r(dst, src, src2)) }
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inst_evstwbox_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBOX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbox_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbox_r_r_r(dst, src, src2)) }
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inst_evstwbo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbo_r_r_r(dst, src, src2)) }
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inst_evstwbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbx_r_r_r(dst, src, src2)) }
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inst_evstwb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwb_r_r_r(dst, src, src2)) }
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inst_evsthbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTHBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsthbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsthbx_r_r_r(dst, src, src2)) }
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inst_evsthb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTHB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsthb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsthb_r_r_r(dst, src, src2)) }
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inst_evlddmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDDMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlddmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlddmx_r_r_r(dst, src, src2)) }
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inst_evlddu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDDU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlddu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlddu_r_r_r(dst, src, src2)) }
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inst_evldwmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDWMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldwmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldwmx_r_r_r(dst, src, src2)) }
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inst_evldwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldwu_r_r_r(dst, src, src2)) }
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inst_evldhmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDHMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldhmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldhmx_r_r_r(dst, src, src2)) }
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inst_evldhu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDHU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldhu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldhu_r_r_r(dst, src, src2)) }
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inst_evldbmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDBMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldbmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldbmx_r_r_r(dst, src, src2)) }
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inst_evldbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evldbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evldbu_r_r_r(dst, src, src2)) }
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inst_evlhhesplatmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHESPLATMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhesplatmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhesplatmx_r_r_r(dst, src, src2)) }
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inst_evlhhesplatu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHESPLATU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhesplatu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhesplatu_r_r_r(dst, src, src2)) }
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inst_evlhhsplathmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHSPLATHMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhsplathmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhsplathmx_r_r_r(dst, src, src2)) }
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inst_evlhhsplathu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHSPLATHU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhsplathu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhsplathu_r_r_r(dst, src, src2)) }
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inst_evlhhousplatmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHOUSPLATMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhousplatmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhousplatmx_r_r_r(dst, src, src2)) }
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inst_evlhhousplatu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHOUSPLATU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhousplatu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhousplatu_r_r_r(dst, src, src2)) }
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inst_evlhhossplatmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHOSSPLATMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhossplatmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhossplatmx_r_r_r(dst, src, src2)) }
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inst_evlhhossplatu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLHHOSSPLATU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlhhossplatu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlhhossplatu_r_r_r(dst, src, src2)) }
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inst_evlwhemx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHEMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhemx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhemx_r_r_r(dst, src, src2)) }
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inst_evlwheu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHEU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwheu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwheu_r_r_r(dst, src, src2)) }
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inst_evlwbsplatwmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBSPLATWMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbsplatwmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbsplatwmx_r_r_r(dst, src, src2)) }
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inst_evlwbsplatwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBSPLATWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbsplatwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbsplatwu_r_r_r(dst, src, src2)) }
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inst_evlwhoumx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHOUMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhoumx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhoumx_r_r_r(dst, src, src2)) }
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inst_evlwhouu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHOUU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhouu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhouu_r_r_r(dst, src, src2)) }
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inst_evlwhosmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHOSMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhosmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhosmx_r_r_r(dst, src, src2)) }
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inst_evlwhosu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHOSU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhosu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhosu_r_r_r(dst, src, src2)) }
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inst_evlwwsplatmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWWSPLATMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwwsplatmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwwsplatmx_r_r_r(dst, src, src2)) }
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inst_evlwwsplatu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWWSPLATU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwwsplatu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwwsplatu_r_r_r(dst, src, src2)) }
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inst_evlwhsplatwmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHSPLATWMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhsplatwmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhsplatwmx_r_r_r(dst, src, src2)) }
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inst_evlwhsplatwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHSPLATWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhsplatwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhsplatwu_r_r_r(dst, src, src2)) }
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inst_evlwhsplatmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHSPLATMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhsplatmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhsplatmx_r_r_r(dst, src, src2)) }
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inst_evlwhsplatu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWHSPLATU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwhsplatu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwhsplatu_r_r_r(dst, src, src2)) }
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inst_evlbbsplatbmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLBBSPLATBMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlbbsplatbmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlbbsplatbmx_r_r_r(dst, src, src2)) }
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inst_evlbbsplatbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLBBSPLATBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlbbsplatbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlbbsplatbu_r_r_r(dst, src, src2)) }
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inst_evstddmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDDMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstddmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstddmx_r_r_r(dst, src, src2)) }
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inst_evstddu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDDU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstddu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstddu_r_r_r(dst, src, src2)) }
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inst_evstdwmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDWMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdwmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdwmx_r_r_r(dst, src, src2)) }
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inst_evstdwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdwu_r_r_r(dst, src, src2)) }
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inst_evstdhmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDHMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdhmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdhmx_r_r_r(dst, src, src2)) }
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inst_evstdhu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDHU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdhu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdhu_r_r_r(dst, src, src2)) }
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inst_evstdbmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDBMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdbmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdbmx_r_r_r(dst, src, src2)) }
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inst_evstdbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstdbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstdbu_r_r_r(dst, src, src2)) }
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inst_evlwbemx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBEMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbemx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbemx_r_r_r(dst, src, src2)) }
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inst_evlwbeu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBEU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbeu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbeu_r_r_r(dst, src, src2)) }
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inst_evlwboumx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBOUMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwboumx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwboumx_r_r_r(dst, src, src2)) }
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inst_evlwbouu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBOUU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbouu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbouu_r_r_r(dst, src, src2)) }
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inst_evlwbosmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBOSMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbosmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbosmx_r_r_r(dst, src, src2)) }
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inst_evlwbosu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLWBOSU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlwbosu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlwbosu_r_r_r(dst, src, src2)) }
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inst_evstwhemx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWHEMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwhemx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwhemx_r_r_r(dst, src, src2)) }
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inst_evstwheu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWHEU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwheu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwheu_r_r_r(dst, src, src2)) }
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inst_evstwbemx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBEMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbemx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbemx_r_r_r(dst, src, src2)) }
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inst_evstwbeu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBEU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbeu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbeu_r_r_r(dst, src, src2)) }
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inst_evstwhomx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWHOMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwhomx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwhomx_r_r_r(dst, src, src2)) }
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inst_evstwhou_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWHOU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwhou_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwhou_r_r_r(dst, src, src2)) }
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inst_evstwbomx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBOMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbomx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbomx_r_r_r(dst, src, src2)) }
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inst_evstwbou_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBOU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbou_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbou_r_r_r(dst, src, src2)) }
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inst_evstwwemx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWWEMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwwemx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwwemx_r_r_r(dst, src, src2)) }
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inst_evstwweu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWWEU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwweu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwweu_r_r_r(dst, src, src2)) }
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inst_evstwbmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbmx_r_r_r(dst, src, src2)) }
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inst_evstwbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwbu_r_r_r(dst, src, src2)) }
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inst_evstwwomx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWWOMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwwomx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwwomx_r_r_r(dst, src, src2)) }
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inst_evstwwou_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTWWOU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstwwou_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstwwou_r_r_r(dst, src, src2)) }
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inst_evsthbmx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTHBMX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsthbmx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsthbmx_r_r_r(dst, src, src2)) }
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inst_evsthbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTHBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsthbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsthbu_r_r_r(dst, src, src2)) }
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inst_evmhusi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHUSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhusi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhusi_r_r_r(dst, src, src2)) }
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inst_evmhssi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHSSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhssi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhssi_r_r_r(dst, src, src2)) }
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inst_evmhsusi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHSUSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhsusi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhsusi_r_r_r(dst, src, src2)) }
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inst_evmhssf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHSSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhssf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhssf_r_r_r(dst, src, src2)) }
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inst_evmhumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhumi_r_r_r(dst, src, src2)) }
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inst_evmhssfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHSSFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhssfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhssfr_r_r_r(dst, src, src2)) }
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inst_evmhesumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesumi_r_r_r(dst, src, src2)) }
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inst_evmhosumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosumi_r_r_r(dst, src, src2)) }
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inst_evmbeumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBEUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbeumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbeumi_r_r_r(dst, src, src2)) }
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inst_evmbesmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesmi_r_r_r(dst, src, src2)) }
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inst_evmbesumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesumi_r_r_r(dst, src, src2)) }
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inst_evmboumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmboumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmboumi_r_r_r(dst, src, src2)) }
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inst_evmbosmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosmi_r_r_r(dst, src, src2)) }
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inst_evmbosumi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSUMI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosumi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosumi_r_r_r(dst, src, src2)) }
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inst_evmhesumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesumia_r_r_r(dst, src, src2)) }
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inst_evmhosumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosumia_r_r_r(dst, src, src2)) }
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inst_evmbeumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBEUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbeumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbeumia_r_r_r(dst, src, src2)) }
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inst_evmbesmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesmia_r_r_r(dst, src, src2)) }
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inst_evmbesumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesumia_r_r_r(dst, src, src2)) }
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inst_evmboumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmboumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmboumia_r_r_r(dst, src, src2)) }
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inst_evmbosmia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosmia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosmia_r_r_r(dst, src, src2)) }
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inst_evmbosumia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSUMIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosumia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosumia_r_r_r(dst, src, src2)) }
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inst_evmwusiw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWUSIW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwusiw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwusiw_r_r_r(dst, src, src2)) }
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inst_evmwssiw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSSIW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwssiw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwssiw_r_r_r(dst, src, src2)) }
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inst_evmwhssfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfr_r_r_r(dst, src, src2)) }
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inst_evmwehgsmfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWEHGSMFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwehgsmfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwehgsmfr_r_r_r(dst, src, src2)) }
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inst_evmwehgsmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWEHGSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwehgsmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwehgsmf_r_r_r(dst, src, src2)) }
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inst_evmwohgsmfr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWOHGSMFR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwohgsmfr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwohgsmfr_r_r_r(dst, src, src2)) }
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inst_evmwohgsmf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWOHGSMF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwohgsmf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwohgsmf_r_r_r(dst, src, src2)) }
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inst_evmwhssfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfra_r_r_r(dst, src, src2)) }
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inst_evmwehgsmfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWEHGSMFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwehgsmfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwehgsmfra_r_r_r(dst, src, src2)) }
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inst_evmwehgsmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWEHGSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwehgsmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwehgsmfa_r_r_r(dst, src, src2)) }
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inst_evmwohgsmfra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWOHGSMFRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwohgsmfra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwohgsmfra_r_r_r(dst, src, src2)) }
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inst_evmwohgsmfa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWOHGSMFA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwohgsmfa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwohgsmfa_r_r_r(dst, src, src2)) }
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inst_evaddusiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDUSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddusiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddusiaa_r_r_r(dst, src, src2)) }
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inst_evaddssiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddssiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddssiaa_r_r_r(dst, src, src2)) }
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inst_evsubfusiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFUSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfusiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfusiaa_r_r_r(dst, src, src2)) }
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inst_evsubfssiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFSSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfssiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfssiaa_r_r_r(dst, src, src2)) }
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inst_evaddsmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsmiaa_r_r_r(dst, src, src2)) }
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inst_evsubfsmiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFSMIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfsmiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfsmiaa_r_r_r(dst, src, src2)) }
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inst_evaddh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddh_r_r_r(dst, src, src2)) }
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inst_evaddhss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDHSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddhss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddhss_r_r_r(dst, src, src2)) }
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inst_evsubfh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfh_r_r_r(dst, src, src2)) }
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inst_evsubfhss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFHSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfhss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfhss_r_r_r(dst, src, src2)) }
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inst_evaddhx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddhx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddhx_r_r_r(dst, src, src2)) }
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inst_evaddhxss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDHXSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddhxss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddhxss_r_r_r(dst, src, src2)) }
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inst_evsubfhx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfhx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfhx_r_r_r(dst, src, src2)) }
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inst_evsubfhxss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFHXSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfhxss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfhxss_r_r_r(dst, src, src2)) }
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inst_evaddd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddd_r_r_r(dst, src, src2)) }
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inst_evadddss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDDSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evadddss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evadddss_r_r_r(dst, src, src2)) }
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inst_evsubfd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfd_r_r_r(dst, src, src2)) }
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inst_evsubfdss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFDSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfdss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfdss_r_r_r(dst, src, src2)) }
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inst_evaddb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddb_r_r_r(dst, src, src2)) }
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inst_evaddbss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDBSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddbss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddbss_r_r_r(dst, src, src2)) }
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inst_evsubfb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfb_r_r_r(dst, src, src2)) }
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inst_evsubfbss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFBSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfbss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfbss_r_r_r(dst, src, src2)) }
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inst_evaddsubfh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSUBFH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsubfh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsubfh_r_r_r(dst, src, src2)) }
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inst_evaddsubfhss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSUBFHSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsubfhss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsubfhss_r_r_r(dst, src, src2)) }
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inst_evsubfaddh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFADDH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfaddh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfaddh_r_r_r(dst, src, src2)) }
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inst_evsubfaddhss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFADDHSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfaddhss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfaddhss_r_r_r(dst, src, src2)) }
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inst_evaddsubfhx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSUBFHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsubfhx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsubfhx_r_r_r(dst, src, src2)) }
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inst_evaddsubfhxss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSUBFHXSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsubfhxss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsubfhxss_r_r_r(dst, src, src2)) }
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inst_evsubfaddhx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFADDHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfaddhx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfaddhx_r_r_r(dst, src, src2)) }
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inst_evsubfaddhxss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFADDHXSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfaddhxss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfaddhxss_r_r_r(dst, src, src2)) }
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inst_evadddus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDDUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evadddus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evadddus_r_r_r(dst, src, src2)) }
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inst_evaddbus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDBUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddbus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddbus_r_r_r(dst, src, src2)) }
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inst_evsubfdus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFDUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfdus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfdus_r_r_r(dst, src, src2)) }
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inst_evsubfbus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFBUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfbus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfbus_r_r_r(dst, src, src2)) }
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inst_evaddwus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDWUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddwus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddwus_r_r_r(dst, src, src2)) }
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inst_evaddwxus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDWXUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddwxus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddwxus_r_r_r(dst, src, src2)) }
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inst_evsubfwus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFWUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfwus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfwus_r_r_r(dst, src, src2)) }
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inst_evsubfwxus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFWXUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfwxus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfwxus_r_r_r(dst, src, src2)) }
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inst_evadd2subf2h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADD2SUBF2H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evadd2subf2h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evadd2subf2h_r_r_r(dst, src, src2)) }
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inst_evadd2subf2hss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADD2SUBF2HSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evadd2subf2hss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evadd2subf2hss_r_r_r(dst, src, src2)) }
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inst_evsubf2add2h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBF2ADD2H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubf2add2h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubf2add2h_r_r_r(dst, src, src2)) }
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inst_evsubf2add2hss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBF2ADD2HSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubf2add2hss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubf2add2hss_r_r_r(dst, src, src2)) }
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inst_evaddhus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDHUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddhus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddhus_r_r_r(dst, src, src2)) }
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inst_evaddhxus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDHXUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddhxus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddhxus_r_r_r(dst, src, src2)) }
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inst_evsubfhus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFHUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfhus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfhus_r_r_r(dst, src, src2)) }
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inst_evsubfhxus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFHXUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfhxus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfhxus_r_r_r(dst, src, src2)) }
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inst_evaddwss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDWSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddwss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddwss_r_r_r(dst, src, src2)) }
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inst_evsubfwss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFWSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfwss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfwss_r_r_r(dst, src, src2)) }
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inst_evaddwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddwx_r_r_r(dst, src, src2)) }
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inst_evaddwxss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDWXSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddwxss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddwxss_r_r_r(dst, src, src2)) }
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inst_evsubfwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfwx_r_r_r(dst, src, src2)) }
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inst_evsubfwxss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFWXSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfwxss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfwxss_r_r_r(dst, src, src2)) }
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inst_evaddsubfw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSUBFW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsubfw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsubfw_r_r_r(dst, src, src2)) }
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inst_evaddsubfwss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSUBFWSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsubfwss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsubfwss_r_r_r(dst, src, src2)) }
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inst_evsubfaddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFADDW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfaddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfaddw_r_r_r(dst, src, src2)) }
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inst_evsubfaddwss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFADDWSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfaddwss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfaddwss_r_r_r(dst, src, src2)) }
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inst_evaddsubfwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSUBFWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsubfwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsubfwx_r_r_r(dst, src, src2)) }
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inst_evaddsubfwxss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDSUBFWXSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddsubfwxss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddsubfwxss_r_r_r(dst, src, src2)) }
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inst_evsubfaddwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFADDWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfaddwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfaddwx_r_r_r(dst, src, src2)) }
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inst_evsubfaddwxss_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFADDWXSS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfaddwxss_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfaddwxss_r_r_r(dst, src, src2)) }
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inst_evmar_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmar_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmar_r_r_r(dst, src, src2)) }
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inst_evsumwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUMWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsumwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsumwu_r_r_r(dst, src, src2)) }
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inst_evsumws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUMWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsumws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsumws_r_r_r(dst, src, src2)) }
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inst_evsum4bu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM4BU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum4bu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum4bu_r_r_r(dst, src, src2)) }
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inst_evsum4bs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM4BS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum4bs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum4bs_r_r_r(dst, src, src2)) }
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inst_evsum2hu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM2HU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum2hu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum2hu_r_r_r(dst, src, src2)) }
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inst_evsum2hs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM2HS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum2hs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum2hs_r_r_r(dst, src, src2)) }
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inst_evdiff2his_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDIFF2HIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdiff2his_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdiff2his_r_r_r(dst, src, src2)) }
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inst_evsum2his_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM2HIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum2his_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum2his_r_r_r(dst, src, src2)) }
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inst_evsumwua_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUMWUA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsumwua_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsumwua_r_r_r(dst, src, src2)) }
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inst_evsumwsa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUMWSA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsumwsa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsumwsa_r_r_r(dst, src, src2)) }
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inst_evsum4bua_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM4BUA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum4bua_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum4bua_r_r_r(dst, src, src2)) }
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inst_evsum4bsa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM4BSA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum4bsa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum4bsa_r_r_r(dst, src, src2)) }
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inst_evsum2hua_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM2HUA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum2hua_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum2hua_r_r_r(dst, src, src2)) }
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inst_evsum2hsa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM2HSA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum2hsa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum2hsa_r_r_r(dst, src, src2)) }
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inst_evdiff2hisa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDIFF2HISA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdiff2hisa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdiff2hisa_r_r_r(dst, src, src2)) }
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inst_evsum2hisa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM2HISA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum2hisa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum2hisa_r_r_r(dst, src, src2)) }
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inst_evsumwuaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUMWUAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsumwuaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsumwuaa_r_r_r(dst, src, src2)) }
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inst_evsumwsaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUMWSAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsumwsaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsumwsaa_r_r_r(dst, src, src2)) }
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inst_evsum4buaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM4BUAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum4buaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum4buaaw_r_r_r(dst, src, src2)) }
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inst_evsum4bsaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM4BSAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum4bsaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum4bsaaw_r_r_r(dst, src, src2)) }
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inst_evsum2huaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM2HUAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum2huaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum2huaaw_r_r_r(dst, src, src2)) }
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inst_evsum2hsaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM2HSAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum2hsaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum2hsaaw_r_r_r(dst, src, src2)) }
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inst_evdiff2hisaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDIFF2HISAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdiff2hisaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdiff2hisaaw_r_r_r(dst, src, src2)) }
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inst_evsum2hisaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUM2HISAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsum2hisaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsum2hisaaw_r_r_r(dst, src, src2)) }
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inst_evdivwsf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDIVWSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdivwsf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdivwsf_r_r_r(dst, src, src2)) }
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inst_evdivwuf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDIVWUF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdivwuf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdivwuf_r_r_r(dst, src, src2)) }
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inst_evdivs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDIVS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdivs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdivs_r_r_r(dst, src, src2)) }
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inst_evdivu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDIVU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdivu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdivu_r_r_r(dst, src, src2)) }
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inst_evaddwegsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDWEGSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddwegsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddwegsi_r_r_r(dst, src, src2)) }
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inst_evaddwegsf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDWEGSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddwegsf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddwegsf_r_r_r(dst, src, src2)) }
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inst_evsubfwegsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFWEGSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfwegsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfwegsi_r_r_r(dst, src, src2)) }
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inst_evsubfwegsf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFWEGSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfwegsf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfwegsf_r_r_r(dst, src, src2)) }
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inst_evaddwogsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDWOGSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddwogsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddwogsi_r_r_r(dst, src, src2)) }
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inst_evaddwogsf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDWOGSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddwogsf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddwogsf_r_r_r(dst, src, src2)) }
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inst_evsubfwogsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFWOGSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfwogsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfwogsi_r_r_r(dst, src, src2)) }
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inst_evsubfwogsf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFWOGSF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfwogsf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfwogsf_r_r_r(dst, src, src2)) }
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inst_evaddhhiuw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDHHIUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddhhiuw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddhhiuw_r_r_r(dst, src, src2)) }
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inst_evaddhhisw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDHHISW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddhhisw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddhhisw_r_r_r(dst, src, src2)) }
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inst_evsubfhhiuw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFHHIUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfhhiuw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfhhiuw_r_r_r(dst, src, src2)) }
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inst_evsubfhhisw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFHHISW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfhhisw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfhhisw_r_r_r(dst, src, src2)) }
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inst_evaddhlouw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDHLOUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddhlouw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddhlouw_r_r_r(dst, src, src2)) }
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inst_evaddhlosw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVADDHLOSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evaddhlosw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evaddhlosw_r_r_r(dst, src, src2)) }
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inst_evsubfhlouw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFHLOUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfhlouw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfhlouw_r_r_r(dst, src, src2)) }
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inst_evsubfhlosw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSUBFHLOSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsubfhlosw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsubfhlosw_r_r_r(dst, src, src2)) }
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inst_evmhesusiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESUSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesusiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesusiaaw_r_r_r(dst, src, src2)) }
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inst_evmhosusiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSUSIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosusiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosusiaaw_r_r_r(dst, src, src2)) }
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inst_evmhesumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesumiaaw_r_r_r(dst, src, src2)) }
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inst_evmhosumiaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSUMIAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosumiaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosumiaaw_r_r_r(dst, src, src2)) }
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inst_evmbeusiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBEUSIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbeusiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbeusiaah_r_r_r(dst, src, src2)) }
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inst_evmbessiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESSIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbessiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbessiaah_r_r_r(dst, src, src2)) }
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inst_evmbesusiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESUSIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesusiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesusiaah_r_r_r(dst, src, src2)) }
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inst_evmbousiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOUSIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbousiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbousiaah_r_r_r(dst, src, src2)) }
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inst_evmbossiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSSIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbossiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbossiaah_r_r_r(dst, src, src2)) }
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inst_evmbosusiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSUSIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosusiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosusiaah_r_r_r(dst, src, src2)) }
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inst_evmbeumiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBEUMIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbeumiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbeumiaah_r_r_r(dst, src, src2)) }
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inst_evmbesmiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESMIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesmiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesmiaah_r_r_r(dst, src, src2)) }
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inst_evmbesumiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESUMIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesumiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesumiaah_r_r_r(dst, src, src2)) }
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inst_evmboumiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOUMIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmboumiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmboumiaah_r_r_r(dst, src, src2)) }
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inst_evmbosmiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSMIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosmiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosmiaah_r_r_r(dst, src, src2)) }
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inst_evmbosumiaah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSUMIAAH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosumiaah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosumiaah_r_r_r(dst, src, src2)) }
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inst_evmwlusiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUSIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlusiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlusiaaw3_r_r_r(dst, src, src2)) }
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inst_evmwlssiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSSIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlssiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlssiaaw3_r_r_r(dst, src, src2)) }
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inst_evmwhssfraaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFRAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfraaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfraaw3_r_r_r(dst, src, src2)) }
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inst_evmwhssfaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfaaw3_r_r_r(dst, src, src2)) }
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inst_evmwhssfraaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFRAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfraaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfraaw_r_r_r(dst, src, src2)) }
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inst_evmwhssfaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfaaw_r_r_r(dst, src, src2)) }
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inst_evmwlumiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlumiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlumiaaw3_r_r_r(dst, src, src2)) }
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inst_evmwlsmiaaw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSMIAAW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlsmiaaw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlsmiaaw3_r_r_r(dst, src, src2)) }
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inst_evmwusiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWUSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwusiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwusiaa_r_r_r(dst, src, src2)) }
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inst_evmwssiaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSSIAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwssiaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwssiaa_r_r_r(dst, src, src2)) }
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inst_evmwehgsmfraa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWEHGSMFRAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwehgsmfraa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwehgsmfraa_r_r_r(dst, src, src2)) }
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inst_evmwehgsmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWEHGSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwehgsmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwehgsmfaa_r_r_r(dst, src, src2)) }
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inst_evmwohgsmfraa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWOHGSMFRAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwohgsmfraa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwohgsmfraa_r_r_r(dst, src, src2)) }
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inst_evmwohgsmfaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWOHGSMFAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwohgsmfaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwohgsmfaa_r_r_r(dst, src, src2)) }
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inst_evmhesusianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESUSIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesusianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesusianw_r_r_r(dst, src, src2)) }
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inst_evmhosusianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSUSIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosusianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosusianw_r_r_r(dst, src, src2)) }
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inst_evmhesumianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHESUMIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhesumianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhesumianw_r_r_r(dst, src, src2)) }
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inst_evmhosumianw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMHOSUMIANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmhosumianw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmhosumianw_r_r_r(dst, src, src2)) }
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inst_evmbeusianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBEUSIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbeusianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbeusianh_r_r_r(dst, src, src2)) }
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inst_evmbessianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESSIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbessianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbessianh_r_r_r(dst, src, src2)) }
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inst_evmbesusianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESUSIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesusianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesusianh_r_r_r(dst, src, src2)) }
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inst_evmbousianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOUSIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbousianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbousianh_r_r_r(dst, src, src2)) }
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inst_evmbossianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSSIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbossianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbossianh_r_r_r(dst, src, src2)) }
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inst_evmbosusianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSUSIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosusianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosusianh_r_r_r(dst, src, src2)) }
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inst_evmbeumianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBEUMIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbeumianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbeumianh_r_r_r(dst, src, src2)) }
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inst_evmbesmianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESMIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesmianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesmianh_r_r_r(dst, src, src2)) }
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inst_evmbesumianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBESUMIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbesumianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbesumianh_r_r_r(dst, src, src2)) }
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inst_evmboumianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOUMIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmboumianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmboumianh_r_r_r(dst, src, src2)) }
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inst_evmbosmianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSMIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosmianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosmianh_r_r_r(dst, src, src2)) }
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inst_evmbosumianh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMBOSUMIANH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmbosumianh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmbosumianh_r_r_r(dst, src, src2)) }
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inst_evmwlusianw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUSIANW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlusianw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlusianw3_r_r_r(dst, src, src2)) }
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inst_evmwlssianw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSSIANW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlssianw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlssianw3_r_r_r(dst, src, src2)) }
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inst_evmwhssfranw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFRANW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfranw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfranw3_r_r_r(dst, src, src2)) }
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inst_evmwhssfanw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFANW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfanw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfanw3_r_r_r(dst, src, src2)) }
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inst_evmwhssfranw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFRANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfranw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfranw_r_r_r(dst, src, src2)) }
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inst_evmwhssfanw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWHSSFANW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwhssfanw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwhssfanw_r_r_r(dst, src, src2)) }
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inst_evmwlumianw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLUMIANW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlumianw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlumianw3_r_r_r(dst, src, src2)) }
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inst_evmwlsmianw3_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWLSMIANW3, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwlsmianw3_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwlsmianw3_r_r_r(dst, src, src2)) }
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inst_evmwusian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWUSIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwusian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwusian_r_r_r(dst, src, src2)) }
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inst_evmwssian_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWSSIAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwssian_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwssian_r_r_r(dst, src, src2)) }
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inst_evmwehgsmfran_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWEHGSMFRAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwehgsmfran_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwehgsmfran_r_r_r(dst, src, src2)) }
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inst_evmwehgsmfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWEHGSMFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwehgsmfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwehgsmfan_r_r_r(dst, src, src2)) }
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inst_evmwohgsmfran_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWOHGSMFRAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwohgsmfran_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwohgsmfran_r_r_r(dst, src, src2)) }
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inst_evmwohgsmfan_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMWOHGSMFAN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmwohgsmfan_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmwohgsmfan_r_r_r(dst, src, src2)) }
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inst_evseteqb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETEQB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evseteqb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evseteqb_r_r_r(dst, src, src2)) }
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inst_evseteqh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETEQH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evseteqh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evseteqh_r_r_r(dst, src, src2)) }
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inst_evseteqw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETEQW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evseteqw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evseteqw_r_r_r(dst, src, src2)) }
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inst_evsetgthu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTHU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgthu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgthu_r_r_r(dst, src, src2)) }
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inst_evsetgths_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgths_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgths_r_r_r(dst, src, src2)) }
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inst_evsetgtwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgtwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgtwu_r_r_r(dst, src, src2)) }
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inst_evsetgtws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgtws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgtws_r_r_r(dst, src, src2)) }
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inst_evsetgtbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgtbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgtbu_r_r_r(dst, src, src2)) }
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inst_evsetgtbs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgtbs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgtbs_r_r_r(dst, src, src2)) }
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inst_evsetltbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetltbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetltbu_r_r_r(dst, src, src2)) }
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inst_evsetltbs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetltbs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetltbs_r_r_r(dst, src, src2)) }
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inst_evsetlthu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTHU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetlthu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetlthu_r_r_r(dst, src, src2)) }
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inst_evsetlths_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetlths_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetlths_r_r_r(dst, src, src2)) }
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inst_evsetltwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetltwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetltwu_r_r_r(dst, src, src2)) }
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inst_evsetltws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetltws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetltws_r_r_r(dst, src, src2)) }
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inst_evsaduw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSADUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsaduw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsaduw_r_r_r(dst, src, src2)) }
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inst_evsadsw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSADSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsadsw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsadsw_r_r_r(dst, src, src2)) }
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inst_evsad4ub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD4UB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad4ub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad4ub_r_r_r(dst, src, src2)) }
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inst_evsad4sb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD4SB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad4sb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad4sb_r_r_r(dst, src, src2)) }
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inst_evsad2uh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD2UH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad2uh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad2uh_r_r_r(dst, src, src2)) }
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inst_evsad2sh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD2SH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad2sh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad2sh_r_r_r(dst, src, src2)) }
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inst_evsaduwa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSADUWA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsaduwa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsaduwa_r_r_r(dst, src, src2)) }
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inst_evsadswa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSADSWA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsadswa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsadswa_r_r_r(dst, src, src2)) }
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inst_evsad4uba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD4UBA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad4uba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad4uba_r_r_r(dst, src, src2)) }
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inst_evsad4sba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD4SBA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad4sba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad4sba_r_r_r(dst, src, src2)) }
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inst_evsad2uha_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD2UHA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad2uha_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad2uha_r_r_r(dst, src, src2)) }
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inst_evsad2sha_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD2SHA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad2sha_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad2sha_r_r_r(dst, src, src2)) }
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inst_evabsdifuw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSDIFUW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsdifuw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsdifuw_r_r_r(dst, src, src2)) }
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inst_evabsdifsw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSDIFSW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsdifsw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsdifsw_r_r_r(dst, src, src2)) }
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inst_evabsdifub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSDIFUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsdifub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsdifub_r_r_r(dst, src, src2)) }
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inst_evabsdifsb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSDIFSB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsdifsb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsdifsb_r_r_r(dst, src, src2)) }
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inst_evabsdifuh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSDIFUH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsdifuh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsdifuh_r_r_r(dst, src, src2)) }
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inst_evabsdifsh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVABSDIFSH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evabsdifsh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evabsdifsh_r_r_r(dst, src, src2)) }
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inst_evsaduwaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSADUWAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsaduwaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsaduwaa_r_r_r(dst, src, src2)) }
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inst_evsadswaa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSADSWAA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsadswaa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsadswaa_r_r_r(dst, src, src2)) }
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inst_evsad4ubaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD4UBAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad4ubaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad4ubaaw_r_r_r(dst, src, src2)) }
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inst_evsad4sbaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD4SBAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad4sbaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad4sbaaw_r_r_r(dst, src, src2)) }
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inst_evsad2uhaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD2UHAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad2uhaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad2uhaaw_r_r_r(dst, src, src2)) }
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inst_evsad2shaaw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSAD2SHAAW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsad2shaaw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsad2shaaw_r_r_r(dst, src, src2)) }
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inst_evpkshubs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSHUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkshubs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkshubs_r_r_r(dst, src, src2)) }
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inst_evpkshsbs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSHSBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkshsbs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkshsbs_r_r_r(dst, src, src2)) }
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inst_evpkswuhs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSWUHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkswuhs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkswuhs_r_r_r(dst, src, src2)) }
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inst_evpkswshs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSWSHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkswshs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkswshs_r_r_r(dst, src, src2)) }
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inst_evpkuhubs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKUHUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkuhubs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkuhubs_r_r_r(dst, src, src2)) }
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inst_evpkuwuhs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKUWUHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkuwuhs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkuwuhs_r_r_r(dst, src, src2)) }
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inst_evpkswshilvs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSWSHILVS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkswshilvs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkswshilvs_r_r_r(dst, src, src2)) }
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inst_evpkswgshefrs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSWGSHEFRS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkswgshefrs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkswgshefrs_r_r_r(dst, src, src2)) }
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inst_evpkswshfrs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSWSHFRS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkswshfrs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkswshfrs_r_r_r(dst, src, src2)) }
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inst_evpkswshilvfrs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSWSHILVFRS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkswshilvfrs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkswshilvfrs_r_r_r(dst, src, src2)) }
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inst_evpksdswfrs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSDSWFRS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpksdswfrs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpksdswfrs_r_r_r(dst, src, src2)) }
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inst_evpksdshefrs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSDSHEFRS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpksdshefrs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpksdshefrs_r_r_r(dst, src, src2)) }
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inst_evpkuduws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKUDUWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkuduws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkuduws_r_r_r(dst, src, src2)) }
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inst_evpksdsws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSDSWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpksdsws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpksdsws_r_r_r(dst, src, src2)) }
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inst_evpkswgswfrs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVPKSWGSWFRS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evpkswgswfrs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evpkswgswfrs_r_r_r(dst, src, src2)) }
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inst_evilveh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVILVEH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evilveh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evilveh_r_r_r(dst, src, src2)) }
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inst_evilveoh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVILVEOH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evilveoh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evilveoh_r_r_r(dst, src, src2)) }
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inst_evilvhih_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVILVHIH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evilvhih_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evilvhih_r_r_r(dst, src, src2)) }
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inst_evilvhiloh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVILVHILOH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evilvhiloh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evilvhiloh_r_r_r(dst, src, src2)) }
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inst_evilvloh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVILVLOH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evilvloh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evilvloh_r_r_r(dst, src, src2)) }
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inst_evilvlohih_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVILVLOHIH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evilvlohih_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evilvlohih_r_r_r(dst, src, src2)) }
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inst_evilvoeh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVILVOEH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evilvoeh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evilvoeh_r_r_r(dst, src, src2)) }
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inst_evilvoh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVILVOH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evilvoh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evilvoh_r_r_r(dst, src, src2)) }
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inst_evdlveb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDLVEB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdlveb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdlveb_r_r_r(dst, src, src2)) }
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inst_evdlveh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDLVEH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdlveh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdlveh_r_r_r(dst, src, src2)) }
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inst_evdlveob_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDLVEOB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdlveob_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdlveob_r_r_r(dst, src, src2)) }
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inst_evdlveoh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDLVEOH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdlveoh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdlveoh_r_r_r(dst, src, src2)) }
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inst_evdlvob_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDLVOB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdlvob_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdlvob_r_r_r(dst, src, src2)) }
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inst_evdlvoh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDLVOH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdlvoh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdlvoh_r_r_r(dst, src, src2)) }
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inst_evdlvoeb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDLVOEB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdlvoeb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdlvoeb_r_r_r(dst, src, src2)) }
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inst_evdlvoeh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVDLVOEH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evdlvoeh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evdlvoeh_r_r_r(dst, src, src2)) }
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inst_evmaxbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxbu_r_r_r(dst, src, src2)) }
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inst_evmaxbs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxbs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxbs_r_r_r(dst, src, src2)) }
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inst_evmaxhu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXHU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxhu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxhu_r_r_r(dst, src, src2)) }
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inst_evmaxhs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxhs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxhs_r_r_r(dst, src, src2)) }
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inst_evmaxwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxwu_r_r_r(dst, src, src2)) }
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inst_evmaxws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxws_r_r_r(dst, src, src2)) }
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inst_evmaxdu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXDU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxdu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxdu_r_r_r(dst, src, src2)) }
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inst_evmaxds_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMAXDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmaxds_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmaxds_r_r_r(dst, src, src2)) }
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inst_evminbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminbu_r_r_r(dst, src, src2)) }
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inst_evminbs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminbs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminbs_r_r_r(dst, src, src2)) }
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inst_evminhu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINHU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminhu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminhu_r_r_r(dst, src, src2)) }
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inst_evminhs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminhs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminhs_r_r_r(dst, src, src2)) }
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inst_evminwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminwu_r_r_r(dst, src, src2)) }
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inst_evminws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminws_r_r_r(dst, src, src2)) }
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inst_evmindu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINDU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evmindu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evmindu_r_r_r(dst, src, src2)) }
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inst_evminds_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVMINDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evminds_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evminds_r_r_r(dst, src, src2)) }
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inst_evavgwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgwu_r_r_r(dst, src, src2)) }
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inst_evavgws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgws_r_r_r(dst, src, src2)) }
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inst_evavgbu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGBU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgbu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgbu_r_r_r(dst, src, src2)) }
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inst_evavgbs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgbs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgbs_r_r_r(dst, src, src2)) }
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inst_evavghu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGHU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavghu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavghu_r_r_r(dst, src, src2)) }
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inst_evavghs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGHS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavghs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavghs_r_r_r(dst, src, src2)) }
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inst_evavgdu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGDU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgdu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgdu_r_r_r(dst, src, src2)) }
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inst_evavgds_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgds_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgds_r_r_r(dst, src, src2)) }
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inst_evavgwur_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGWUR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgwur_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgwur_r_r_r(dst, src, src2)) }
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inst_evavgwsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGWSR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgwsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgwsr_r_r_r(dst, src, src2)) }
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inst_evavgbur_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGBUR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgbur_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgbur_r_r_r(dst, src, src2)) }
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inst_evavgbsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGBSR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgbsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgbsr_r_r_r(dst, src, src2)) }
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inst_evavghur_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGHUR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavghur_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavghur_r_r_r(dst, src, src2)) }
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inst_evavghsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGHSR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavghsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavghsr_r_r_r(dst, src, src2)) }
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inst_evavgdur_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGDUR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgdur_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgdur_r_r_r(dst, src, src2)) }
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inst_evavgdsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVAVGDSR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evavgdsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evavgdsr_r_r_r(dst, src, src2)) }
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inst_ps_div_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_DIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_div_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_div_fr_fr_fr(dst, src, src2)) }
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inst_ps_div_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_DIV_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_div_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_div_dot_fr_fr_fr(dst, src, src2)) }
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inst_ps_sub_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_sub_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_sub_fr_fr_fr(dst, src, src2)) }
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inst_ps_sub_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_SUB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_sub_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_sub_dot_fr_fr_fr(dst, src, src2)) }
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inst_ps_add_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_add_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_add_fr_fr_fr(dst, src, src2)) }
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inst_ps_add_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_ADD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_add_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_add_dot_fr_fr_fr(dst, src, src2)) }
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inst_ps_sel_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_SEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_sel_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_sel_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_sel_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_SEL_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_sel_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_sel_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_res_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_RES, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_res_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_res_fr_fr(dst, src)) }
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inst_ps_res_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_RES_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_res_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_res_dot_fr_fr(dst, src)) }
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inst_ps_mul_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MUL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_mul_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_mul_fr_fr_fr(dst, src, src2)) }
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inst_ps_mul_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MUL_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_mul_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_mul_dot_fr_fr_fr(dst, src, src2)) }
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inst_ps_rsqrte_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_RSQRTE, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_rsqrte_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_rsqrte_fr_fr(dst, src)) }
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inst_ps_rsqrte_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_RSQRTE_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_rsqrte_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_rsqrte_dot_fr_fr(dst, src)) }
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inst_ps_msub_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_MSUB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_msub_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_msub_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_msub_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_MSUB_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_msub_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_msub_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_madd_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_MADD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_madd_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_madd_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_madd_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_MADD_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_madd_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_madd_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_nmsub_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_NMSUB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_nmsub_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_nmsub_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_nmsub_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_NMSUB_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_nmsub_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_nmsub_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_nmadd_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_NMADD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_nmadd_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_nmadd_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_nmadd_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_NMADD_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_nmadd_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_nmadd_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_sum0_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_SUM0, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_sum0_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_sum0_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_sum0_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_SUM0_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_sum0_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_sum0_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_sum1_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_SUM1, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_sum1_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_sum1_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_sum1_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_SUM1_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_sum1_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_sum1_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_muls0_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MULS0, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_muls0_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_muls0_fr_fr_fr(dst, src, src2)) }
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inst_ps_muls0_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MULS0_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_muls0_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_muls0_dot_fr_fr_fr(dst, src, src2)) }
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inst_ps_muls1_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MULS1, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_muls1_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_muls1_fr_fr_fr(dst, src, src2)) }
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inst_ps_muls1_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MULS1_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_muls1_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_muls1_dot_fr_fr_fr(dst, src, src2)) }
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inst_ps_madds0_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_MADDS0, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_madds0_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_madds0_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_madds0_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_MADDS0_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_madds0_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_madds0_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_madds1_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_MADDS1, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_madds1_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_madds1_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_madds1_dot_fr_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .PS_MADDS1_DOT, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_ps_madds1_dot_fr_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_ps_madds1_dot_fr_fr_fr_fr(dst, src, src2, src3)) }
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inst_ps_neg_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_neg_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_neg_fr_fr(dst, src)) }
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inst_ps_neg_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_NEG_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_neg_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_neg_dot_fr_fr(dst, src)) }
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inst_ps_mr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_MR, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_mr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_mr_fr_fr(dst, src)) }
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inst_ps_mr_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_MR_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_mr_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_mr_dot_fr_fr(dst, src)) }
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inst_ps_nabs_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_NABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_nabs_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_nabs_fr_fr(dst, src)) }
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inst_ps_nabs_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_NABS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_nabs_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_nabs_dot_fr_fr(dst, src)) }
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inst_ps_abs_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_ABS, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_abs_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_abs_fr_fr(dst, src)) }
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inst_ps_abs_dot_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PS_ABS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_ps_abs_dot_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ps_abs_dot_fr_fr(dst, src)) }
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inst_ps_cmpu0_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_CMPU0, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_cmpu0_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_cmpu0_crf_fr_fr(dst, src, src2)) }
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inst_ps_cmpu1_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_CMPU1, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_cmpu1_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_cmpu1_crf_fr_fr(dst, src, src2)) }
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inst_ps_cmpo0_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_CMPO0, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_cmpo0_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_cmpo0_crf_fr_fr(dst, src, src2)) }
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inst_ps_cmpo1_crf_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_CMPO1, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_cmpo1_crf_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_cmpo1_crf_fr_fr(dst, src, src2)) }
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inst_ps_merge00_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MERGE00, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_merge00_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_merge00_fr_fr_fr(dst, src, src2)) }
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inst_ps_merge00_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MERGE00_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_merge00_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_merge00_dot_fr_fr_fr(dst, src, src2)) }
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inst_ps_merge01_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MERGE01, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_merge01_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_merge01_fr_fr_fr(dst, src, src2)) }
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inst_ps_merge01_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MERGE01_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_merge01_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_merge01_dot_fr_fr_fr(dst, src, src2)) }
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inst_ps_merge10_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MERGE10, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_merge10_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_merge10_fr_fr_fr(dst, src, src2)) }
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inst_ps_merge10_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MERGE10_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_merge10_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_merge10_dot_fr_fr_fr(dst, src, src2)) }
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inst_ps_merge11_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MERGE11, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_merge11_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_merge11_fr_fr_fr(dst, src, src2)) }
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inst_ps_merge11_dot_fr_fr_fr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PS_MERGE11_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ps_merge11_dot_fr_fr_fr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ps_merge11_dot_fr_fr_fr(dst, src, src2)) }
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inst_psq_lx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSQ_LX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_psq_lx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_psq_lx_fr_mem(dst, addr)) }
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inst_psq_lux_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSQ_LUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_psq_lux_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_psq_lux_fr_mem(dst, addr)) }
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inst_psq_stx_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSQ_STX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_psq_stx_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_psq_stx_fr_mem(dst, addr)) }
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inst_psq_stux_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSQ_STUX, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_psq_stux_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_psq_stux_fr_mem(dst, addr)) }
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inst_psq_l_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSQ_L, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_psq_l_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_psq_l_fr_mem(dst, addr)) }
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inst_psq_lu_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSQ_LU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_psq_lu_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_psq_lu_fr_mem(dst, addr)) }
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inst_psq_st_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSQ_ST, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_psq_st_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_psq_st_fr_mem(dst, addr)) }
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inst_psq_stu_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .PSQ_STU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_psq_stu_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_psq_stu_fr_mem(dst, addr)) }
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inst_vaddfp128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDFP128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vaddfp128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddfp128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vsubfp128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBFP128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubfp128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubfp128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vmulfp128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULFP128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmulfp128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmulfp128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vmaddfp128_vr128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMADDFP128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmaddfp128_vr128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmaddfp128_vr128_vr128_vr128_vr128(dst, src, src2, src3)) }
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inst_vmaddcfp128_vr128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMADDCFP128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmaddcfp128_vr128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmaddcfp128_vr128_vr128_vr128_vr128(dst, src, src2, src3)) }
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inst_vnmsubfp128_vr128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VNMSUBFP128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vnmsubfp128_vr128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vnmsubfp128_vr128_vr128_vr128_vr128(dst, src, src2, src3)) }
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inst_vmsum3fp128_vr128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUM3FP128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsum3fp128_vr128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsum3fp128_vr128_vr128_vr128_vr128(dst, src, src2, src3)) }
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inst_vmsum4fp128_vr128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMSUM4FP128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vmsum4fp128_vr128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmsum4fp128_vr128_vr128_vr128_vr128(dst, src, src2, src3)) }
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inst_vmaxfp128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXFP128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmaxfp128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxfp128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vminfp128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINFP128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vminfp128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminfp128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vrefp128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREFP128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrefp128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrefp128_vr128_vr128(dst, src)) }
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inst_vrsqrtefp128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTEFP128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrsqrtefp128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrtefp128_vr128_vr128(dst, src)) }
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inst_vexptefp128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VEXPTEFP128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vexptefp128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vexptefp128_vr128_vr128(dst, src)) }
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inst_vlogefp128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VLOGEFP128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vlogefp128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vlogefp128_vr128_vr128(dst, src)) }
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inst_vand128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAND128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vand128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vand128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vandc128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VANDC128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vandc128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vandc128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vor128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VOR128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vor128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vor128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vxor128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VXOR128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vxor128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vxor128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vnor128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNOR128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vnor128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnor128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vsel128_vr128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VSEL128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vsel128_vr128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vsel128_vr128_vr128_vr128_vr128(dst, src, src2, src3)) }
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inst_vcmpeqfp128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQFP128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpeqfp128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpeqfp128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vcmpeqfp128_dot_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQFP128_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpeqfp128_dot_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpeqfp128_dot_vr128_vr128_vr128(dst, src, src2)) }
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inst_vcmpgefp128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGEFP128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgefp128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgefp128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vcmpgefp128_dot_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGEFP128_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgefp128_dot_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgefp128_dot_vr128_vr128_vr128(dst, src, src2)) }
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inst_vcmpgtfp128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTFP128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtfp128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtfp128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vcmpgtfp128_dot_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTFP128_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtfp128_dot_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtfp128_dot_vr128_vr128_vr128(dst, src, src2)) }
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inst_vcmpbfp128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPBFP128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpbfp128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpbfp128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vcmpbfp128_dot_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPBFP128_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpbfp128_dot_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpbfp128_dot_vr128_vr128_vr128(dst, src, src2)) }
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inst_vcmpequw128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUW128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequw128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequw128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vcmpequw128_dot_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUW128_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequw128_dot_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequw128_dot_vr128_vr128_vr128(dst, src, src2)) }
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inst_vrfim128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRFIM128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrfim128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrfim128_vr128_vr128(dst, src)) }
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inst_vrfin128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRFIN128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrfin128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrfin128_vr128_vr128(dst, src)) }
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inst_vrfip128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRFIP128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrfip128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrfip128_vr128_vr128(dst, src)) }
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inst_vrfiz128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRFIZ128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vrfiz128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrfiz128_vr128_vr128(dst, src)) }
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inst_vcfpsxws128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCFPSXWS128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcfpsxws128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcfpsxws128_vr128_vr128(dst, src)) }
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inst_vcfpuxws128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCFPUXWS128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcfpuxws128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcfpuxws128_vr128_vr128(dst, src)) }
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inst_vcsxwfp128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCSXWFP128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcsxwfp128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcsxwfp128_vr128_vr128(dst, src)) }
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inst_vcuxwfp128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCUXWFP128, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vcuxwfp128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcuxwfp128_vr128_vr128(dst, src)) }
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inst_vspltw128_vr128_vr128_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSPLTW128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vspltw128_vr128_vr128_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vspltw128_vr128_vr128_imm(dst, src, imm)) }
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inst_vspltisw128_vr128_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSPLTISW128, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} }
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emit_vspltisw128_vr128_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vspltisw128_vr128_imm(dst, imm)) }
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inst_vmrghw128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGHW128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrghw128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrghw128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vmrglw128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMRGLW128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmrglw128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmrglw128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vpkd3d128_vr128_vr128_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .VPKD3D128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_vpkd3d128_vr128_vr128_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_vpkd3d128_vr128_vr128_imm_imm(dst, src, imm, imm2)) }
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inst_vupkd3d128_vr128_vr128_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VUPKD3D128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vupkd3d128_vr128_vr128_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vupkd3d128_vr128_vr128_imm(dst, src, imm)) }
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inst_vperm128_vr128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VPERM128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} }
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emit_vperm128_vr128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vperm128_vr128_vr128_vr128_vr128(dst, src, src2, src3)) }
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inst_vpermwi128_vr128_vr128_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VPERMWI128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_vpermwi128_vr128_vr128_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vpermwi128_vr128_vr128_imm(dst, src, imm)) }
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inst_vrlimi128_vr128_vr128_imm_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .VRLIMI128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} }
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emit_vrlimi128_vr128_vr128_imm_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_vrlimi128_vr128_vr128_imm_imm(dst, src, imm, imm2)) }
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inst_vsldoi128_vr128_vr128_vr128_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSLDOI128, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} }
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emit_vsldoi128_vr128_vr128_vr128_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vsldoi128_vr128_vr128_vr128_imm(dst, src, src2, imm)) }
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inst_vrlw128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRLW128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vrlw128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrlw128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vslw128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSLW128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vslw128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vslw128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vsrw128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRW128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsrw128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsrw128_vr128_vr128_vr128(dst, src, src2)) }
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inst_vsraw128_vr128_vr128_vr128 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSRAW128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsraw128_vr128_vr128_vr128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsraw128_vr128_vr128_vr128(dst, src, src2)) }
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inst_lvebx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVEBX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvebx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvebx128_vr128_r_r(dst, src, src2)) }
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inst_lvehx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVEHX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvehx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvehx128_vr128_r_r(dst, src, src2)) }
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inst_lvewx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVEWX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvewx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvewx128_vr128_r_r(dst, src, src2)) }
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inst_lvx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvx128_vr128_r_r(dst, src, src2)) }
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inst_lvxl128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVXL128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvxl128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvxl128_vr128_r_r(dst, src, src2)) }
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inst_lvlx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVLX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvlx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvlx128_vr128_r_r(dst, src, src2)) }
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inst_lvrx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVRX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvrx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvrx128_vr128_r_r(dst, src, src2)) }
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inst_lvlxl128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVLXL128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvlxl128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvlxl128_vr128_r_r(dst, src, src2)) }
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inst_lvrxl128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVRXL128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvrxl128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvrxl128_vr128_r_r(dst, src, src2)) }
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inst_stvebx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVEBX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvebx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvebx128_vr128_r_r(dst, src, src2)) }
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inst_stvehx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVEHX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvehx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvehx128_vr128_r_r(dst, src, src2)) }
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inst_stvewx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVEWX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvewx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvewx128_vr128_r_r(dst, src, src2)) }
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inst_stvx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvx128_vr128_r_r(dst, src, src2)) }
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inst_stvxl128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVXL128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvxl128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvxl128_vr128_r_r(dst, src, src2)) }
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inst_stvlx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVLX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvlx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvlx128_vr128_r_r(dst, src, src2)) }
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inst_stvrx128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVRX128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvrx128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvrx128_vr128_r_r(dst, src, src2)) }
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inst_stvlxl128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVLXL128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvlxl128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvlxl128_vr128_r_r(dst, src, src2)) }
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inst_stvrxl128_vr128_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVRXL128, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvrxl128_vr128_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvrxl128_vr128_r_r(dst, src, src2)) }
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inst_ti_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_ti_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ti_r_r_imm(dst, src, imm)) }
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inst_mulhhwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHHWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhhwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhhwu_r_r_r(dst, src, src2)) }
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inst_mulhhwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHHWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhhwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhhwu_dot_r_r_r(dst, src, src2)) }
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inst_machhwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwu_r_r_r(dst, src, src2)) }
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inst_machhwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwu_dot_r_r_r(dst, src, src2)) }
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inst_mulhhw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhhw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhhw_r_r_r(dst, src, src2)) }
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inst_mulhhw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULHHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulhhw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulhhw_dot_r_r_r(dst, src, src2)) }
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inst_machhw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhw_r_r_r(dst, src, src2)) }
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inst_machhw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhw_dot_r_r_r(dst, src, src2)) }
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inst_nmachhw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACHHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmachhw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmachhw_r_r_r(dst, src, src2)) }
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inst_nmachhw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACHHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmachhw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmachhw_dot_r_r_r(dst, src, src2)) }
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inst_machhwsu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWSU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwsu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwsu_r_r_r(dst, src, src2)) }
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inst_machhwsu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWSU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwsu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwsu_dot_r_r_r(dst, src, src2)) }
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inst_machhws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhws_r_r_r(dst, src, src2)) }
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inst_machhws_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhws_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhws_dot_r_r_r(dst, src, src2)) }
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inst_nmachhws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACHHWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmachhws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmachhws_r_r_r(dst, src, src2)) }
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inst_nmachhws_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACHHWS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmachhws_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmachhws_dot_r_r_r(dst, src, src2)) }
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inst_vadduqm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDUQM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vadduqm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadduqm_r_r_r(dst, src, src2)) }
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inst_vcmpuq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpuq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpuq_r_r_r(dst, src, src2)) }
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inst_mulchwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULCHWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulchwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulchwu_r_r_r(dst, src, src2)) }
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inst_mulchwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULCHWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulchwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulchwu_dot_r_r_r(dst, src, src2)) }
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inst_macchwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwu_r_r_r(dst, src, src2)) }
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inst_macchwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwu_dot_r_r_r(dst, src, src2)) }
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inst_vcmpsq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPSQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpsq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpsq_r_r_r(dst, src, src2)) }
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inst_mulchw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULCHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulchw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulchw_r_r_r(dst, src, src2)) }
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inst_mulchw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULCHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulchw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulchw_dot_r_r_r(dst, src, src2)) }
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inst_macchw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchw_r_r_r(dst, src, src2)) }
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inst_macchw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchw_dot_r_r_r(dst, src, src2)) }
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inst_nmacchw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACCHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmacchw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmacchw_r_r_r(dst, src, src2)) }
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inst_nmacchw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACCHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmacchw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmacchw_dot_r_r_r(dst, src, src2)) }
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inst_macchwsu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWSU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwsu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwsu_r_r_r(dst, src, src2)) }
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inst_macchwsu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWSU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwsu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwsu_dot_r_r_r(dst, src, src2)) }
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inst_vcmpequq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequq_r_r_r(dst, src, src2)) }
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inst_macchws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchws_r_r_r(dst, src, src2)) }
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inst_macchws_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchws_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchws_dot_r_r_r(dst, src, src2)) }
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inst_nmacchws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACCHWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmacchws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmacchws_r_r_r(dst, src, src2)) }
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inst_nmacchws_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACCHWS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmacchws_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmacchws_dot_r_r_r(dst, src, src2)) }
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inst_vcmpgtuq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtuq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtuq_r_r_r(dst, src, src2)) }
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inst_vcuxwfp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCUXWFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcuxwfp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcuxwfp_r_r_r(dst, src, src2)) }
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inst_mullhwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLHWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullhwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullhwu_r_r_r(dst, src, src2)) }
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inst_mullhwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLHWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullhwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullhwu_dot_r_r_r(dst, src, src2)) }
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inst_maclhwu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwu_r_r_r(dst, src, src2)) }
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inst_maclhwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwu_dot_r_r_r(dst, src, src2)) }
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inst_vcsxwfp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCSXWFP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcsxwfp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcsxwfp_r_r_r(dst, src, src2)) }
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inst_mullhw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullhw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullhw_r_r_r(dst, src, src2)) }
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inst_mullhw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullhw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullhw_dot_r_r_r(dst, src, src2)) }
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inst_maclhw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhw_r_r_r(dst, src, src2)) }
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inst_maclhw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhw_dot_r_r_r(dst, src, src2)) }
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inst_nmaclhw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACLHW, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmaclhw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmaclhw_r_r_r(dst, src, src2)) }
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inst_nmaclhw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACLHW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmaclhw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmaclhw_dot_r_r_r(dst, src, src2)) }
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inst_vcmpgtsq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsq_r_r_r(dst, src, src2)) }
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inst_vcfpuxws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCFPUXWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcfpuxws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcfpuxws_r_r_r(dst, src, src2)) }
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inst_maclhwsu_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWSU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwsu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwsu_r_r_r(dst, src, src2)) }
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inst_maclhwsu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWSU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwsu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwsu_dot_r_r_r(dst, src, src2)) }
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inst_vcfpsxws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCFPSXWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcfpsxws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcfpsxws_r_r_r(dst, src, src2)) }
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inst_maclhws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhws_r_r_r(dst, src, src2)) }
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inst_maclhws_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhws_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhws_dot_r_r_r(dst, src, src2)) }
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inst_nmaclhws_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACLHWS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmaclhws_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmaclhws_r_r_r(dst, src, src2)) }
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inst_nmaclhws_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACLHWS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmaclhws_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmaclhws_dot_r_r_r(dst, src, src2)) }
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inst_machhwuo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwuo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwuo_r_r_r(dst, src, src2)) }
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inst_machhwuo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwuo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwuo_dot_r_r_r(dst, src, src2)) }
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inst_machhwo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwo_r_r_r(dst, src, src2)) }
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inst_machhwo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwo_dot_r_r_r(dst, src, src2)) }
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inst_nmachhwo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACHHWO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmachhwo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmachhwo_r_r_r(dst, src, src2)) }
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inst_nmachhwo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACHHWO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmachhwo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmachhwo_dot_r_r_r(dst, src, src2)) }
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inst_vmr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vmr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmr_r_r_r(dst, src, src2)) }
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inst_machhwsuo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWSUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwsuo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwsuo_r_r_r(dst, src, src2)) }
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inst_machhwsuo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWSUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwsuo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwsuo_dot_r_r_r(dst, src, src2)) }
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inst_machhwso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwso_r_r_r(dst, src, src2)) }
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inst_machhwso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACHHWSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_machhwso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_machhwso_dot_r_r_r(dst, src, src2)) }
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inst_nmachhwso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACHHWSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmachhwso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmachhwso_r_r_r(dst, src, src2)) }
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inst_nmachhwso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACHHWSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmachhwso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmachhwso_dot_r_r_r(dst, src, src2)) }
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inst_vsubuqm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBUQM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vsubuqm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubuqm_r_r_r(dst, src, src2)) }
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inst_vnot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vnot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnot_r_r_r(dst, src, src2)) }
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inst_vgbbd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VGBBD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vgbbd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vgbbd_r_r_r(dst, src, src2)) }
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inst_macchwuo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwuo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwuo_r_r_r(dst, src, src2)) }
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inst_macchwuo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwuo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwuo_dot_r_r_r(dst, src, src2)) }
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inst_macchwo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwo_r_r_r(dst, src, src2)) }
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inst_macchwo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwo_dot_r_r_r(dst, src, src2)) }
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inst_nmacchwo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACCHWO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmacchwo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmacchwo_r_r_r(dst, src, src2)) }
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inst_nmacchwo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACCHWO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmacchwo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmacchwo_dot_r_r_r(dst, src, src2)) }
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inst_macchwsuo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWSUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwsuo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwsuo_r_r_r(dst, src, src2)) }
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inst_macchwsuo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWSUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwsuo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwsuo_dot_r_r_r(dst, src, src2)) }
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inst_vcmpequq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPEQUQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpequq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpequq_dot_r_r_r(dst, src, src2)) }
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inst_macchwso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwso_r_r_r(dst, src, src2)) }
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inst_macchwso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACCHWSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_macchwso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_macchwso_dot_r_r_r(dst, src, src2)) }
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inst_nmacchwso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACCHWSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmacchwso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmacchwso_r_r_r(dst, src, src2)) }
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inst_nmacchwso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACCHWSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmacchwso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmacchwso_dot_r_r_r(dst, src, src2)) }
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inst_vcmpgtuq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTUQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtuq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtuq_dot_r_r_r(dst, src, src2)) }
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inst_maclhwuo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwuo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwuo_r_r_r(dst, src, src2)) }
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inst_maclhwuo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwuo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwuo_dot_r_r_r(dst, src, src2)) }
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inst_maclhwo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwo_r_r_r(dst, src, src2)) }
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inst_maclhwo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwo_dot_r_r_r(dst, src, src2)) }
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inst_nmaclhwo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACLHWO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmaclhwo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmaclhwo_r_r_r(dst, src, src2)) }
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inst_nmaclhwo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACLHWO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmaclhwo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmaclhwo_dot_r_r_r(dst, src, src2)) }
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inst_vcmpgtsq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMPGTSQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vcmpgtsq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmpgtsq_dot_r_r_r(dst, src, src2)) }
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inst_maclhwsuo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWSUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwsuo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwsuo_r_r_r(dst, src, src2)) }
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inst_maclhwsuo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWSUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwsuo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwsuo_dot_r_r_r(dst, src, src2)) }
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inst_maclhwso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwso_r_r_r(dst, src, src2)) }
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inst_maclhwso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MACLHWSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maclhwso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maclhwso_dot_r_r_r(dst, src, src2)) }
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inst_nmaclhwso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACLHWSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmaclhwso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmaclhwso_r_r_r(dst, src, src2)) }
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inst_nmaclhwso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NMACLHWSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nmaclhwso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nmaclhwso_dot_r_r_r(dst, src, src2)) }
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inst_dcbz_l_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBZ_L, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcbz_l_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcbz_l_r_r_r(dst, src, src2)) }
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inst_muli_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MULI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_muli_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_muli_r_r_imm(dst, src, imm)) }
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inst_sfi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SFI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_sfi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sfi_r_r_imm(dst, src, imm)) }
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inst_dozi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DOZI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dozi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dozi_r_r_imm(dst, src, imm)) }
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inst_ai_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .AI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_ai_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ai_r_r_imm(dst, src, imm)) }
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inst_subic_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUBIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_subic_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subic_r_r_imm(dst, src, imm)) }
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inst_ai_dot_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .AI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_ai_dot_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ai_dot_r_r_imm(dst, src, imm)) }
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inst_subic_dot_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUBIC_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_subic_dot_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subic_dot_r_r_imm(dst, src, imm)) }
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inst_lil_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LIL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_lil_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lil_r_r_imm(dst, src, imm)) }
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inst_cal_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CAL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_cal_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_cal_r_r_imm(dst, src, imm)) }
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inst_subi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUBI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_subi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subi_r_r_imm(dst, src, imm)) }
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inst_liu_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LIU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_liu_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_liu_r_r_imm(dst, src, imm)) }
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inst_cau_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CAU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_cau_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_cau_r_r_imm(dst, src, imm)) }
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inst_subis_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUBIS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_subis_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subis_r_r_imm(dst, src, imm)) }
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inst_crnot_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CRNOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_crnot_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_crnot_r_r_imm(dst, src, imm)) }
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inst_rfci_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RFCI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_rfci_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rfci_r_r_imm(dst, src, imm)) }
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inst_rfscv_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RFSCV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_rfscv_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rfscv_r_r_imm(dst, src, imm)) }
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inst_rfsvc_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RFSVC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_rfsvc_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rfsvc_r_r_imm(dst, src, imm)) }
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inst_rfgi_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RFGI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_rfgi_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rfgi_r_r_imm(dst, src, imm)) }
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inst_ics_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_ics_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ics_r_r_imm(dst, src, imm)) }
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inst_crclr_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CRCLR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_crclr_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_crclr_r_r_imm(dst, src, imm)) }
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inst_dnh_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DNH, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_dnh_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dnh_r_r_imm(dst, src, imm)) }
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inst_crset_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CRSET, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_crset_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_crset_r_r_imm(dst, src, imm)) }
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inst_urfid_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URFID, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_urfid_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urfid_r_r_imm(dst, src, imm)) }
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inst_doze_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DOZE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_doze_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_doze_r_r_imm(dst, src, imm)) }
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inst_crmove_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CRMOVE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_crmove_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_crmove_r_r_imm(dst, src, imm)) }
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inst_sleep_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLEEP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_sleep_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sleep_r_r_imm(dst, src, imm)) }
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inst_rvwinkle_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RVWINKLE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_rvwinkle_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rvwinkle_r_r_imm(dst, src, imm)) }
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inst_oril_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ORIL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_oril_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_oril_r_r_imm(dst, src, imm)) }
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inst_oriu_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ORIU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_oriu_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_oriu_r_r_imm(dst, src, imm)) }
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inst_xoril_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XORIL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xoril_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xoril_r_r_imm(dst, src, imm)) }
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inst_xoriu_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XORIU, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_xoriu_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xoriu_r_r_imm(dst, src, imm)) }
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inst_andil_dot_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ANDIL_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_andil_dot_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_andil_dot_r_r_imm(dst, src, imm)) }
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inst_andiu_dot_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ANDIU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} }
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emit_andiu_dot_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_andiu_dot_r_r_imm(dst, src, imm)) }
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inst_rotldi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROTLDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rotldi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rotldi_dot_r_r_r(dst, src, src2)) }
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inst_rotrdi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROTRDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rotrdi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rotrdi_dot_r_r_r(dst, src, src2)) }
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inst_clrldi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CLRLDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_clrldi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_clrldi_dot_r_r_r(dst, src, src2)) }
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inst_srdi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srdi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srdi_dot_r_r_r(dst, src, src2)) }
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inst_extrdi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EXTRDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_extrdi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_extrdi_dot_r_r_r(dst, src, src2)) }
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inst_clrrdi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CLRRDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_clrrdi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_clrrdi_dot_r_r_r(dst, src, src2)) }
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inst_sldi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sldi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sldi_dot_r_r_r(dst, src, src2)) }
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inst_extldi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EXTLDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_extldi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_extldi_dot_r_r_r(dst, src, src2)) }
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inst_clrlsldi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CLRLSLDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_clrlsldi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_clrlsldi_r_r_r(dst, src, src2)) }
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inst_clrlsldi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CLRLSLDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_clrlsldi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_clrlsldi_dot_r_r_r(dst, src, src2)) }
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inst_insrdi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INSRDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_insrdi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_insrdi_r_r_r(dst, src, src2)) }
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inst_insrdi_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INSRDI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_insrdi_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_insrdi_dot_r_r_r(dst, src, src2)) }
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inst_rotld_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROTLD_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rotld_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rotld_dot_r_r_r(dst, src, src2)) }
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inst_t_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .T, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_t_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_t_r_r_r(dst, src, src2)) }
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inst_sf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sf_r_r_r(dst, src, src2)) }
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inst_sf_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SF_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sf_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sf_dot_r_r_r(dst, src, src2)) }
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inst_a_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .A_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_a_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_a_dot_r_r_r(dst, src, src2)) }
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inst_lx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lx_r_r_r(dst, src, src2)) }
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inst_sl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sl_r_r_r(dst, src, src2)) }
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inst_sl_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SL_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sl_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sl_dot_r_r_r(dst, src, src2)) }
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inst_cntlz_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CNTLZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cntlz_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cntlz_r_r_r(dst, src, src2)) }
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inst_cntlz_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CNTLZ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cntlz_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cntlz_dot_r_r_r(dst, src, src2)) }
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inst_maskg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MASKG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maskg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maskg_r_r_r(dst, src, src2)) }
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inst_maskg_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MASKG_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maskg_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maskg_dot_r_r_r(dst, src, src2)) }
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inst_ldepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LDEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ldepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ldepx_r_r_r(dst, src, src2)) }
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inst_waitasec_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WAITASEC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_waitasec_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_waitasec_r_r_r(dst, src, src2)) }
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inst_mviwsplt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MVIWSPLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mviwsplt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mviwsplt_r_r_r(dst, src, src2)) }
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inst_mfvsrd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFVSRD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mfvsrd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mfvsrd_r_r_r(dst, src, src2)) }
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inst_eratilx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ERATILX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_eratilx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eratilx_r_r_r(dst, src, src2)) }
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inst_lux_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LUX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lux_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lux_r_r_r(dst, src, src2)) }
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inst_subwus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBWUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subwus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subwus_r_r_r(dst, src, src2)) }
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inst_subwus_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBWUS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subwus_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subwus_dot_r_r_r(dst, src, src2)) }
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inst_subdus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBDUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subdus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subdus_r_r_r(dst, src, src2)) }
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inst_subdus_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBDUS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subdus_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subdus_dot_r_r_r(dst, src, src2)) }
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inst_subfus_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFUS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfus_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfus_r_r_r(dst, src, src2)) }
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inst_subfus_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFUS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfus_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfus_dot_r_r_r(dst, src, src2)) }
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inst_dlmzb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DLMZB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dlmzb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dlmzb_r_r_r(dst, src, src2)) }
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inst_dlmzb_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DLMZB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dlmzb_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dlmzb_dot_r_r_r(dst, src, src2)) }
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inst_dni_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DNI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dni_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dni_r_r_r(dst, src, src2)) }
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inst_mul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_r_r_r(dst, src, src2)) }
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inst_mul_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mul_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_dot_r_r_r(dst, src, src2)) }
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inst_mvidsplt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MVIDSPLT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mvidsplt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mvidsplt_r_r_r(dst, src, src2)) }
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inst_mtsrdin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTSRDIN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtsrdin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtsrdin_r_r_r(dst, src, src2)) }
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inst_mfvsrwz_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFVSRWZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mfvsrwz_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mfvsrwz_r_r_r(dst, src, src2)) }
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inst_clf_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CLF, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_clf_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_clf_r_r_r(dst, src, src2)) }
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inst_dcbtstls_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBTSTLS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcbtstls_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcbtstls_r_r_r(dst, src, src2)) }
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inst_sfe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfe_r_r_r(dst, src, src2)) }
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inst_sfe_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfe_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfe_dot_r_r_r(dst, src, src2)) }
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inst_ae_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ae_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ae_r_r_r(dst, src, src2)) }
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inst_ae_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ae_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ae_dot_r_r_r(dst, src, src2)) }
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inst_dcbtstlse_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBTSTLSE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcbtstlse_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcbtstlse_r_r_r(dst, src, src2)) }
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inst_mtsle_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTSLE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtsle_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtsle_r_r_r(dst, src, src2)) }
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inst_eratsx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ERATSX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_eratsx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eratsx_r_r_r(dst, src, src2)) }
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inst_eratsx_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ERATSX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_eratsx_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eratsx_dot_r_r_r(dst, src, src2)) }
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inst_stx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stx_r_r_r(dst, src, src2)) }
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inst_slq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_slq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_slq_r_r_r(dst, src, src2)) }
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inst_slq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_slq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_slq_dot_r_r_r(dst, src, src2)) }
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inst_sle_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sle_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sle_r_r_r(dst, src, src2)) }
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inst_sle_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sle_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sle_dot_r_r_r(dst, src, src2)) }
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inst_stdepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STDEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stdepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stdepx_r_r_r(dst, src, src2)) }
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inst_dcbtls_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBTLS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcbtls_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcbtls_r_r_r(dst, src, src2)) }
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inst_dcbtlse_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBTLSE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcbtlse_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcbtlse_r_r_r(dst, src, src2)) }
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inst_mtvsrd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTVSRD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtvsrd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtvsrd_r_r_r(dst, src, src2)) }
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inst_eratre_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ERATRE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_eratre_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eratre_r_r_r(dst, src, src2)) }
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inst_wchkall_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WCHKALL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_wchkall_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_wchkall_r_r_r(dst, src, src2)) }
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inst_stux_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STUX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stux_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stux_r_r_r(dst, src, src2)) }
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inst_sliq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLIQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sliq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sliq_r_r_r(dst, src, src2)) }
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inst_sliq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLIQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sliq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sliq_dot_r_r_r(dst, src, src2)) }
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inst_icblq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ICBLQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_icblq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_icblq_dot_r_r_r(dst, src, src2)) }
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inst_sfze_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFZE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfze_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfze_r_r_r(dst, src, src2)) }
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inst_sfze_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFZE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfze_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfze_dot_r_r_r(dst, src, src2)) }
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inst_aze_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AZE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_aze_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_aze_r_r_r(dst, src, src2)) }
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inst_aze_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AZE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_aze_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_aze_dot_r_r_r(dst, src, src2)) }
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inst_mtvsrwa_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTVSRWA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtvsrwa_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtvsrwa_r_r_r(dst, src, src2)) }
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inst_eratwe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ERATWE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_eratwe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eratwe_r_r_r(dst, src, src2)) }
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inst_ldawx_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LDAWX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ldawx_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ldawx_dot_r_r_r(dst, src, src2)) }
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inst_sllq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLLQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sllq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sllq_r_r_r(dst, src, src2)) }
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inst_sllq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLLQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sllq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sllq_dot_r_r_r(dst, src, src2)) }
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inst_sleq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLEQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sleq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sleq_r_r_r(dst, src, src2)) }
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inst_sleq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLEQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sleq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sleq_dot_r_r_r(dst, src, src2)) }
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inst_sfme_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFME, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfme_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfme_r_r_r(dst, src, src2)) }
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inst_sfme_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFME_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfme_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfme_dot_r_r_r(dst, src, src2)) }
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inst_ame_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AME, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ame_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ame_r_r_r(dst, src, src2)) }
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inst_ame_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AME_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ame_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ame_dot_r_r_r(dst, src, src2)) }
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inst_muls_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_muls_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_muls_r_r_r(dst, src, src2)) }
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inst_muls_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_muls_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_muls_dot_r_r_r(dst, src, src2)) }
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inst_icblce_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ICBLCE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_icblce_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_icblce_r_r_r(dst, src, src2)) }
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inst_mtsri_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTSRI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtsri_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtsri_r_r_r(dst, src, src2)) }
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inst_mtvsrwz_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTVSRWZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtvsrwz_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtvsrwz_r_r_r(dst, src, src2)) }
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inst_dcbtstct_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBTSTCT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcbtstct_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcbtstct_r_r_r(dst, src, src2)) }
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inst_dcbtstds_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBTSTDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcbtstds_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcbtstds_r_r_r(dst, src, src2)) }
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inst_slliq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLLIQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_slliq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_slliq_r_r_r(dst, src, src2)) }
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inst_slliq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLLIQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_slliq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_slliq_dot_r_r_r(dst, src, src2)) }
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inst_mfdcrx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFDCRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mfdcrx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mfdcrx_r_r_r(dst, src, src2)) }
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inst_mfdcrx_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFDCRX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mfdcrx_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mfdcrx_dot_r_r_r(dst, src, src2)) }
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inst_lvexbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVEXBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvexbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvexbx_r_r_r(dst, src, src2)) }
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inst_lvepxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVEPXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvepxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvepxl_r_r_r(dst, src, src2)) }
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inst_doz_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_doz_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_doz_r_r_r(dst, src, src2)) }
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inst_doz_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOZ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_doz_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_doz_dot_r_r_r(dst, src, src2)) }
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inst_cax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CAX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cax_r_r_r(dst, src, src2)) }
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inst_cax_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CAX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cax_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cax_dot_r_r_r(dst, src, src2)) }
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inst_ehpriv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EHPRIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ehpriv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ehpriv_r_r_r(dst, src, src2)) }
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inst_mfapidi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFAPIDI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mfapidi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mfapidi_r_r_r(dst, src, src2)) }
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inst_lscbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSCBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lscbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lscbx_r_r_r(dst, src, src2)) }
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inst_lscbx_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSCBX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lscbx_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lscbx_dot_r_r_r(dst, src, src2)) }
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inst_dcbtct_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBTCT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcbtct_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcbtct_r_r_r(dst, src, src2)) }
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inst_dcbtds_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBTDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcbtds_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcbtds_r_r_r(dst, src, src2)) }
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inst_mfdcrux_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFDCRUX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mfdcrux_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mfdcrux_r_r_r(dst, src, src2)) }
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inst_lvexhx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVEXHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvexhx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvexhx_r_r_r(dst, src, src2)) }
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inst_lvepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvepx_r_r_r(dst, src, src2)) }
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inst_mfbhrbe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFBHRBE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mfbhrbe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mfbhrbe_r_r_r(dst, src, src2)) }
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inst_tlbi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TLBI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_tlbi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tlbi_r_r_r(dst, src, src2)) }
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inst_eciwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ECIWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_eciwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eciwx_r_r_r(dst, src, src2)) }
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inst_mfdcr_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFDCR_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mfdcr_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mfdcr_dot_r_r_r(dst, src, src2)) }
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inst_lvexwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVEXWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvexwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvexwx_r_r_r(dst, src, src2)) }
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inst_dcread_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCREAD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcread_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcread_r_r_r(dst, src, src2)) }
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inst_div_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_div_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_div_r_r_r(dst, src, src2)) }
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inst_div_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIV_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_div_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_div_dot_r_r_r(dst, src, src2)) }
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inst_mftmr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFTMR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mftmr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mftmr_r_r_r(dst, src, src2)) }
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inst_abs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_abs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_abs_r_r_r(dst, src, src2)) }
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inst_abs_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ABS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_abs_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_abs_dot_r_r_r(dst, src, src2)) }
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inst_divs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divs_r_r_r(dst, src, src2)) }
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inst_divs_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divs_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divs_dot_r_r_r(dst, src, src2)) }
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inst_lxvwsx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LXVWSX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lxvwsx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lxvwsx_r_r_r(dst, src, src2)) }
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inst_tlbia_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TLBIA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_tlbia_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tlbia_r_r_r(dst, src, src2)) }
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inst_setbc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SETBC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_setbc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setbc_r_r_r(dst, src, src2)) }
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inst_mtdcrx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTDCRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtdcrx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtdcrx_r_r_r(dst, src, src2)) }
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inst_mtdcrx_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTDCRX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtdcrx_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtdcrx_dot_r_r_r(dst, src, src2)) }
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inst_stvexbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVEXBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvexbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvexbx_r_r_r(dst, src, src2)) }
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inst_dcblc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBLC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcblc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcblc_r_r_r(dst, src, src2)) }
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inst_dcblce_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBLCE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcblce_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcblce_r_r_r(dst, src, src2)) }
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inst_pbt_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PBT_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_pbt_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pbt_dot_r_r_r(dst, src, src2)) }
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inst_icswx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ICSWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_icswx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_icswx_r_r_r(dst, src, src2)) }
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inst_icswx_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ICSWX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_icswx_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_icswx_dot_r_r_r(dst, src, src2)) }
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inst_setbcr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SETBCR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_setbcr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setbcr_r_r_r(dst, src, src2)) }
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inst_mtdcrux_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTDCRUX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtdcrux_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtdcrux_r_r_r(dst, src, src2)) }
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inst_stvexhx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVEXHX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvexhx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvexhx_r_r_r(dst, src, src2)) }
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inst_dcblq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCBLQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcblq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcblq_dot_r_r_r(dst, src, src2)) }
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inst_clrbhrb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CLRBHRB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_clrbhrb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_clrbhrb_r_r_r(dst, src, src2)) }
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inst_ecowx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ECOWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ecowx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ecowx_r_r_r(dst, src, src2)) }
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inst_setnbc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SETNBC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_setnbc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setnbc_r_r_r(dst, src, src2)) }
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inst_mtdcr_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTDCR_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mtdcr_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mtdcr_dot_r_r_r(dst, src, src2)) }
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inst_stvexwx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVEXWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvexwx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvexwx_r_r_r(dst, src, src2)) }
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inst_dci_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dci_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dci_r_r_r(dst, src, src2)) }
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inst_mttmr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MTTMR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mttmr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mttmr_r_r_r(dst, src, src2)) }
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inst_setnbcr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SETNBCR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_setnbcr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setnbcr_r_r_r(dst, src, src2)) }
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inst_dsn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DSN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dsn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dsn_r_r_r(dst, src, src2)) }
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inst_nabs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NABS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nabs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nabs_r_r_r(dst, src, src2)) }
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inst_nabs_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NABS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nabs_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nabs_dot_r_r_r(dst, src, src2)) }
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inst_icbtlse_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ICBTLSE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_icbtlse_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_icbtlse_r_r_r(dst, src, src2)) }
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inst_cli_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CLI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_cli_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cli_r_r_r(dst, src, src2)) }
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inst_mcrxr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCRXR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mcrxr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mcrxr_r_r_r(dst, src, src2)) }
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inst_lbdcbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LBDCBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lbdcbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lbdcbx_r_r_r(dst, src, src2)) }
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inst_lbdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LBDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lbdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lbdx_r_r_r(dst, src, src2)) }
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inst_bblels_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BBLELS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_bblels_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bblels_r_r_r(dst, src, src2)) }
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inst_lvlx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvlx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvlx_r_r_r(dst, src, src2)) }
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inst_subfco_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFCO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfco_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfco_r_r_r(dst, src, src2)) }
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inst_sfo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfo_r_r_r(dst, src, src2)) }
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inst_subco_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBCO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subco_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subco_r_r_r(dst, src, src2)) }
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inst_subfco_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFCO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfco_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfco_dot_r_r_r(dst, src, src2)) }
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inst_sfo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfo_dot_r_r_r(dst, src, src2)) }
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inst_subco_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBCO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subco_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subco_dot_r_r_r(dst, src, src2)) }
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inst_addco_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDCO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addco_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addco_r_r_r(dst, src, src2)) }
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inst_ao_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ao_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ao_r_r_r(dst, src, src2)) }
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inst_addco_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDCO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addco_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addco_dot_r_r_r(dst, src, src2)) }
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inst_ao_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ao_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ao_dot_r_r_r(dst, src, src2)) }
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inst_clcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CLCS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_clcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_clcs_r_r_r(dst, src, src2)) }
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inst_lsx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lsx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsx_r_r_r(dst, src, src2)) }
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inst_lbrx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LBRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lbrx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lbrx_r_r_r(dst, src, src2)) }
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inst_sr_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SR_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sr_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sr_dot_r_r_r(dst, src, src2)) }
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inst_rrib_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RRIB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rrib_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rrib_r_r_r(dst, src, src2)) }
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inst_rrib_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RRIB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rrib_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rrib_dot_r_r_r(dst, src, src2)) }
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inst_maskir_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MASKIR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maskir_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maskir_r_r_r(dst, src, src2)) }
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inst_maskir_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MASKIR_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_maskir_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_maskir_dot_r_r_r(dst, src, src2)) }
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inst_lhdcbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LHDCBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lhdcbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lhdcbx_r_r_r(dst, src, src2)) }
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inst_lhdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LHDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lhdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lhdx_r_r_r(dst, src, src2)) }
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inst_lvtrx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVTRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvtrx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvtrx_r_r_r(dst, src, src2)) }
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inst_bbelr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BBELR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_bbelr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bbelr_r_r_r(dst, src, src2)) }
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inst_lvrx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvrx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvrx_r_r_r(dst, src, src2)) }
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inst_subfo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfo_r_r_r(dst, src, src2)) }
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inst_subo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subo_r_r_r(dst, src, src2)) }
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inst_subfo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfo_dot_r_r_r(dst, src, src2)) }
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inst_subo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subo_dot_r_r_r(dst, src, src2)) }
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inst_lwdcbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LWDCBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lwdcbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lwdcbx_r_r_r(dst, src, src2)) }
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inst_lwdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LWDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lwdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lwdx_r_r_r(dst, src, src2)) }
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inst_lvtlx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVTLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvtlx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvtlx_r_r_r(dst, src, src2)) }
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inst_lsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsi_r_r_r(dst, src, src2)) }
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inst_dcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dcs_r_r_r(dst, src, src2)) }
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inst_mffgpr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFFGPR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mffgpr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mffgpr_r_r_r(dst, src, src2)) }
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inst_lddx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LDDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lddx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lddx_r_r_r(dst, src, src2)) }
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inst_lvswx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVSWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvswx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvswx_r_r_r(dst, src, src2)) }
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inst_nego_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NEGO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nego_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nego_r_r_r(dst, src, src2)) }
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inst_nego_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NEGO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nego_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nego_dot_r_r_r(dst, src, src2)) }
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inst_mulo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulo_r_r_r(dst, src, src2)) }
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inst_mulo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulo_dot_r_r_r(dst, src, src2)) }
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inst_mfsri_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFSRI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mfsri_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mfsri_r_r_r(dst, src, src2)) }
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inst_dclst_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCLST, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dclst_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dclst_r_r_r(dst, src, src2)) }
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inst_stbdcbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STBDCBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stbdcbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stbdcbx_r_r_r(dst, src, src2)) }
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inst_stbdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STBDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stbdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stbdx_r_r_r(dst, src, src2)) }
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inst_stvlx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvlx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvlx_r_r_r(dst, src, src2)) }
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inst_subfeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfeo_r_r_r(dst, src, src2)) }
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inst_sfeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfeo_r_r_r(dst, src, src2)) }
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inst_subfeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfeo_dot_r_r_r(dst, src, src2)) }
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inst_sfeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfeo_dot_r_r_r(dst, src, src2)) }
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inst_addeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addeo_r_r_r(dst, src, src2)) }
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inst_aeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_aeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_aeo_r_r_r(dst, src, src2)) }
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inst_addeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addeo_dot_r_r_r(dst, src, src2)) }
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inst_aeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_aeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_aeo_dot_r_r_r(dst, src, src2)) }
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inst_hashstp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .HASHSTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_hashstp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_hashstp_r_r_r(dst, src, src2)) }
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inst_stsx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STSX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stsx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stsx_r_r_r(dst, src, src2)) }
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inst_stbrx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STBRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stbrx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stbrx_r_r_r(dst, src, src2)) }
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inst_srq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srq_r_r_r(dst, src, src2)) }
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inst_srq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srq_dot_r_r_r(dst, src, src2)) }
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inst_sre_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRE, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sre_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sre_r_r_r(dst, src, src2)) }
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inst_sre_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sre_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sre_dot_r_r_r(dst, src, src2)) }
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inst_sthdcbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STHDCBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sthdcbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sthdcbx_r_r_r(dst, src, src2)) }
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inst_sthdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STHDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sthdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sthdx_r_r_r(dst, src, src2)) }
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inst_stvfrx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVFRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvfrx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvfrx_r_r_r(dst, src, src2)) }
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inst_stvrx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVRX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvrx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvrx_r_r_r(dst, src, src2)) }
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inst_hashchkp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .HASHCHKP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_hashchkp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_hashchkp_r_r_r(dst, src, src2)) }
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inst_sriq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRIQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sriq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sriq_r_r_r(dst, src, src2)) }
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inst_sriq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRIQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sriq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sriq_dot_r_r_r(dst, src, src2)) }
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inst_stwdcbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STWDCBX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stwdcbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stwdcbx_r_r_r(dst, src, src2)) }
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inst_stwdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STWDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stwdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stwdx_r_r_r(dst, src, src2)) }
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inst_stvflx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVFLX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvflx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvflx_r_r_r(dst, src, src2)) }
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inst_subfzeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFZEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfzeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfzeo_r_r_r(dst, src, src2)) }
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inst_sfzeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFZEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfzeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfzeo_r_r_r(dst, src, src2)) }
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inst_subfzeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFZEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfzeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfzeo_dot_r_r_r(dst, src, src2)) }
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inst_sfzeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFZEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfzeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfzeo_dot_r_r_r(dst, src, src2)) }
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inst_addzeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDZEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addzeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addzeo_r_r_r(dst, src, src2)) }
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inst_azeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AZEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_azeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_azeo_r_r_r(dst, src, src2)) }
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inst_addzeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDZEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addzeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addzeo_dot_r_r_r(dst, src, src2)) }
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inst_azeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AZEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_azeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_azeo_dot_r_r_r(dst, src, src2)) }
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inst_hashst_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .HASHST, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_hashst_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_hashst_r_r_r(dst, src, src2)) }
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inst_stsi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STSI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stsi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stsi_r_r_r(dst, src, src2)) }
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inst_srlq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRLQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srlq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srlq_r_r_r(dst, src, src2)) }
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inst_srlq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRLQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srlq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srlq_dot_r_r_r(dst, src, src2)) }
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inst_sreq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SREQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sreq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sreq_r_r_r(dst, src, src2)) }
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inst_sreq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SREQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sreq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sreq_dot_r_r_r(dst, src, src2)) }
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inst_mftgpr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MFTGPR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mftgpr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mftgpr_r_r_r(dst, src, src2)) }
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inst_stddx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STDDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stddx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stddx_r_r_r(dst, src, src2)) }
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inst_stvswx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVSWX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvswx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvswx_r_r_r(dst, src, src2)) }
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inst_subfmeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFMEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfmeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfmeo_r_r_r(dst, src, src2)) }
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inst_sfmeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFMEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfmeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfmeo_r_r_r(dst, src, src2)) }
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inst_subfmeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBFMEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_subfmeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subfmeo_dot_r_r_r(dst, src, src2)) }
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inst_sfmeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SFMEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sfmeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sfmeo_dot_r_r_r(dst, src, src2)) }
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inst_mulldo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLDO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulldo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulldo_r_r_r(dst, src, src2)) }
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inst_mulldo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLDO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulldo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulldo_dot_r_r_r(dst, src, src2)) }
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inst_addmeo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDMEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addmeo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addmeo_r_r_r(dst, src, src2)) }
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inst_ameo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AMEO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ameo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ameo_r_r_r(dst, src, src2)) }
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inst_addmeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDMEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addmeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addmeo_dot_r_r_r(dst, src, src2)) }
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inst_ameo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AMEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ameo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ameo_dot_r_r_r(dst, src, src2)) }
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inst_mullwo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLWO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullwo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullwo_r_r_r(dst, src, src2)) }
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inst_mulso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulso_r_r_r(dst, src, src2)) }
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inst_mullwo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULLWO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mullwo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mullwo_dot_r_r_r(dst, src, src2)) }
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inst_mulso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MULSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_mulso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mulso_dot_r_r_r(dst, src, src2)) }
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inst_tsr_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TSR_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_tsr_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tsr_dot_r_r_r(dst, src, src2)) }
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inst_hashchk_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .HASHCHK, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_hashchk_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_hashchk_r_r_r(dst, src, src2)) }
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inst_srliq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRLIQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srliq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srliq_r_r_r(dst, src, src2)) }
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inst_srliq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRLIQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srliq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srliq_dot_r_r_r(dst, src, src2)) }
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inst_lvsm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVSM, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvsm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvsm_r_r_r(dst, src, src2)) }
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inst_stvepxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVEPXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvepxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvepxl_r_r_r(dst, src, src2)) }
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inst_lvlxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVLXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvlxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvlxl_r_r_r(dst, src, src2)) }
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inst_dozo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOZO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dozo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dozo_r_r_r(dst, src, src2)) }
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inst_dozo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOZO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dozo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dozo_dot_r_r_r(dst, src, src2)) }
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inst_addo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addo_r_r_r(dst, src, src2)) }
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inst_caxo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CAXO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_caxo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_caxo_r_r_r(dst, src, src2)) }
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inst_addo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_addo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addo_dot_r_r_r(dst, src, src2)) }
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inst_caxo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CAXO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_caxo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_caxo_dot_r_r_r(dst, src, src2)) }
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inst_lfqx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LFQX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lfqx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lfqx_r_r_r(dst, src, src2)) }
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inst_sra_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sra_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sra_r_r_r(dst, src, src2)) }
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inst_sra_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRA_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sra_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sra_dot_r_r_r(dst, src, src2)) }
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inst_evlddepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVLDDEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evlddepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evlddepx_r_r_r(dst, src, src2)) }
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inst_lfddx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LFDDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lfddx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lfddx_r_r_r(dst, src, src2)) }
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inst_lvtrxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVTRXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvtrxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvtrxl_r_r_r(dst, src, src2)) }
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inst_stvepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvepx_r_r_r(dst, src, src2)) }
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inst_lvrxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVRXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvrxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvrxl_r_r_r(dst, src, src2)) }
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inst_rac_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rac_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rac_r_r_r(dst, src, src2)) }
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inst_erativax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ERATIVAX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_erativax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_erativax_r_r_r(dst, src, src2)) }
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inst_lfqux_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LFQUX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lfqux_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lfqux_r_r_r(dst, src, src2)) }
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inst_srai_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srai_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srai_r_r_r(dst, src, src2)) }
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inst_srai_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAI_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srai_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srai_dot_r_r_r(dst, src, src2)) }
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inst_lvtlxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVTLXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvtlxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvtlxl_r_r_r(dst, src, src2)) }
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inst_divo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divo_r_r_r(dst, src, src2)) }
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inst_divo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divo_dot_r_r_r(dst, src, src2)) }
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inst_tlbsrx_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TLBSRX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_tlbsrx_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tlbsrx_dot_r_r_r(dst, src, src2)) }
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inst_slbiag_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLBIAG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_slbiag_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_slbiag_r_r_r(dst, src, src2)) }
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inst_lvswxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LVSWXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_lvswxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lvswxl_r_r_r(dst, src, src2)) }
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inst_abso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ABSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_abso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_abso_r_r_r(dst, src, src2)) }
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inst_abso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ABSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_abso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_abso_dot_r_r_r(dst, src, src2)) }
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inst_divso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divso_r_r_r(dst, src, src2)) }
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inst_divso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divso_dot_r_r_r(dst, src, src2)) }
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inst_rmieg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RMIEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_rmieg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rmieg_r_r_r(dst, src, src2)) }
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inst_stvlxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVLXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvlxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvlxl_r_r_r(dst, src, src2)) }
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inst_divdeuo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDEUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdeuo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdeuo_dot_r_r_r(dst, src, src2)) }
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inst_divweuo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWEUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divweuo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divweuo_dot_r_r_r(dst, src, src2)) }
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inst_tlbsx_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TLBSX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_tlbsx_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tlbsx_dot_r_r_r(dst, src, src2)) }
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inst_stfqx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STFQX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stfqx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stfqx_r_r_r(dst, src, src2)) }
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inst_sraq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sraq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sraq_r_r_r(dst, src, src2)) }
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inst_sraq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sraq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sraq_dot_r_r_r(dst, src, src2)) }
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inst_srea_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SREA, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srea_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srea_r_r_r(dst, src, src2)) }
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inst_srea_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SREA_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_srea_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srea_dot_r_r_r(dst, src, src2)) }
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inst_exts_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EXTS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_exts_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_exts_r_r_r(dst, src, src2)) }
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inst_exts_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EXTS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_exts_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_exts_dot_r_r_r(dst, src, src2)) }
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inst_evstddepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSTDDEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evstddepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evstddepx_r_r_r(dst, src, src2)) }
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inst_stfddx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STFDDX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stfddx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stfddx_r_r_r(dst, src, src2)) }
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inst_stvfrxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVFRXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvfrxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvfrxl_r_r_r(dst, src, src2)) }
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inst_wclrall_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WCLRALL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_wclrall_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_wclrall_r_r_r(dst, src, src2)) }
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inst_wclr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WCLR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_wclr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_wclr_r_r_r(dst, src, src2)) }
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inst_stvrxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVRXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvrxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvrxl_r_r_r(dst, src, src2)) }
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inst_divdeo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdeo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdeo_dot_r_r_r(dst, src, src2)) }
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inst_divweo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWEO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divweo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divweo_dot_r_r_r(dst, src, src2)) }
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inst_icswepx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ICSWEPX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_icswepx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_icswepx_r_r_r(dst, src, src2)) }
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inst_icswepx_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ICSWEPX_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_icswepx_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_icswepx_dot_r_r_r(dst, src, src2)) }
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inst_stfqux_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STFQUX, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stfqux_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stfqux_r_r_r(dst, src, src2)) }
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inst_sraiq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAIQ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sraiq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sraiq_r_r_r(dst, src, src2)) }
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inst_sraiq_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRAIQ_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_sraiq_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sraiq_dot_r_r_r(dst, src, src2)) }
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inst_stvflxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVFLXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvflxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvflxl_r_r_r(dst, src, src2)) }
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inst_ici_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ICI, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_ici_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ici_r_r_r(dst, src, src2)) }
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inst_divduo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divduo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divduo_r_r_r(dst, src, src2)) }
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inst_divduo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divduo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divduo_dot_r_r_r(dst, src, src2)) }
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inst_divwuo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWUO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwuo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwuo_r_r_r(dst, src, src2)) }
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inst_divwuo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWUO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwuo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwuo_dot_r_r_r(dst, src, src2)) }
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inst_slbfee_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SLBFEE_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_slbfee_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_slbfee_dot_r_r_r(dst, src, src2)) }
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inst_stvswxl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .STVSWXL, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_stvswxl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_stvswxl_r_r_r(dst, src, src2)) }
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inst_icread_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ICREAD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_icread_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_icread_r_r_r(dst, src, src2)) }
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inst_nabso_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NABSO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nabso_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nabso_r_r_r(dst, src, src2)) }
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inst_nabso_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .NABSO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_nabso_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nabso_dot_r_r_r(dst, src, src2)) }
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inst_divdo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdo_r_r_r(dst, src, src2)) }
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inst_divdo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVDO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divdo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divdo_dot_r_r_r(dst, src, src2)) }
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inst_divwo_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWO, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwo_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwo_r_r_r(dst, src, src2)) }
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inst_divwo_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DIVWO_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_divwo_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_divwo_dot_r_r_r(dst, src, src2)) }
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inst_dclz_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DCLZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_dclz_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dclz_r_r_r(dst, src, src2)) }
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inst_lu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lu_r_mem(dst, addr)) }
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inst_st_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .ST, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_st_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_st_r_mem(dst, addr)) }
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inst_stu_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stu_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stu_r_mem(dst, addr)) }
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inst_lm_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LM, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lm_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lm_r_mem(dst, addr)) }
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inst_stm_r_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STM, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stm_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stm_r_mem(dst, addr)) }
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inst_lfq_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfq_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfq_fr_mem(dst, addr)) }
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inst_lfqu_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .LFQU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_lfqu_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_lfqu_fr_mem(dst, addr)) }
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inst_stfq_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfq_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfq_fr_mem(dst, addr)) }
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inst_stfqu_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .STFQU, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_stfqu_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_stfqu_fr_mem(dst, addr)) }
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inst_fcir_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FCIR, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fcir_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fcir_fr_mem(dst, addr)) }
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inst_fcir_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FCIR_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fcir_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fcir_dot_fr_mem(dst, addr)) }
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inst_fcirz_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FCIRZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fcirz_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fcirz_fr_mem(dst, addr)) }
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inst_fcirz_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FCIRZ_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fcirz_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fcirz_dot_fr_mem(dst, addr)) }
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inst_fd_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FD, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fd_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fd_fr_mem(dst, addr)) }
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inst_fd_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FD_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fd_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fd_dot_fr_mem(dst, addr)) }
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inst_fs_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FS, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fs_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fs_fr_mem(dst, addr)) }
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inst_fs_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fs_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fs_dot_fr_mem(dst, addr)) }
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inst_fa_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FA, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fa_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fa_fr_mem(dst, addr)) }
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inst_fa_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FA_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fa_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fa_dot_fr_mem(dst, addr)) }
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inst_fm_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FM, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fm_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fm_fr_mem(dst, addr)) }
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inst_fm_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FM_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fm_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fm_dot_fr_mem(dst, addr)) }
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inst_fms_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FMS, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fms_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fms_fr_mem(dst, addr)) }
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inst_fms_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FMS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fms_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fms_dot_fr_mem(dst, addr)) }
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inst_fma_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FMA, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fma_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fma_fr_mem(dst, addr)) }
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inst_fma_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FMA_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fma_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fma_dot_fr_mem(dst, addr)) }
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inst_fnms_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FNMS, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fnms_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fnms_fr_mem(dst, addr)) }
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inst_fnms_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FNMS_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fnms_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fnms_dot_fr_mem(dst, addr)) }
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inst_fnma_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FNMA, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fnma_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fnma_fr_mem(dst, addr)) }
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inst_fnma_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .FNMA_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_fnma_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_fnma_dot_fr_mem(dst, addr)) }
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inst_dtstexq_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .DTSTEXQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_dtstexq_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_dtstexq_fr_mem(dst, addr)) }
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inst_xscmpexpqp_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .XSCMPEXPQP, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_xscmpexpqp_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_xscmpexpqp_fr_mem(dst, addr)) }
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inst_dxexq_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .DXEXQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_dxexq_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_dxexq_fr_mem(dst, addr)) }
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inst_dxexq_dot_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .DXEXQ_DOT, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_dxexq_dot_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_dxexq_dot_fr_mem(dst, addr)) }
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inst_dtstsfq_fr_mem :: #force_inline proc "contextless" (dst: Register, addr: Memory) -> Instruction { return Instruction{mnemonic = .DTSTSFQ, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(addr), {}, {}}} }
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emit_dtstsfq_fr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, addr: Memory) { append(instructions, inst_dtstsfq_fr_mem(dst, addr)) }
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inst_evseteqb_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETEQB_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evseteqb_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evseteqb_dot_r_r_r(dst, src, src2)) }
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inst_evseteqh_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETEQH_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evseteqh_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evseteqh_dot_r_r_r(dst, src, src2)) }
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inst_evseteqw_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETEQW_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evseteqw_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evseteqw_dot_r_r_r(dst, src, src2)) }
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inst_evsetgthu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTHU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgthu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgthu_dot_r_r_r(dst, src, src2)) }
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inst_evsetgths_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTHS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgths_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgths_dot_r_r_r(dst, src, src2)) }
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inst_evsetgtwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgtwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgtwu_dot_r_r_r(dst, src, src2)) }
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inst_evsetgtws_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTWS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgtws_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgtws_dot_r_r_r(dst, src, src2)) }
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inst_evsetgtbu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTBU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgtbu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgtbu_dot_r_r_r(dst, src, src2)) }
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inst_evsetgtbs_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETGTBS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetgtbs_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetgtbs_dot_r_r_r(dst, src, src2)) }
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inst_evsetltbu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTBU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetltbu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetltbu_dot_r_r_r(dst, src, src2)) }
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inst_evsetltbs_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTBS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetltbs_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetltbs_dot_r_r_r(dst, src, src2)) }
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inst_evsetlthu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTHU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetlthu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetlthu_dot_r_r_r(dst, src, src2)) }
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inst_evsetlths_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTHS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetlths_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetlths_dot_r_r_r(dst, src, src2)) }
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inst_evsetltwu_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTWU_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetltwu_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetltwu_dot_r_r_r(dst, src, src2)) }
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inst_evsetltws_dot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EVSETLTWS_DOT, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_evsetltws_dot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_evsetltws_dot_r_r_r(dst, src, src2)) }
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// =============================================================================
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// Overload Groups
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// =============================================================================
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inst_b :: inst_b_rel
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emit_b :: emit_b_rel
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inst_bl :: inst_bl_rel
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emit_bl :: emit_bl_rel
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inst_ba :: inst_ba_rel
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emit_ba :: emit_ba_rel
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inst_bla :: inst_bla_rel
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emit_bla :: emit_bla_rel
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inst_bc :: inst_bc_bo_crb_rel
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emit_bc :: emit_bc_bo_crb_rel
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inst_bcl :: inst_bcl_bo_crb_rel
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emit_bcl :: emit_bcl_bo_crb_rel
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inst_bca :: inst_bca_bo_crb_rel
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emit_bca :: emit_bca_bo_crb_rel
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inst_bcla :: inst_bcla_bo_crb_rel
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emit_bcla :: emit_bcla_bo_crb_rel
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inst_bclr :: inst_bclr_bo_crb_bh
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emit_bclr :: emit_bclr_bo_crb_bh
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inst_bclrl :: inst_bclrl_bo_crb_bh
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emit_bclrl :: emit_bclrl_bo_crb_bh
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inst_bcctr :: inst_bcctr_bo_crb_bh
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emit_bcctr :: emit_bcctr_bo_crb_bh
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inst_bcctrl :: inst_bcctrl_bo_crb_bh
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emit_bcctrl :: emit_bcctrl_bo_crb_bh
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inst_bctar :: inst_bctar_bo_crb_bh
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emit_bctar :: emit_bctar_bo_crb_bh
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inst_bctarl :: inst_bctarl_bo_crb_bh
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emit_bctarl :: emit_bctarl_bo_crb_bh
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inst_sc :: inst_sc_imm
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emit_sc :: emit_sc_imm
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inst_crand :: inst_crand_crb_crb_crb
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emit_crand :: emit_crand_crb_crb_crb
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inst_crnand :: inst_crnand_crb_crb_crb
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emit_crnand :: emit_crnand_crb_crb_crb
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inst_cror :: inst_cror_crb_crb_crb
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emit_cror :: emit_cror_crb_crb_crb
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inst_crnor :: inst_crnor_crb_crb_crb
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emit_crnor :: emit_crnor_crb_crb_crb
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inst_crxor :: inst_crxor_crb_crb_crb
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emit_crxor :: emit_crxor_crb_crb_crb
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inst_creqv :: inst_creqv_crb_crb_crb
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emit_creqv :: emit_creqv_crb_crb_crb
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inst_crandc :: inst_crandc_crb_crb_crb
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emit_crandc :: emit_crandc_crb_crb_crb
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inst_crorc :: inst_crorc_crb_crb_crb
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emit_crorc :: emit_crorc_crb_crb_crb
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inst_mcrf :: inst_mcrf_crf_crf
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emit_mcrf :: emit_mcrf_crf_crf
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inst_lbz :: inst_lbz_r_mem
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emit_lbz :: emit_lbz_r_mem
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inst_lbzu :: inst_lbzu_r_mem
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emit_lbzu :: emit_lbzu_r_mem
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inst_lbzx :: inst_lbzx_r_mem
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emit_lbzx :: emit_lbzx_r_mem
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inst_lbzux :: inst_lbzux_r_mem
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emit_lbzux :: emit_lbzux_r_mem
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inst_lhz :: inst_lhz_r_mem
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|
emit_lhz :: emit_lhz_r_mem
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|
inst_lhzu :: inst_lhzu_r_mem
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|
emit_lhzu :: emit_lhzu_r_mem
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|
inst_lhzx :: inst_lhzx_r_mem
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|
emit_lhzx :: emit_lhzx_r_mem
|
|
inst_lhzux :: inst_lhzux_r_mem
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|
emit_lhzux :: emit_lhzux_r_mem
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|
inst_lha :: inst_lha_r_mem
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|
emit_lha :: emit_lha_r_mem
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|
inst_lhau :: inst_lhau_r_mem
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|
emit_lhau :: emit_lhau_r_mem
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|
inst_lhax :: inst_lhax_r_mem
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|
emit_lhax :: emit_lhax_r_mem
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|
inst_lhaux :: inst_lhaux_r_mem
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|
emit_lhaux :: emit_lhaux_r_mem
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|
inst_lwz :: inst_lwz_r_mem
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|
emit_lwz :: emit_lwz_r_mem
|
|
inst_lwzu :: inst_lwzu_r_mem
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|
emit_lwzu :: emit_lwzu_r_mem
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|
inst_lwzx :: inst_lwzx_r_mem
|
|
emit_lwzx :: emit_lwzx_r_mem
|
|
inst_lwzux :: inst_lwzux_r_mem
|
|
emit_lwzux :: emit_lwzux_r_mem
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|
inst_lwa :: inst_lwa_r_mem
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|
emit_lwa :: emit_lwa_r_mem
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|
inst_lwax :: inst_lwax_r_mem
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|
emit_lwax :: emit_lwax_r_mem
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|
inst_lwaux :: inst_lwaux_r_mem
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|
emit_lwaux :: emit_lwaux_r_mem
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|
inst_ld :: inst_ld_r_mem
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|
emit_ld :: emit_ld_r_mem
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|
inst_ldu :: inst_ldu_r_mem
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|
emit_ldu :: emit_ldu_r_mem
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|
inst_ldx :: inst_ldx_r_mem
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|
emit_ldx :: emit_ldx_r_mem
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|
inst_ldux :: inst_ldux_r_mem
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|
emit_ldux :: emit_ldux_r_mem
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|
inst_lq :: inst_lq_r_mem
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|
emit_lq :: emit_lq_r_mem
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|
inst_lhbrx :: inst_lhbrx_r_mem
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|
emit_lhbrx :: emit_lhbrx_r_mem
|
|
inst_lwbrx :: inst_lwbrx_r_mem
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|
emit_lwbrx :: emit_lwbrx_r_mem
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|
inst_ldbrx :: inst_ldbrx_r_mem
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|
emit_ldbrx :: emit_ldbrx_r_mem
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|
inst_lmw :: inst_lmw_r_mem
|
|
emit_lmw :: emit_lmw_r_mem
|
|
inst_lswi :: inst_lswi_r_r_imm
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|
emit_lswi :: emit_lswi_r_r_imm
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|
inst_lswx :: inst_lswx_r_mem
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|
emit_lswx :: emit_lswx_r_mem
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|
inst_stb :: inst_stb_r_mem
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|
emit_stb :: emit_stb_r_mem
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|
inst_stbu :: inst_stbu_r_mem
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|
emit_stbu :: emit_stbu_r_mem
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|
inst_stbx :: inst_stbx_r_mem
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|
emit_stbx :: emit_stbx_r_mem
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|
inst_stbux :: inst_stbux_r_mem
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|
emit_stbux :: emit_stbux_r_mem
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|
inst_sth :: inst_sth_r_mem
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|
emit_sth :: emit_sth_r_mem
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|
inst_sthu :: inst_sthu_r_mem
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|
emit_sthu :: emit_sthu_r_mem
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|
inst_sthx :: inst_sthx_r_mem
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emit_sthx :: emit_sthx_r_mem
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inst_sthux :: inst_sthux_r_mem
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|
emit_sthux :: emit_sthux_r_mem
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|
inst_stw :: inst_stw_r_mem
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|
emit_stw :: emit_stw_r_mem
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|
inst_stwu :: inst_stwu_r_mem
|
|
emit_stwu :: emit_stwu_r_mem
|
|
inst_stwx :: inst_stwx_r_mem
|
|
emit_stwx :: emit_stwx_r_mem
|
|
inst_stwux :: inst_stwux_r_mem
|
|
emit_stwux :: emit_stwux_r_mem
|
|
inst_std :: inst_std_r_mem
|
|
emit_std :: emit_std_r_mem
|
|
inst_stdu :: inst_stdu_r_mem
|
|
emit_stdu :: emit_stdu_r_mem
|
|
inst_stdx :: inst_stdx_r_mem
|
|
emit_stdx :: emit_stdx_r_mem
|
|
inst_stdux :: inst_stdux_r_mem
|
|
emit_stdux :: emit_stdux_r_mem
|
|
inst_stq :: inst_stq_r_mem
|
|
emit_stq :: emit_stq_r_mem
|
|
inst_sthbrx :: inst_sthbrx_r_mem
|
|
emit_sthbrx :: emit_sthbrx_r_mem
|
|
inst_stwbrx :: inst_stwbrx_r_mem
|
|
emit_stwbrx :: emit_stwbrx_r_mem
|
|
inst_stdbrx :: inst_stdbrx_r_mem
|
|
emit_stdbrx :: emit_stdbrx_r_mem
|
|
inst_stmw :: inst_stmw_r_mem
|
|
emit_stmw :: emit_stmw_r_mem
|
|
inst_stswi :: inst_stswi_r_r_imm
|
|
emit_stswi :: emit_stswi_r_r_imm
|
|
inst_stswx :: inst_stswx_r_mem
|
|
emit_stswx :: emit_stswx_r_mem
|
|
inst_lbarx :: inst_lbarx_r_mem
|
|
emit_lbarx :: emit_lbarx_r_mem
|
|
inst_lharx :: inst_lharx_r_mem
|
|
emit_lharx :: emit_lharx_r_mem
|
|
inst_lwarx :: inst_lwarx_r_mem
|
|
emit_lwarx :: emit_lwarx_r_mem
|
|
inst_ldarx :: inst_ldarx_r_mem
|
|
emit_ldarx :: emit_ldarx_r_mem
|
|
inst_lqarx :: inst_lqarx_r_mem
|
|
emit_lqarx :: emit_lqarx_r_mem
|
|
inst_stbcx_dot :: inst_stbcx_dot_r_mem
|
|
emit_stbcx_dot :: emit_stbcx_dot_r_mem
|
|
inst_sthcx_dot :: inst_sthcx_dot_r_mem
|
|
emit_sthcx_dot :: emit_sthcx_dot_r_mem
|
|
inst_stwcx_dot :: inst_stwcx_dot_r_mem
|
|
emit_stwcx_dot :: emit_stwcx_dot_r_mem
|
|
inst_stdcx_dot :: inst_stdcx_dot_r_mem
|
|
emit_stdcx_dot :: emit_stdcx_dot_r_mem
|
|
inst_stqcx_dot :: inst_stqcx_dot_r_mem
|
|
emit_stqcx_dot :: emit_stqcx_dot_r_mem
|
|
inst_addi :: inst_addi_r_rz_simm
|
|
emit_addi :: emit_addi_r_rz_simm
|
|
inst_addis :: inst_addis_r_rz_simm
|
|
emit_addis :: emit_addis_r_rz_simm
|
|
inst_addic :: inst_addic_r_r_simm
|
|
emit_addic :: emit_addic_r_r_simm
|
|
inst_addic_dot :: inst_addic_dot_r_r_simm
|
|
emit_addic_dot :: emit_addic_dot_r_r_simm
|
|
inst_subfic :: inst_subfic_r_r_simm
|
|
emit_subfic :: emit_subfic_r_r_simm
|
|
inst_addpcis :: inst_addpcis_r_simm
|
|
emit_addpcis :: emit_addpcis_r_simm
|
|
inst_add :: inst_add_r_r_r
|
|
emit_add :: emit_add_r_r_r
|
|
inst_add_dot :: inst_add_dot_r_r_r
|
|
emit_add_dot :: emit_add_dot_r_r_r
|
|
inst_add_o :: inst_add_o_r_r_r
|
|
emit_add_o :: emit_add_o_r_r_r
|
|
inst_add_o_dot :: inst_add_o_dot_r_r_r
|
|
emit_add_o_dot :: emit_add_o_dot_r_r_r
|
|
inst_addc :: inst_addc_r_r_r
|
|
emit_addc :: emit_addc_r_r_r
|
|
inst_addc_dot :: inst_addc_dot_r_r_r
|
|
emit_addc_dot :: emit_addc_dot_r_r_r
|
|
inst_addc_o :: inst_addc_o_r_r_r
|
|
emit_addc_o :: emit_addc_o_r_r_r
|
|
inst_addc_o_dot :: inst_addc_o_dot_r_r_r
|
|
emit_addc_o_dot :: emit_addc_o_dot_r_r_r
|
|
inst_adde :: inst_adde_r_r_r
|
|
emit_adde :: emit_adde_r_r_r
|
|
inst_adde_dot :: inst_adde_dot_r_r_r
|
|
emit_adde_dot :: emit_adde_dot_r_r_r
|
|
inst_adde_o :: inst_adde_o_r_r_r
|
|
emit_adde_o :: emit_adde_o_r_r_r
|
|
inst_adde_o_dot :: inst_adde_o_dot_r_r_r
|
|
emit_adde_o_dot :: emit_adde_o_dot_r_r_r
|
|
inst_addme :: inst_addme_r_r
|
|
emit_addme :: emit_addme_r_r
|
|
inst_addme_dot :: inst_addme_dot_r_r
|
|
emit_addme_dot :: emit_addme_dot_r_r
|
|
inst_addme_o :: inst_addme_o_r_r
|
|
emit_addme_o :: emit_addme_o_r_r
|
|
inst_addme_o_dot :: inst_addme_o_dot_r_r
|
|
emit_addme_o_dot :: emit_addme_o_dot_r_r
|
|
inst_addze :: inst_addze_r_r
|
|
emit_addze :: emit_addze_r_r
|
|
inst_addze_dot :: inst_addze_dot_r_r
|
|
emit_addze_dot :: emit_addze_dot_r_r
|
|
inst_addze_o :: inst_addze_o_r_r
|
|
emit_addze_o :: emit_addze_o_r_r
|
|
inst_addze_o_dot :: inst_addze_o_dot_r_r
|
|
emit_addze_o_dot :: emit_addze_o_dot_r_r
|
|
inst_addex :: inst_addex_r_r_r
|
|
emit_addex :: emit_addex_r_r_r
|
|
inst_subf :: inst_subf_r_r_r
|
|
emit_subf :: emit_subf_r_r_r
|
|
inst_subf_dot :: inst_subf_dot_r_r_r
|
|
emit_subf_dot :: emit_subf_dot_r_r_r
|
|
inst_subf_o :: inst_subf_o_r_r_r
|
|
emit_subf_o :: emit_subf_o_r_r_r
|
|
inst_subf_o_dot :: inst_subf_o_dot_r_r_r
|
|
emit_subf_o_dot :: emit_subf_o_dot_r_r_r
|
|
inst_subfc :: inst_subfc_r_r_r
|
|
emit_subfc :: emit_subfc_r_r_r
|
|
inst_subfc_dot :: inst_subfc_dot_r_r_r
|
|
emit_subfc_dot :: emit_subfc_dot_r_r_r
|
|
inst_subfc_o :: inst_subfc_o_r_r_r
|
|
emit_subfc_o :: emit_subfc_o_r_r_r
|
|
inst_subfc_o_dot :: inst_subfc_o_dot_r_r_r
|
|
emit_subfc_o_dot :: emit_subfc_o_dot_r_r_r
|
|
inst_subfe :: inst_subfe_r_r_r
|
|
emit_subfe :: emit_subfe_r_r_r
|
|
inst_subfe_dot :: inst_subfe_dot_r_r_r
|
|
emit_subfe_dot :: emit_subfe_dot_r_r_r
|
|
inst_subfe_o :: inst_subfe_o_r_r_r
|
|
emit_subfe_o :: emit_subfe_o_r_r_r
|
|
inst_subfe_o_dot :: inst_subfe_o_dot_r_r_r
|
|
emit_subfe_o_dot :: emit_subfe_o_dot_r_r_r
|
|
inst_subfme :: inst_subfme_r_r
|
|
emit_subfme :: emit_subfme_r_r
|
|
inst_subfme_dot :: inst_subfme_dot_r_r
|
|
emit_subfme_dot :: emit_subfme_dot_r_r
|
|
inst_subfme_o :: inst_subfme_o_r_r
|
|
emit_subfme_o :: emit_subfme_o_r_r
|
|
inst_subfme_o_dot :: inst_subfme_o_dot_r_r
|
|
emit_subfme_o_dot :: emit_subfme_o_dot_r_r
|
|
inst_subfze :: inst_subfze_r_r
|
|
emit_subfze :: emit_subfze_r_r
|
|
inst_subfze_dot :: inst_subfze_dot_r_r
|
|
emit_subfze_dot :: emit_subfze_dot_r_r
|
|
inst_subfze_o :: inst_subfze_o_r_r
|
|
emit_subfze_o :: emit_subfze_o_r_r
|
|
inst_subfze_o_dot :: inst_subfze_o_dot_r_r
|
|
emit_subfze_o_dot :: emit_subfze_o_dot_r_r
|
|
inst_neg :: inst_neg_r_r
|
|
emit_neg :: emit_neg_r_r
|
|
inst_neg_dot :: inst_neg_dot_r_r
|
|
emit_neg_dot :: emit_neg_dot_r_r
|
|
inst_neg_o :: inst_neg_o_r_r
|
|
emit_neg_o :: emit_neg_o_r_r
|
|
inst_neg_o_dot :: inst_neg_o_dot_r_r
|
|
emit_neg_o_dot :: emit_neg_o_dot_r_r
|
|
inst_mulli :: inst_mulli_r_rz_simm
|
|
emit_mulli :: emit_mulli_r_rz_simm
|
|
inst_mulhw :: inst_mulhw_r_r_r
|
|
emit_mulhw :: emit_mulhw_r_r_r
|
|
inst_mulhw_dot :: inst_mulhw_dot_r_r_r
|
|
emit_mulhw_dot :: emit_mulhw_dot_r_r_r
|
|
inst_mulhwu :: inst_mulhwu_r_r_r
|
|
emit_mulhwu :: emit_mulhwu_r_r_r
|
|
inst_mulhwu_dot :: inst_mulhwu_dot_r_r_r
|
|
emit_mulhwu_dot :: emit_mulhwu_dot_r_r_r
|
|
inst_mullw :: inst_mullw_r_r_r
|
|
emit_mullw :: emit_mullw_r_r_r
|
|
inst_mullw_dot :: inst_mullw_dot_r_r_r
|
|
emit_mullw_dot :: emit_mullw_dot_r_r_r
|
|
inst_mullw_o :: inst_mullw_o_r_r_r
|
|
emit_mullw_o :: emit_mullw_o_r_r_r
|
|
inst_mullw_o_dot :: inst_mullw_o_dot_r_r_r
|
|
emit_mullw_o_dot :: emit_mullw_o_dot_r_r_r
|
|
inst_mulld :: inst_mulld_r_r_r
|
|
emit_mulld :: emit_mulld_r_r_r
|
|
inst_mulld_dot :: inst_mulld_dot_r_r_r
|
|
emit_mulld_dot :: emit_mulld_dot_r_r_r
|
|
inst_mulld_o :: inst_mulld_o_r_r_r
|
|
emit_mulld_o :: emit_mulld_o_r_r_r
|
|
inst_mulld_o_dot :: inst_mulld_o_dot_r_r_r
|
|
emit_mulld_o_dot :: emit_mulld_o_dot_r_r_r
|
|
inst_mulhd :: inst_mulhd_r_r_r
|
|
emit_mulhd :: emit_mulhd_r_r_r
|
|
inst_mulhd_dot :: inst_mulhd_dot_r_r_r
|
|
emit_mulhd_dot :: emit_mulhd_dot_r_r_r
|
|
inst_mulhdu :: inst_mulhdu_r_r_r
|
|
emit_mulhdu :: emit_mulhdu_r_r_r
|
|
inst_mulhdu_dot :: inst_mulhdu_dot_r_r_r
|
|
emit_mulhdu_dot :: emit_mulhdu_dot_r_r_r
|
|
inst_maddld :: inst_maddld_r_r_r_r
|
|
emit_maddld :: emit_maddld_r_r_r_r
|
|
inst_maddhd :: inst_maddhd_r_r_r_r
|
|
emit_maddhd :: emit_maddhd_r_r_r_r
|
|
inst_maddhdu :: inst_maddhdu_r_r_r_r
|
|
emit_maddhdu :: emit_maddhdu_r_r_r_r
|
|
inst_divw :: inst_divw_r_r_r
|
|
emit_divw :: emit_divw_r_r_r
|
|
inst_divw_dot :: inst_divw_dot_r_r_r
|
|
emit_divw_dot :: emit_divw_dot_r_r_r
|
|
inst_divw_o :: inst_divw_o_r_r_r
|
|
emit_divw_o :: emit_divw_o_r_r_r
|
|
inst_divw_o_dot :: inst_divw_o_dot_r_r_r
|
|
emit_divw_o_dot :: emit_divw_o_dot_r_r_r
|
|
inst_divwu :: inst_divwu_r_r_r
|
|
emit_divwu :: emit_divwu_r_r_r
|
|
inst_divwu_dot :: inst_divwu_dot_r_r_r
|
|
emit_divwu_dot :: emit_divwu_dot_r_r_r
|
|
inst_divwu_o :: inst_divwu_o_r_r_r
|
|
emit_divwu_o :: emit_divwu_o_r_r_r
|
|
inst_divwu_o_dot :: inst_divwu_o_dot_r_r_r
|
|
emit_divwu_o_dot :: emit_divwu_o_dot_r_r_r
|
|
inst_divd :: inst_divd_r_r_r
|
|
emit_divd :: emit_divd_r_r_r
|
|
inst_divd_dot :: inst_divd_dot_r_r_r
|
|
emit_divd_dot :: emit_divd_dot_r_r_r
|
|
inst_divd_o :: inst_divd_o_r_r_r
|
|
emit_divd_o :: emit_divd_o_r_r_r
|
|
inst_divd_o_dot :: inst_divd_o_dot_r_r_r
|
|
emit_divd_o_dot :: emit_divd_o_dot_r_r_r
|
|
inst_divdu :: inst_divdu_r_r_r
|
|
emit_divdu :: emit_divdu_r_r_r
|
|
inst_divdu_dot :: inst_divdu_dot_r_r_r
|
|
emit_divdu_dot :: emit_divdu_dot_r_r_r
|
|
inst_divdu_o :: inst_divdu_o_r_r_r
|
|
emit_divdu_o :: emit_divdu_o_r_r_r
|
|
inst_divdu_o_dot :: inst_divdu_o_dot_r_r_r
|
|
emit_divdu_o_dot :: emit_divdu_o_dot_r_r_r
|
|
inst_divwe :: inst_divwe_r_r_r
|
|
emit_divwe :: emit_divwe_r_r_r
|
|
inst_divwe_dot :: inst_divwe_dot_r_r_r
|
|
emit_divwe_dot :: emit_divwe_dot_r_r_r
|
|
inst_divwe_o :: inst_divwe_o_r_r_r
|
|
emit_divwe_o :: emit_divwe_o_r_r_r
|
|
inst_divwe_o_dot :: inst_divwe_o_dot_r_r_r
|
|
emit_divwe_o_dot :: emit_divwe_o_dot_r_r_r
|
|
inst_divweu :: inst_divweu_r_r_r
|
|
emit_divweu :: emit_divweu_r_r_r
|
|
inst_divweu_dot :: inst_divweu_dot_r_r_r
|
|
emit_divweu_dot :: emit_divweu_dot_r_r_r
|
|
inst_divweu_o :: inst_divweu_o_r_r_r
|
|
emit_divweu_o :: emit_divweu_o_r_r_r
|
|
inst_divweu_o_dot :: inst_divweu_o_dot_r_r_r
|
|
emit_divweu_o_dot :: emit_divweu_o_dot_r_r_r
|
|
inst_divde :: inst_divde_r_r_r
|
|
emit_divde :: emit_divde_r_r_r
|
|
inst_divde_dot :: inst_divde_dot_r_r_r
|
|
emit_divde_dot :: emit_divde_dot_r_r_r
|
|
inst_divde_o :: inst_divde_o_r_r_r
|
|
emit_divde_o :: emit_divde_o_r_r_r
|
|
inst_divde_o_dot :: inst_divde_o_dot_r_r_r
|
|
emit_divde_o_dot :: emit_divde_o_dot_r_r_r
|
|
inst_divdeu :: inst_divdeu_r_r_r
|
|
emit_divdeu :: emit_divdeu_r_r_r
|
|
inst_divdeu_dot :: inst_divdeu_dot_r_r_r
|
|
emit_divdeu_dot :: emit_divdeu_dot_r_r_r
|
|
inst_divdeu_o :: inst_divdeu_o_r_r_r
|
|
emit_divdeu_o :: emit_divdeu_o_r_r_r
|
|
inst_divdeu_o_dot :: inst_divdeu_o_dot_r_r_r
|
|
emit_divdeu_o_dot :: emit_divdeu_o_dot_r_r_r
|
|
inst_modsw :: inst_modsw_r_r_r
|
|
emit_modsw :: emit_modsw_r_r_r
|
|
inst_moduw :: inst_moduw_r_r_r
|
|
emit_moduw :: emit_moduw_r_r_r
|
|
inst_modsd :: inst_modsd_r_r_r
|
|
emit_modsd :: emit_modsd_r_r_r
|
|
inst_modud :: inst_modud_r_r_r
|
|
emit_modud :: emit_modud_r_r_r
|
|
inst_twi :: inst_twi_imm_r_simm
|
|
emit_twi :: emit_twi_imm_r_simm
|
|
inst_tw :: inst_tw_imm_r_r
|
|
emit_tw :: emit_tw_imm_r_r
|
|
inst_tdi :: inst_tdi_imm_r_simm
|
|
emit_tdi :: emit_tdi_imm_r_simm
|
|
inst_td :: inst_td_imm_r_r
|
|
emit_td :: emit_td_imm_r_r
|
|
inst_andi_dot :: inst_andi_dot_r_r_uimm
|
|
emit_andi_dot :: emit_andi_dot_r_r_uimm
|
|
inst_andis_dot :: inst_andis_dot_r_r_uimm
|
|
emit_andis_dot :: emit_andis_dot_r_r_uimm
|
|
inst_ori :: inst_ori_r_r_uimm
|
|
emit_ori :: emit_ori_r_r_uimm
|
|
inst_oris :: inst_oris_r_r_uimm
|
|
emit_oris :: emit_oris_r_r_uimm
|
|
inst_xori :: inst_xori_r_r_uimm
|
|
emit_xori :: emit_xori_r_r_uimm
|
|
inst_xoris :: inst_xoris_r_r_uimm
|
|
emit_xoris :: emit_xoris_r_r_uimm
|
|
inst_and :: inst_and_r_r_r
|
|
emit_and :: emit_and_r_r_r
|
|
inst_and_dot :: inst_and_dot_r_r_r
|
|
emit_and_dot :: emit_and_dot_r_r_r
|
|
inst_or :: inst_or_r_r_r
|
|
emit_or :: emit_or_r_r_r
|
|
inst_or_dot :: inst_or_dot_r_r_r
|
|
emit_or_dot :: emit_or_dot_r_r_r
|
|
inst_xor :: inst_xor_r_r_r
|
|
emit_xor :: emit_xor_r_r_r
|
|
inst_xor_dot :: inst_xor_dot_r_r_r
|
|
emit_xor_dot :: emit_xor_dot_r_r_r
|
|
inst_nand :: inst_nand_r_r_r
|
|
emit_nand :: emit_nand_r_r_r
|
|
inst_nand_dot :: inst_nand_dot_r_r_r
|
|
emit_nand_dot :: emit_nand_dot_r_r_r
|
|
inst_nor :: inst_nor_r_r_r
|
|
emit_nor :: emit_nor_r_r_r
|
|
inst_nor_dot :: inst_nor_dot_r_r_r
|
|
emit_nor_dot :: emit_nor_dot_r_r_r
|
|
inst_eqv :: inst_eqv_r_r_r
|
|
emit_eqv :: emit_eqv_r_r_r
|
|
inst_eqv_dot :: inst_eqv_dot_r_r_r
|
|
emit_eqv_dot :: emit_eqv_dot_r_r_r
|
|
inst_andc :: inst_andc_r_r_r
|
|
emit_andc :: emit_andc_r_r_r
|
|
inst_andc_dot :: inst_andc_dot_r_r_r
|
|
emit_andc_dot :: emit_andc_dot_r_r_r
|
|
inst_orc :: inst_orc_r_r_r
|
|
emit_orc :: emit_orc_r_r_r
|
|
inst_orc_dot :: inst_orc_dot_r_r_r
|
|
emit_orc_dot :: emit_orc_dot_r_r_r
|
|
inst_extsb :: inst_extsb_r_r
|
|
emit_extsb :: emit_extsb_r_r
|
|
inst_extsb_dot :: inst_extsb_dot_r_r
|
|
emit_extsb_dot :: emit_extsb_dot_r_r
|
|
inst_extsh :: inst_extsh_r_r
|
|
emit_extsh :: emit_extsh_r_r
|
|
inst_extsh_dot :: inst_extsh_dot_r_r
|
|
emit_extsh_dot :: emit_extsh_dot_r_r
|
|
inst_extsw :: inst_extsw_r_r
|
|
emit_extsw :: emit_extsw_r_r
|
|
inst_extsw_dot :: inst_extsw_dot_r_r
|
|
emit_extsw_dot :: emit_extsw_dot_r_r
|
|
inst_cntlzw :: inst_cntlzw_r_r
|
|
emit_cntlzw :: emit_cntlzw_r_r
|
|
inst_cntlzw_dot :: inst_cntlzw_dot_r_r
|
|
emit_cntlzw_dot :: emit_cntlzw_dot_r_r
|
|
inst_cntlzd :: inst_cntlzd_r_r
|
|
emit_cntlzd :: emit_cntlzd_r_r
|
|
inst_cntlzd_dot :: inst_cntlzd_dot_r_r
|
|
emit_cntlzd_dot :: emit_cntlzd_dot_r_r
|
|
inst_cnttzw :: inst_cnttzw_r_r
|
|
emit_cnttzw :: emit_cnttzw_r_r
|
|
inst_cnttzw_dot :: inst_cnttzw_dot_r_r
|
|
emit_cnttzw_dot :: emit_cnttzw_dot_r_r
|
|
inst_cnttzd :: inst_cnttzd_r_r
|
|
emit_cnttzd :: emit_cnttzd_r_r
|
|
inst_cnttzd_dot :: inst_cnttzd_dot_r_r
|
|
emit_cnttzd_dot :: emit_cnttzd_dot_r_r
|
|
inst_popcntb :: inst_popcntb_r_r
|
|
emit_popcntb :: emit_popcntb_r_r
|
|
inst_popcntw :: inst_popcntw_r_r
|
|
emit_popcntw :: emit_popcntw_r_r
|
|
inst_popcntd :: inst_popcntd_r_r
|
|
emit_popcntd :: emit_popcntd_r_r
|
|
inst_prtyw :: inst_prtyw_r_r
|
|
emit_prtyw :: emit_prtyw_r_r
|
|
inst_prtyd :: inst_prtyd_r_r
|
|
emit_prtyd :: emit_prtyd_r_r
|
|
inst_bpermd :: inst_bpermd_r_r_r
|
|
emit_bpermd :: emit_bpermd_r_r_r
|
|
inst_cmpb :: inst_cmpb_r_r_r
|
|
emit_cmpb :: emit_cmpb_r_r_r
|
|
inst_slw :: inst_slw_r_r_r
|
|
emit_slw :: emit_slw_r_r_r
|
|
inst_slw_dot :: inst_slw_dot_r_r_r
|
|
emit_slw_dot :: emit_slw_dot_r_r_r
|
|
inst_srw :: inst_srw_r_r_r
|
|
emit_srw :: emit_srw_r_r_r
|
|
inst_srw_dot :: inst_srw_dot_r_r_r
|
|
emit_srw_dot :: emit_srw_dot_r_r_r
|
|
inst_sraw :: inst_sraw_r_r_r
|
|
emit_sraw :: emit_sraw_r_r_r
|
|
inst_sraw_dot :: inst_sraw_dot_r_r_r
|
|
emit_sraw_dot :: emit_sraw_dot_r_r_r
|
|
inst_srawi :: inst_srawi_r_r_imm
|
|
emit_srawi :: emit_srawi_r_r_imm
|
|
inst_srawi_dot :: inst_srawi_dot_r_r_imm
|
|
emit_srawi_dot :: emit_srawi_dot_r_r_imm
|
|
inst_sld :: inst_sld_r_r_r
|
|
emit_sld :: emit_sld_r_r_r
|
|
inst_sld_dot :: inst_sld_dot_r_r_r
|
|
emit_sld_dot :: emit_sld_dot_r_r_r
|
|
inst_srd :: inst_srd_r_r_r
|
|
emit_srd :: emit_srd_r_r_r
|
|
inst_srd_dot :: inst_srd_dot_r_r_r
|
|
emit_srd_dot :: emit_srd_dot_r_r_r
|
|
inst_srad :: inst_srad_r_r_r
|
|
emit_srad :: emit_srad_r_r_r
|
|
inst_srad_dot :: inst_srad_dot_r_r_r
|
|
emit_srad_dot :: emit_srad_dot_r_r_r
|
|
inst_sradi :: inst_sradi_r_r_imm
|
|
emit_sradi :: emit_sradi_r_r_imm
|
|
inst_sradi_dot :: inst_sradi_dot_r_r_imm
|
|
emit_sradi_dot :: emit_sradi_dot_r_r_imm
|
|
inst_rlwinm :: inst_rlwinm_r_r_imm_imm
|
|
emit_rlwinm :: emit_rlwinm_r_r_imm_imm
|
|
inst_rlwinm_dot :: inst_rlwinm_dot_r_r_imm_imm
|
|
emit_rlwinm_dot :: emit_rlwinm_dot_r_r_imm_imm
|
|
inst_rlwnm :: inst_rlwnm_r_r_r_imm
|
|
emit_rlwnm :: emit_rlwnm_r_r_r_imm
|
|
inst_rlwnm_dot :: inst_rlwnm_dot_r_r_r_imm
|
|
emit_rlwnm_dot :: emit_rlwnm_dot_r_r_r_imm
|
|
inst_rlwimi :: inst_rlwimi_r_r_imm_imm
|
|
emit_rlwimi :: emit_rlwimi_r_r_imm_imm
|
|
inst_rlwimi_dot :: inst_rlwimi_dot_r_r_imm_imm
|
|
emit_rlwimi_dot :: emit_rlwimi_dot_r_r_imm_imm
|
|
inst_rldicl :: inst_rldicl_r_r_imm_imm
|
|
emit_rldicl :: emit_rldicl_r_r_imm_imm
|
|
inst_rldicl_dot :: inst_rldicl_dot_r_r_imm_imm
|
|
emit_rldicl_dot :: emit_rldicl_dot_r_r_imm_imm
|
|
inst_rldicr :: inst_rldicr_r_r_imm_imm
|
|
emit_rldicr :: emit_rldicr_r_r_imm_imm
|
|
inst_rldicr_dot :: inst_rldicr_dot_r_r_imm_imm
|
|
emit_rldicr_dot :: emit_rldicr_dot_r_r_imm_imm
|
|
inst_rldic :: inst_rldic_r_r_imm_imm
|
|
emit_rldic :: emit_rldic_r_r_imm_imm
|
|
inst_rldic_dot :: inst_rldic_dot_r_r_imm_imm
|
|
emit_rldic_dot :: emit_rldic_dot_r_r_imm_imm
|
|
inst_rldimi :: inst_rldimi_r_r_imm_imm
|
|
emit_rldimi :: emit_rldimi_r_r_imm_imm
|
|
inst_rldimi_dot :: inst_rldimi_dot_r_r_imm_imm
|
|
emit_rldimi_dot :: emit_rldimi_dot_r_r_imm_imm
|
|
inst_rldcl :: inst_rldcl_r_r_r_imm
|
|
emit_rldcl :: emit_rldcl_r_r_r_imm
|
|
inst_rldcl_dot :: inst_rldcl_dot_r_r_r_imm
|
|
emit_rldcl_dot :: emit_rldcl_dot_r_r_r_imm
|
|
inst_rldcr :: inst_rldcr_r_r_r_imm
|
|
emit_rldcr :: emit_rldcr_r_r_r_imm
|
|
inst_rldcr_dot :: inst_rldcr_dot_r_r_r_imm
|
|
emit_rldcr_dot :: emit_rldcr_dot_r_r_r_imm
|
|
inst_cmpi :: inst_cmpi_crf_imm_r_simm
|
|
emit_cmpi :: emit_cmpi_crf_imm_r_simm
|
|
inst_cmpli :: inst_cmpli_crf_imm_r_uimm
|
|
emit_cmpli :: emit_cmpli_crf_imm_r_uimm
|
|
inst_cmp :: inst_cmp_crf_imm_r_r
|
|
emit_cmp :: emit_cmp_crf_imm_r_r
|
|
inst_cmpl :: inst_cmpl_crf_imm_r_r
|
|
emit_cmpl :: emit_cmpl_crf_imm_r_r
|
|
inst_cmprb :: inst_cmprb_crf_imm_r_r
|
|
emit_cmprb :: emit_cmprb_crf_imm_r_r
|
|
inst_cmpeqb :: inst_cmpeqb_crf_r_r
|
|
emit_cmpeqb :: emit_cmpeqb_crf_r_r
|
|
inst_fadd :: inst_fadd_fr_fr_fr
|
|
emit_fadd :: emit_fadd_fr_fr_fr
|
|
inst_fadd_dot :: inst_fadd_dot_fr_fr_fr
|
|
emit_fadd_dot :: emit_fadd_dot_fr_fr_fr
|
|
inst_fadds :: inst_fadds_fr_fr_fr
|
|
emit_fadds :: emit_fadds_fr_fr_fr
|
|
inst_fadds_dot :: inst_fadds_dot_fr_fr_fr
|
|
emit_fadds_dot :: emit_fadds_dot_fr_fr_fr
|
|
inst_fsub :: inst_fsub_fr_fr_fr
|
|
emit_fsub :: emit_fsub_fr_fr_fr
|
|
inst_fsub_dot :: inst_fsub_dot_fr_fr_fr
|
|
emit_fsub_dot :: emit_fsub_dot_fr_fr_fr
|
|
inst_fsubs :: inst_fsubs_fr_fr_fr
|
|
emit_fsubs :: emit_fsubs_fr_fr_fr
|
|
inst_fsubs_dot :: inst_fsubs_dot_fr_fr_fr
|
|
emit_fsubs_dot :: emit_fsubs_dot_fr_fr_fr
|
|
inst_fmul :: inst_fmul_fr_fr_fr
|
|
emit_fmul :: emit_fmul_fr_fr_fr
|
|
inst_fmul_dot :: inst_fmul_dot_fr_fr_fr
|
|
emit_fmul_dot :: emit_fmul_dot_fr_fr_fr
|
|
inst_fmuls :: inst_fmuls_fr_fr_fr
|
|
emit_fmuls :: emit_fmuls_fr_fr_fr
|
|
inst_fmuls_dot :: inst_fmuls_dot_fr_fr_fr
|
|
emit_fmuls_dot :: emit_fmuls_dot_fr_fr_fr
|
|
inst_fdiv :: inst_fdiv_fr_fr_fr
|
|
emit_fdiv :: emit_fdiv_fr_fr_fr
|
|
inst_fdiv_dot :: inst_fdiv_dot_fr_fr_fr
|
|
emit_fdiv_dot :: emit_fdiv_dot_fr_fr_fr
|
|
inst_fdivs :: inst_fdivs_fr_fr_fr
|
|
emit_fdivs :: emit_fdivs_fr_fr_fr
|
|
inst_fdivs_dot :: inst_fdivs_dot_fr_fr_fr
|
|
emit_fdivs_dot :: emit_fdivs_dot_fr_fr_fr
|
|
inst_fsqrt :: inst_fsqrt_fr_fr
|
|
emit_fsqrt :: emit_fsqrt_fr_fr
|
|
inst_fsqrt_dot :: inst_fsqrt_dot_fr_fr
|
|
emit_fsqrt_dot :: emit_fsqrt_dot_fr_fr
|
|
inst_fsqrts :: inst_fsqrts_fr_fr
|
|
emit_fsqrts :: emit_fsqrts_fr_fr
|
|
inst_fsqrts_dot :: inst_fsqrts_dot_fr_fr
|
|
emit_fsqrts_dot :: emit_fsqrts_dot_fr_fr
|
|
inst_fre :: inst_fre_fr_fr
|
|
emit_fre :: emit_fre_fr_fr
|
|
inst_fre_dot :: inst_fre_dot_fr_fr
|
|
emit_fre_dot :: emit_fre_dot_fr_fr
|
|
inst_fres :: inst_fres_fr_fr
|
|
emit_fres :: emit_fres_fr_fr
|
|
inst_fres_dot :: inst_fres_dot_fr_fr
|
|
emit_fres_dot :: emit_fres_dot_fr_fr
|
|
inst_frsqrte :: inst_frsqrte_fr_fr
|
|
emit_frsqrte :: emit_frsqrte_fr_fr
|
|
inst_frsqrte_dot :: inst_frsqrte_dot_fr_fr
|
|
emit_frsqrte_dot :: emit_frsqrte_dot_fr_fr
|
|
inst_frsqrtes :: inst_frsqrtes_fr_fr
|
|
emit_frsqrtes :: emit_frsqrtes_fr_fr
|
|
inst_frsqrtes_dot :: inst_frsqrtes_dot_fr_fr
|
|
emit_frsqrtes_dot :: emit_frsqrtes_dot_fr_fr
|
|
inst_fmadd :: inst_fmadd_fr_fr_fr_fr
|
|
emit_fmadd :: emit_fmadd_fr_fr_fr_fr
|
|
inst_fmadd_dot :: inst_fmadd_dot_fr_fr_fr_fr
|
|
emit_fmadd_dot :: emit_fmadd_dot_fr_fr_fr_fr
|
|
inst_fmadds :: inst_fmadds_fr_fr_fr_fr
|
|
emit_fmadds :: emit_fmadds_fr_fr_fr_fr
|
|
inst_fmadds_dot :: inst_fmadds_dot_fr_fr_fr_fr
|
|
emit_fmadds_dot :: emit_fmadds_dot_fr_fr_fr_fr
|
|
inst_fmsub :: inst_fmsub_fr_fr_fr_fr
|
|
emit_fmsub :: emit_fmsub_fr_fr_fr_fr
|
|
inst_fmsub_dot :: inst_fmsub_dot_fr_fr_fr_fr
|
|
emit_fmsub_dot :: emit_fmsub_dot_fr_fr_fr_fr
|
|
inst_fmsubs :: inst_fmsubs_fr_fr_fr_fr
|
|
emit_fmsubs :: emit_fmsubs_fr_fr_fr_fr
|
|
inst_fmsubs_dot :: inst_fmsubs_dot_fr_fr_fr_fr
|
|
emit_fmsubs_dot :: emit_fmsubs_dot_fr_fr_fr_fr
|
|
inst_fnmadd :: inst_fnmadd_fr_fr_fr_fr
|
|
emit_fnmadd :: emit_fnmadd_fr_fr_fr_fr
|
|
inst_fnmadd_dot :: inst_fnmadd_dot_fr_fr_fr_fr
|
|
emit_fnmadd_dot :: emit_fnmadd_dot_fr_fr_fr_fr
|
|
inst_fnmadds :: inst_fnmadds_fr_fr_fr_fr
|
|
emit_fnmadds :: emit_fnmadds_fr_fr_fr_fr
|
|
inst_fnmadds_dot :: inst_fnmadds_dot_fr_fr_fr_fr
|
|
emit_fnmadds_dot :: emit_fnmadds_dot_fr_fr_fr_fr
|
|
inst_fnmsub :: inst_fnmsub_fr_fr_fr_fr
|
|
emit_fnmsub :: emit_fnmsub_fr_fr_fr_fr
|
|
inst_fnmsub_dot :: inst_fnmsub_dot_fr_fr_fr_fr
|
|
emit_fnmsub_dot :: emit_fnmsub_dot_fr_fr_fr_fr
|
|
inst_fnmsubs :: inst_fnmsubs_fr_fr_fr_fr
|
|
emit_fnmsubs :: emit_fnmsubs_fr_fr_fr_fr
|
|
inst_fnmsubs_dot :: inst_fnmsubs_dot_fr_fr_fr_fr
|
|
emit_fnmsubs_dot :: emit_fnmsubs_dot_fr_fr_fr_fr
|
|
inst_fsel :: inst_fsel_fr_fr_fr_fr
|
|
emit_fsel :: emit_fsel_fr_fr_fr_fr
|
|
inst_fsel_dot :: inst_fsel_dot_fr_fr_fr_fr
|
|
emit_fsel_dot :: emit_fsel_dot_fr_fr_fr_fr
|
|
inst_fcpsgn :: inst_fcpsgn_fr_fr_fr
|
|
emit_fcpsgn :: emit_fcpsgn_fr_fr_fr
|
|
inst_fcpsgn_dot :: inst_fcpsgn_dot_fr_fr_fr
|
|
emit_fcpsgn_dot :: emit_fcpsgn_dot_fr_fr_fr
|
|
inst_fneg :: inst_fneg_fr_fr
|
|
emit_fneg :: emit_fneg_fr_fr
|
|
inst_fneg_dot :: inst_fneg_dot_fr_fr
|
|
emit_fneg_dot :: emit_fneg_dot_fr_fr
|
|
inst_fabs :: inst_fabs_fr_fr
|
|
emit_fabs :: emit_fabs_fr_fr
|
|
inst_fabs_dot :: inst_fabs_dot_fr_fr
|
|
emit_fabs_dot :: emit_fabs_dot_fr_fr
|
|
inst_fnabs :: inst_fnabs_fr_fr
|
|
emit_fnabs :: emit_fnabs_fr_fr
|
|
inst_fnabs_dot :: inst_fnabs_dot_fr_fr
|
|
emit_fnabs_dot :: emit_fnabs_dot_fr_fr
|
|
inst_fmr :: inst_fmr_fr_fr
|
|
emit_fmr :: emit_fmr_fr_fr
|
|
inst_fmr_dot :: inst_fmr_dot_fr_fr
|
|
emit_fmr_dot :: emit_fmr_dot_fr_fr
|
|
inst_frsp :: inst_frsp_fr_fr
|
|
emit_frsp :: emit_frsp_fr_fr
|
|
inst_frsp_dot :: inst_frsp_dot_fr_fr
|
|
emit_frsp_dot :: emit_frsp_dot_fr_fr
|
|
inst_fctid :: inst_fctid_fr_fr
|
|
emit_fctid :: emit_fctid_fr_fr
|
|
inst_fctid_dot :: inst_fctid_dot_fr_fr
|
|
emit_fctid_dot :: emit_fctid_dot_fr_fr
|
|
inst_fctidu :: inst_fctidu_fr_fr
|
|
emit_fctidu :: emit_fctidu_fr_fr
|
|
inst_fctidu_dot :: inst_fctidu_dot_fr_fr
|
|
emit_fctidu_dot :: emit_fctidu_dot_fr_fr
|
|
inst_fctidz :: inst_fctidz_fr_fr
|
|
emit_fctidz :: emit_fctidz_fr_fr
|
|
inst_fctidz_dot :: inst_fctidz_dot_fr_fr
|
|
emit_fctidz_dot :: emit_fctidz_dot_fr_fr
|
|
inst_fctiduz :: inst_fctiduz_fr_fr
|
|
emit_fctiduz :: emit_fctiduz_fr_fr
|
|
inst_fctiduz_dot :: inst_fctiduz_dot_fr_fr
|
|
emit_fctiduz_dot :: emit_fctiduz_dot_fr_fr
|
|
inst_fctiw :: inst_fctiw_fr_fr
|
|
emit_fctiw :: emit_fctiw_fr_fr
|
|
inst_fctiw_dot :: inst_fctiw_dot_fr_fr
|
|
emit_fctiw_dot :: emit_fctiw_dot_fr_fr
|
|
inst_fctiwu :: inst_fctiwu_fr_fr
|
|
emit_fctiwu :: emit_fctiwu_fr_fr
|
|
inst_fctiwu_dot :: inst_fctiwu_dot_fr_fr
|
|
emit_fctiwu_dot :: emit_fctiwu_dot_fr_fr
|
|
inst_fctiwz :: inst_fctiwz_fr_fr
|
|
emit_fctiwz :: emit_fctiwz_fr_fr
|
|
inst_fctiwz_dot :: inst_fctiwz_dot_fr_fr
|
|
emit_fctiwz_dot :: emit_fctiwz_dot_fr_fr
|
|
inst_fctiwuz :: inst_fctiwuz_fr_fr
|
|
emit_fctiwuz :: emit_fctiwuz_fr_fr
|
|
inst_fctiwuz_dot :: inst_fctiwuz_dot_fr_fr
|
|
emit_fctiwuz_dot :: emit_fctiwuz_dot_fr_fr
|
|
inst_fcfid :: inst_fcfid_fr_fr
|
|
emit_fcfid :: emit_fcfid_fr_fr
|
|
inst_fcfid_dot :: inst_fcfid_dot_fr_fr
|
|
emit_fcfid_dot :: emit_fcfid_dot_fr_fr
|
|
inst_fcfidu :: inst_fcfidu_fr_fr
|
|
emit_fcfidu :: emit_fcfidu_fr_fr
|
|
inst_fcfidu_dot :: inst_fcfidu_dot_fr_fr
|
|
emit_fcfidu_dot :: emit_fcfidu_dot_fr_fr
|
|
inst_fcfids :: inst_fcfids_fr_fr
|
|
emit_fcfids :: emit_fcfids_fr_fr
|
|
inst_fcfids_dot :: inst_fcfids_dot_fr_fr
|
|
emit_fcfids_dot :: emit_fcfids_dot_fr_fr
|
|
inst_fcfidus :: inst_fcfidus_fr_fr
|
|
emit_fcfidus :: emit_fcfidus_fr_fr
|
|
inst_fcfidus_dot :: inst_fcfidus_dot_fr_fr
|
|
emit_fcfidus_dot :: emit_fcfidus_dot_fr_fr
|
|
inst_frin :: inst_frin_fr_fr
|
|
emit_frin :: emit_frin_fr_fr
|
|
inst_frin_dot :: inst_frin_dot_fr_fr
|
|
emit_frin_dot :: emit_frin_dot_fr_fr
|
|
inst_friz :: inst_friz_fr_fr
|
|
emit_friz :: emit_friz_fr_fr
|
|
inst_friz_dot :: inst_friz_dot_fr_fr
|
|
emit_friz_dot :: emit_friz_dot_fr_fr
|
|
inst_frip :: inst_frip_fr_fr
|
|
emit_frip :: emit_frip_fr_fr
|
|
inst_frip_dot :: inst_frip_dot_fr_fr
|
|
emit_frip_dot :: emit_frip_dot_fr_fr
|
|
inst_frim :: inst_frim_fr_fr
|
|
emit_frim :: emit_frim_fr_fr
|
|
inst_frim_dot :: inst_frim_dot_fr_fr
|
|
emit_frim_dot :: emit_frim_dot_fr_fr
|
|
inst_fcmpu :: inst_fcmpu_crf_fr_fr
|
|
emit_fcmpu :: emit_fcmpu_crf_fr_fr
|
|
inst_fcmpo :: inst_fcmpo_crf_fr_fr
|
|
emit_fcmpo :: emit_fcmpo_crf_fr_fr
|
|
inst_ftdiv :: inst_ftdiv_crf_fr_fr
|
|
emit_ftdiv :: emit_ftdiv_crf_fr_fr
|
|
inst_ftsqrt :: inst_ftsqrt_crf_fr
|
|
emit_ftsqrt :: emit_ftsqrt_crf_fr
|
|
inst_fmrgew :: inst_fmrgew_fr_fr_fr
|
|
emit_fmrgew :: emit_fmrgew_fr_fr_fr
|
|
inst_fmrgow :: inst_fmrgow_fr_fr_fr
|
|
emit_fmrgow :: emit_fmrgow_fr_fr_fr
|
|
inst_lfs :: inst_lfs_fr_mem
|
|
emit_lfs :: emit_lfs_fr_mem
|
|
inst_lfsu :: inst_lfsu_fr_mem
|
|
emit_lfsu :: emit_lfsu_fr_mem
|
|
inst_lfsx :: inst_lfsx_fr_mem
|
|
emit_lfsx :: emit_lfsx_fr_mem
|
|
inst_lfsux :: inst_lfsux_fr_mem
|
|
emit_lfsux :: emit_lfsux_fr_mem
|
|
inst_lfd :: inst_lfd_fr_mem
|
|
emit_lfd :: emit_lfd_fr_mem
|
|
inst_lfdu :: inst_lfdu_fr_mem
|
|
emit_lfdu :: emit_lfdu_fr_mem
|
|
inst_lfdx :: inst_lfdx_fr_mem
|
|
emit_lfdx :: emit_lfdx_fr_mem
|
|
inst_lfdux :: inst_lfdux_fr_mem
|
|
emit_lfdux :: emit_lfdux_fr_mem
|
|
inst_lfiwax :: inst_lfiwax_fr_mem
|
|
emit_lfiwax :: emit_lfiwax_fr_mem
|
|
inst_lfiwzx :: inst_lfiwzx_fr_mem
|
|
emit_lfiwzx :: emit_lfiwzx_fr_mem
|
|
inst_lfdp :: inst_lfdp_fr_mem
|
|
emit_lfdp :: emit_lfdp_fr_mem
|
|
inst_lfdpx :: inst_lfdpx_fr_mem
|
|
emit_lfdpx :: emit_lfdpx_fr_mem
|
|
inst_stfs :: inst_stfs_fr_mem
|
|
emit_stfs :: emit_stfs_fr_mem
|
|
inst_stfsu :: inst_stfsu_fr_mem
|
|
emit_stfsu :: emit_stfsu_fr_mem
|
|
inst_stfsx :: inst_stfsx_fr_mem
|
|
emit_stfsx :: emit_stfsx_fr_mem
|
|
inst_stfsux :: inst_stfsux_fr_mem
|
|
emit_stfsux :: emit_stfsux_fr_mem
|
|
inst_stfd :: inst_stfd_fr_mem
|
|
emit_stfd :: emit_stfd_fr_mem
|
|
inst_stfdu :: inst_stfdu_fr_mem
|
|
emit_stfdu :: emit_stfdu_fr_mem
|
|
inst_stfdx :: inst_stfdx_fr_mem
|
|
emit_stfdx :: emit_stfdx_fr_mem
|
|
inst_stfdux :: inst_stfdux_fr_mem
|
|
emit_stfdux :: emit_stfdux_fr_mem
|
|
inst_stfiwx :: inst_stfiwx_fr_mem
|
|
emit_stfiwx :: emit_stfiwx_fr_mem
|
|
inst_stfdp :: inst_stfdp_fr_mem
|
|
emit_stfdp :: emit_stfdp_fr_mem
|
|
inst_stfdpx :: inst_stfdpx_fr_mem
|
|
emit_stfdpx :: emit_stfdpx_fr_mem
|
|
inst_mffs :: inst_mffs_fr
|
|
emit_mffs :: emit_mffs_fr
|
|
inst_mffs_dot :: inst_mffs_dot_fr
|
|
emit_mffs_dot :: emit_mffs_dot_fr
|
|
inst_mcrfs :: inst_mcrfs_crf_crf
|
|
emit_mcrfs :: emit_mcrfs_crf_crf
|
|
inst_mtfsb0 :: inst_mtfsb0_crb
|
|
emit_mtfsb0 :: emit_mtfsb0_crb
|
|
inst_mtfsb0_dot :: inst_mtfsb0_dot_crb
|
|
emit_mtfsb0_dot :: emit_mtfsb0_dot_crb
|
|
inst_mtfsb1 :: inst_mtfsb1_crb
|
|
emit_mtfsb1 :: emit_mtfsb1_crb
|
|
inst_mtfsb1_dot :: inst_mtfsb1_dot_crb
|
|
emit_mtfsb1_dot :: emit_mtfsb1_dot_crb
|
|
inst_mtfsfi :: inst_mtfsfi_crf_imm
|
|
emit_mtfsfi :: emit_mtfsfi_crf_imm
|
|
inst_mtfsfi_dot :: inst_mtfsfi_dot_crf_imm
|
|
emit_mtfsfi_dot :: emit_mtfsfi_dot_crf_imm
|
|
inst_mtfsf :: inst_mtfsf_imm_fr
|
|
emit_mtfsf :: emit_mtfsf_imm_fr
|
|
inst_mtfsf_dot :: inst_mtfsf_dot_imm_fr
|
|
emit_mtfsf_dot :: emit_mtfsf_dot_imm_fr
|
|
inst_mfspr :: inst_mfspr_r_spr
|
|
emit_mfspr :: emit_mfspr_r_spr
|
|
inst_mtspr :: inst_mtspr_spr_r
|
|
emit_mtspr :: emit_mtspr_spr_r
|
|
inst_mftb :: inst_mftb_r_spr
|
|
emit_mftb :: emit_mftb_r_spr
|
|
inst_mfcr :: inst_mfcr_r
|
|
emit_mfcr :: emit_mfcr_r
|
|
inst_mtcrf :: inst_mtcrf_imm_r
|
|
emit_mtcrf :: emit_mtcrf_imm_r
|
|
inst_mtocrf :: inst_mtocrf_imm_r
|
|
emit_mtocrf :: emit_mtocrf_imm_r
|
|
inst_mfocrf :: inst_mfocrf_r_imm
|
|
emit_mfocrf :: emit_mfocrf_r_imm
|
|
inst_mtmsr :: inst_mtmsr_r
|
|
emit_mtmsr :: emit_mtmsr_r
|
|
inst_mfmsr :: inst_mfmsr_r
|
|
emit_mfmsr :: emit_mfmsr_r
|
|
inst_mtmsrd :: inst_mtmsrd_r
|
|
emit_mtmsrd :: emit_mtmsrd_r
|
|
inst_sc_hv :: inst_sc_hv_imm
|
|
emit_sc_hv :: emit_sc_hv_imm
|
|
inst_rfi :: inst_rfi_none
|
|
emit_rfi :: emit_rfi_none
|
|
inst_rfid :: inst_rfid_none
|
|
emit_rfid :: emit_rfid_none
|
|
inst_hrfid :: inst_hrfid_none
|
|
emit_hrfid :: emit_hrfid_none
|
|
inst_sync :: inst_sync_none
|
|
emit_sync :: emit_sync_none
|
|
inst_lwsync :: inst_lwsync_none
|
|
emit_lwsync :: emit_lwsync_none
|
|
inst_ptesync :: inst_ptesync_none
|
|
emit_ptesync :: emit_ptesync_none
|
|
inst_eieio :: inst_eieio_none
|
|
emit_eieio :: emit_eieio_none
|
|
inst_isync :: inst_isync_none
|
|
emit_isync :: emit_isync_none
|
|
inst_dcbt :: inst_dcbt_mem
|
|
emit_dcbt :: emit_dcbt_mem
|
|
inst_dcbtst :: inst_dcbtst_mem
|
|
emit_dcbtst :: emit_dcbtst_mem
|
|
inst_dcba :: inst_dcba_mem
|
|
emit_dcba :: emit_dcba_mem
|
|
inst_dcbf :: inst_dcbf_mem
|
|
emit_dcbf :: emit_dcbf_mem
|
|
inst_dcbz :: inst_dcbz_mem
|
|
emit_dcbz :: emit_dcbz_mem
|
|
inst_dcbzl :: inst_dcbzl_mem
|
|
emit_dcbzl :: emit_dcbzl_mem
|
|
inst_icbi :: inst_icbi_mem
|
|
emit_icbi :: emit_icbi_mem
|
|
inst_icbt :: inst_icbt_mem
|
|
emit_icbt :: emit_icbt_mem
|
|
inst_nap :: inst_nap_none
|
|
emit_nap :: emit_nap_none
|
|
inst_wait :: inst_wait_none
|
|
emit_wait :: emit_wait_none
|
|
inst_msync :: inst_msync_none
|
|
emit_msync :: emit_msync_none
|
|
inst_tlbie :: inst_tlbie_r_r
|
|
emit_tlbie :: emit_tlbie_r_r
|
|
inst_tlbiel :: inst_tlbiel_r
|
|
emit_tlbiel :: emit_tlbiel_r
|
|
inst_tlbsync :: inst_tlbsync_none
|
|
emit_tlbsync :: emit_tlbsync_none
|
|
inst_slbie :: inst_slbie_r
|
|
emit_slbie :: emit_slbie_r
|
|
inst_slbia :: inst_slbia_none
|
|
emit_slbia :: emit_slbia_none
|
|
inst_slbmte :: inst_slbmte_r_r
|
|
emit_slbmte :: emit_slbmte_r_r
|
|
inst_slbmfee :: inst_slbmfee_r_r
|
|
emit_slbmfee :: emit_slbmfee_r_r
|
|
inst_slbmfev :: inst_slbmfev_r_r
|
|
emit_slbmfev :: emit_slbmfev_r_r
|
|
inst_slbsync :: inst_slbsync_none
|
|
emit_slbsync :: emit_slbsync_none
|
|
inst_slbieg :: inst_slbieg_r_r
|
|
emit_slbieg :: emit_slbieg_r_r
|
|
inst_darn :: inst_darn_r_imm
|
|
emit_darn :: emit_darn_r_imm
|
|
inst_vand :: inst_vand_v_v_v
|
|
emit_vand :: emit_vand_v_v_v
|
|
inst_vandc :: inst_vandc_v_v_v
|
|
emit_vandc :: emit_vandc_v_v_v
|
|
inst_vor :: inst_vor_v_v_v
|
|
emit_vor :: emit_vor_v_v_v
|
|
inst_vorc :: inst_vorc_v_v_v
|
|
emit_vorc :: emit_vorc_v_v_v
|
|
inst_vnor :: inst_vnor_v_v_v
|
|
emit_vnor :: emit_vnor_v_v_v
|
|
inst_vxor :: inst_vxor_v_v_v
|
|
emit_vxor :: emit_vxor_v_v_v
|
|
inst_veqv :: inst_veqv_v_v_v
|
|
emit_veqv :: emit_veqv_v_v_v
|
|
inst_vnand :: inst_vnand_v_v_v
|
|
emit_vnand :: emit_vnand_v_v_v
|
|
inst_vsel :: inst_vsel_v_v_v_v
|
|
emit_vsel :: emit_vsel_v_v_v_v
|
|
inst_vaddubm :: inst_vaddubm_v_v_v
|
|
emit_vaddubm :: emit_vaddubm_v_v_v
|
|
inst_vadduhm :: inst_vadduhm_v_v_v
|
|
emit_vadduhm :: emit_vadduhm_v_v_v
|
|
inst_vadduwm :: inst_vadduwm_v_v_v
|
|
emit_vadduwm :: emit_vadduwm_v_v_v
|
|
inst_vaddudm :: inst_vaddudm_v_v_v
|
|
emit_vaddudm :: emit_vaddudm_v_v_v
|
|
inst_vaddfp :: inst_vaddfp_v_v_v
|
|
emit_vaddfp :: emit_vaddfp_v_v_v
|
|
inst_vsububm :: inst_vsububm_v_v_v
|
|
emit_vsububm :: emit_vsububm_v_v_v
|
|
inst_vsubuhm :: inst_vsubuhm_v_v_v
|
|
emit_vsubuhm :: emit_vsubuhm_v_v_v
|
|
inst_vsubuwm :: inst_vsubuwm_v_v_v
|
|
emit_vsubuwm :: emit_vsubuwm_v_v_v
|
|
inst_vsubudm :: inst_vsubudm_v_v_v
|
|
emit_vsubudm :: emit_vsubudm_v_v_v
|
|
inst_vsubfp :: inst_vsubfp_v_v_v
|
|
emit_vsubfp :: emit_vsubfp_v_v_v
|
|
inst_vaddcuw :: inst_vaddcuw_v_v_v
|
|
emit_vaddcuw :: emit_vaddcuw_v_v_v
|
|
inst_vaddcuq :: inst_vaddcuq_v_v_v
|
|
emit_vaddcuq :: emit_vaddcuq_v_v_v
|
|
inst_vaddecuq :: inst_vaddecuq_v_v_v_v
|
|
emit_vaddecuq :: emit_vaddecuq_v_v_v_v
|
|
inst_vaddeuqm :: inst_vaddeuqm_v_v_v_v
|
|
emit_vaddeuqm :: emit_vaddeuqm_v_v_v_v
|
|
inst_vsubcuw :: inst_vsubcuw_v_v_v
|
|
emit_vsubcuw :: emit_vsubcuw_v_v_v
|
|
inst_vsubcuq :: inst_vsubcuq_v_v_v
|
|
emit_vsubcuq :: emit_vsubcuq_v_v_v
|
|
inst_vsubecuq :: inst_vsubecuq_v_v_v_v
|
|
emit_vsubecuq :: emit_vsubecuq_v_v_v_v
|
|
inst_vsubeuqm :: inst_vsubeuqm_v_v_v_v
|
|
emit_vsubeuqm :: emit_vsubeuqm_v_v_v_v
|
|
inst_vaddubs :: inst_vaddubs_v_v_v
|
|
emit_vaddubs :: emit_vaddubs_v_v_v
|
|
inst_vadduhs :: inst_vadduhs_v_v_v
|
|
emit_vadduhs :: emit_vadduhs_v_v_v
|
|
inst_vadduws :: inst_vadduws_v_v_v
|
|
emit_vadduws :: emit_vadduws_v_v_v
|
|
inst_vaddsbs :: inst_vaddsbs_v_v_v
|
|
emit_vaddsbs :: emit_vaddsbs_v_v_v
|
|
inst_vaddshs :: inst_vaddshs_v_v_v
|
|
emit_vaddshs :: emit_vaddshs_v_v_v
|
|
inst_vaddsws :: inst_vaddsws_v_v_v
|
|
emit_vaddsws :: emit_vaddsws_v_v_v
|
|
inst_vsububs :: inst_vsububs_v_v_v
|
|
emit_vsububs :: emit_vsububs_v_v_v
|
|
inst_vsubuhs :: inst_vsubuhs_v_v_v
|
|
emit_vsubuhs :: emit_vsubuhs_v_v_v
|
|
inst_vsubuws :: inst_vsubuws_v_v_v
|
|
emit_vsubuws :: emit_vsubuws_v_v_v
|
|
inst_vsubsbs :: inst_vsubsbs_v_v_v
|
|
emit_vsubsbs :: emit_vsubsbs_v_v_v
|
|
inst_vsubshs :: inst_vsubshs_v_v_v
|
|
emit_vsubshs :: emit_vsubshs_v_v_v
|
|
inst_vsubsws :: inst_vsubsws_v_v_v
|
|
emit_vsubsws :: emit_vsubsws_v_v_v
|
|
inst_vmulesb :: inst_vmulesb_v_v_v
|
|
emit_vmulesb :: emit_vmulesb_v_v_v
|
|
inst_vmulesh :: inst_vmulesh_v_v_v
|
|
emit_vmulesh :: emit_vmulesh_v_v_v
|
|
inst_vmulesw :: inst_vmulesw_v_v_v
|
|
emit_vmulesw :: emit_vmulesw_v_v_v
|
|
inst_vmuleub :: inst_vmuleub_v_v_v
|
|
emit_vmuleub :: emit_vmuleub_v_v_v
|
|
inst_vmuleuh :: inst_vmuleuh_v_v_v
|
|
emit_vmuleuh :: emit_vmuleuh_v_v_v
|
|
inst_vmuleuw :: inst_vmuleuw_v_v_v
|
|
emit_vmuleuw :: emit_vmuleuw_v_v_v
|
|
inst_vmulosb :: inst_vmulosb_v_v_v
|
|
emit_vmulosb :: emit_vmulosb_v_v_v
|
|
inst_vmulosh :: inst_vmulosh_v_v_v
|
|
emit_vmulosh :: emit_vmulosh_v_v_v
|
|
inst_vmulosw :: inst_vmulosw_v_v_v
|
|
emit_vmulosw :: emit_vmulosw_v_v_v
|
|
inst_vmuloub :: inst_vmuloub_v_v_v
|
|
emit_vmuloub :: emit_vmuloub_v_v_v
|
|
inst_vmulouh :: inst_vmulouh_v_v_v
|
|
emit_vmulouh :: emit_vmulouh_v_v_v
|
|
inst_vmulouw :: inst_vmulouw_v_v_v
|
|
emit_vmulouw :: emit_vmulouw_v_v_v
|
|
inst_vmuluwm :: inst_vmuluwm_v_v_v
|
|
emit_vmuluwm :: emit_vmuluwm_v_v_v
|
|
inst_vmsumubm :: inst_vmsumubm_v_v_v_v
|
|
emit_vmsumubm :: emit_vmsumubm_v_v_v_v
|
|
inst_vmsummbm :: inst_vmsummbm_v_v_v_v
|
|
emit_vmsummbm :: emit_vmsummbm_v_v_v_v
|
|
inst_vmsumuhm :: inst_vmsumuhm_v_v_v_v
|
|
emit_vmsumuhm :: emit_vmsumuhm_v_v_v_v
|
|
inst_vmsumshm :: inst_vmsumshm_v_v_v_v
|
|
emit_vmsumshm :: emit_vmsumshm_v_v_v_v
|
|
inst_vmsumuhs :: inst_vmsumuhs_v_v_v_v
|
|
emit_vmsumuhs :: emit_vmsumuhs_v_v_v_v
|
|
inst_vmsumshs :: inst_vmsumshs_v_v_v_v
|
|
emit_vmsumshs :: emit_vmsumshs_v_v_v_v
|
|
inst_vmsumudm :: inst_vmsumudm_v_v_v_v
|
|
emit_vmsumudm :: emit_vmsumudm_v_v_v_v
|
|
inst_vcmpequb :: inst_vcmpequb_v_v_v
|
|
emit_vcmpequb :: emit_vcmpequb_v_v_v
|
|
inst_vcmpequb_dot :: inst_vcmpequb_dot_v_v_v
|
|
emit_vcmpequb_dot :: emit_vcmpequb_dot_v_v_v
|
|
inst_vcmpequh :: inst_vcmpequh_v_v_v
|
|
emit_vcmpequh :: emit_vcmpequh_v_v_v
|
|
inst_vcmpequh_dot :: inst_vcmpequh_dot_v_v_v
|
|
emit_vcmpequh_dot :: emit_vcmpequh_dot_v_v_v
|
|
inst_vcmpequw :: inst_vcmpequw_v_v_v
|
|
emit_vcmpequw :: emit_vcmpequw_v_v_v
|
|
inst_vcmpequw_dot :: inst_vcmpequw_dot_v_v_v
|
|
emit_vcmpequw_dot :: emit_vcmpequw_dot_v_v_v
|
|
inst_vcmpequd :: inst_vcmpequd_v_v_v
|
|
emit_vcmpequd :: emit_vcmpequd_v_v_v
|
|
inst_vcmpequd_dot :: inst_vcmpequd_dot_v_v_v
|
|
emit_vcmpequd_dot :: emit_vcmpequd_dot_v_v_v
|
|
inst_vcmpneb :: inst_vcmpneb_v_v_v
|
|
emit_vcmpneb :: emit_vcmpneb_v_v_v
|
|
inst_vcmpneb_dot :: inst_vcmpneb_dot_v_v_v
|
|
emit_vcmpneb_dot :: emit_vcmpneb_dot_v_v_v
|
|
inst_vcmpneh :: inst_vcmpneh_v_v_v
|
|
emit_vcmpneh :: emit_vcmpneh_v_v_v
|
|
inst_vcmpneh_dot :: inst_vcmpneh_dot_v_v_v
|
|
emit_vcmpneh_dot :: emit_vcmpneh_dot_v_v_v
|
|
inst_vcmpnew :: inst_vcmpnew_v_v_v
|
|
emit_vcmpnew :: emit_vcmpnew_v_v_v
|
|
inst_vcmpnew_dot :: inst_vcmpnew_dot_v_v_v
|
|
emit_vcmpnew_dot :: emit_vcmpnew_dot_v_v_v
|
|
inst_vcmpgtsb :: inst_vcmpgtsb_v_v_v
|
|
emit_vcmpgtsb :: emit_vcmpgtsb_v_v_v
|
|
inst_vcmpgtsb_dot :: inst_vcmpgtsb_dot_v_v_v
|
|
emit_vcmpgtsb_dot :: emit_vcmpgtsb_dot_v_v_v
|
|
inst_vcmpgtsh :: inst_vcmpgtsh_v_v_v
|
|
emit_vcmpgtsh :: emit_vcmpgtsh_v_v_v
|
|
inst_vcmpgtsh_dot :: inst_vcmpgtsh_dot_v_v_v
|
|
emit_vcmpgtsh_dot :: emit_vcmpgtsh_dot_v_v_v
|
|
inst_vcmpgtsw :: inst_vcmpgtsw_v_v_v
|
|
emit_vcmpgtsw :: emit_vcmpgtsw_v_v_v
|
|
inst_vcmpgtsw_dot :: inst_vcmpgtsw_dot_v_v_v
|
|
emit_vcmpgtsw_dot :: emit_vcmpgtsw_dot_v_v_v
|
|
inst_vcmpgtsd :: inst_vcmpgtsd_v_v_v
|
|
emit_vcmpgtsd :: emit_vcmpgtsd_v_v_v
|
|
inst_vcmpgtsd_dot :: inst_vcmpgtsd_dot_v_v_v
|
|
emit_vcmpgtsd_dot :: emit_vcmpgtsd_dot_v_v_v
|
|
inst_vcmpgtub :: inst_vcmpgtub_v_v_v
|
|
emit_vcmpgtub :: emit_vcmpgtub_v_v_v
|
|
inst_vcmpgtub_dot :: inst_vcmpgtub_dot_v_v_v
|
|
emit_vcmpgtub_dot :: emit_vcmpgtub_dot_v_v_v
|
|
inst_vcmpgtuh :: inst_vcmpgtuh_v_v_v
|
|
emit_vcmpgtuh :: emit_vcmpgtuh_v_v_v
|
|
inst_vcmpgtuh_dot :: inst_vcmpgtuh_dot_v_v_v
|
|
emit_vcmpgtuh_dot :: emit_vcmpgtuh_dot_v_v_v
|
|
inst_vcmpgtuw :: inst_vcmpgtuw_v_v_v
|
|
emit_vcmpgtuw :: emit_vcmpgtuw_v_v_v
|
|
inst_vcmpgtuw_dot :: inst_vcmpgtuw_dot_v_v_v
|
|
emit_vcmpgtuw_dot :: emit_vcmpgtuw_dot_v_v_v
|
|
inst_vcmpgtud :: inst_vcmpgtud_v_v_v
|
|
emit_vcmpgtud :: emit_vcmpgtud_v_v_v
|
|
inst_vcmpgtud_dot :: inst_vcmpgtud_dot_v_v_v
|
|
emit_vcmpgtud_dot :: emit_vcmpgtud_dot_v_v_v
|
|
inst_vcmpeqfp :: inst_vcmpeqfp_v_v_v
|
|
emit_vcmpeqfp :: emit_vcmpeqfp_v_v_v
|
|
inst_vcmpeqfp_dot :: inst_vcmpeqfp_dot_v_v_v
|
|
emit_vcmpeqfp_dot :: emit_vcmpeqfp_dot_v_v_v
|
|
inst_vcmpgefp :: inst_vcmpgefp_v_v_v
|
|
emit_vcmpgefp :: emit_vcmpgefp_v_v_v
|
|
inst_vcmpgefp_dot :: inst_vcmpgefp_dot_v_v_v
|
|
emit_vcmpgefp_dot :: emit_vcmpgefp_dot_v_v_v
|
|
inst_vcmpgtfp :: inst_vcmpgtfp_v_v_v
|
|
emit_vcmpgtfp :: emit_vcmpgtfp_v_v_v
|
|
inst_vcmpgtfp_dot :: inst_vcmpgtfp_dot_v_v_v
|
|
emit_vcmpgtfp_dot :: emit_vcmpgtfp_dot_v_v_v
|
|
inst_vcmpbfp :: inst_vcmpbfp_v_v_v
|
|
emit_vcmpbfp :: emit_vcmpbfp_v_v_v
|
|
inst_vcmpbfp_dot :: inst_vcmpbfp_dot_v_v_v
|
|
emit_vcmpbfp_dot :: emit_vcmpbfp_dot_v_v_v
|
|
inst_vmaxsb :: inst_vmaxsb_v_v_v
|
|
emit_vmaxsb :: emit_vmaxsb_v_v_v
|
|
inst_vmaxsh :: inst_vmaxsh_v_v_v
|
|
emit_vmaxsh :: emit_vmaxsh_v_v_v
|
|
inst_vmaxsw :: inst_vmaxsw_v_v_v
|
|
emit_vmaxsw :: emit_vmaxsw_v_v_v
|
|
inst_vmaxsd :: inst_vmaxsd_v_v_v
|
|
emit_vmaxsd :: emit_vmaxsd_v_v_v
|
|
inst_vmaxub :: inst_vmaxub_v_v_v
|
|
emit_vmaxub :: emit_vmaxub_v_v_v
|
|
inst_vmaxuh :: inst_vmaxuh_v_v_v
|
|
emit_vmaxuh :: emit_vmaxuh_v_v_v
|
|
inst_vmaxuw :: inst_vmaxuw_v_v_v
|
|
emit_vmaxuw :: emit_vmaxuw_v_v_v
|
|
inst_vmaxud :: inst_vmaxud_v_v_v
|
|
emit_vmaxud :: emit_vmaxud_v_v_v
|
|
inst_vmaxfp :: inst_vmaxfp_v_v_v
|
|
emit_vmaxfp :: emit_vmaxfp_v_v_v
|
|
inst_vminsb :: inst_vminsb_v_v_v
|
|
emit_vminsb :: emit_vminsb_v_v_v
|
|
inst_vminsh :: inst_vminsh_v_v_v
|
|
emit_vminsh :: emit_vminsh_v_v_v
|
|
inst_vminsw :: inst_vminsw_v_v_v
|
|
emit_vminsw :: emit_vminsw_v_v_v
|
|
inst_vminsd :: inst_vminsd_v_v_v
|
|
emit_vminsd :: emit_vminsd_v_v_v
|
|
inst_vminub :: inst_vminub_v_v_v
|
|
emit_vminub :: emit_vminub_v_v_v
|
|
inst_vminuh :: inst_vminuh_v_v_v
|
|
emit_vminuh :: emit_vminuh_v_v_v
|
|
inst_vminuw :: inst_vminuw_v_v_v
|
|
emit_vminuw :: emit_vminuw_v_v_v
|
|
inst_vminud :: inst_vminud_v_v_v
|
|
emit_vminud :: emit_vminud_v_v_v
|
|
inst_vminfp :: inst_vminfp_v_v_v
|
|
emit_vminfp :: emit_vminfp_v_v_v
|
|
inst_vavgsb :: inst_vavgsb_v_v_v
|
|
emit_vavgsb :: emit_vavgsb_v_v_v
|
|
inst_vavgsh :: inst_vavgsh_v_v_v
|
|
emit_vavgsh :: emit_vavgsh_v_v_v
|
|
inst_vavgsw :: inst_vavgsw_v_v_v
|
|
emit_vavgsw :: emit_vavgsw_v_v_v
|
|
inst_vavgub :: inst_vavgub_v_v_v
|
|
emit_vavgub :: emit_vavgub_v_v_v
|
|
inst_vavguh :: inst_vavguh_v_v_v
|
|
emit_vavguh :: emit_vavguh_v_v_v
|
|
inst_vavguw :: inst_vavguw_v_v_v
|
|
emit_vavguw :: emit_vavguw_v_v_v
|
|
inst_vsl :: inst_vsl_v_v_v
|
|
emit_vsl :: emit_vsl_v_v_v
|
|
inst_vsr :: inst_vsr_v_v_v
|
|
emit_vsr :: emit_vsr_v_v_v
|
|
inst_vslo :: inst_vslo_v_v_v
|
|
emit_vslo :: emit_vslo_v_v_v
|
|
inst_vsro :: inst_vsro_v_v_v
|
|
emit_vsro :: emit_vsro_v_v_v
|
|
inst_vslb :: inst_vslb_v_v_v
|
|
emit_vslb :: emit_vslb_v_v_v
|
|
inst_vslh :: inst_vslh_v_v_v
|
|
emit_vslh :: emit_vslh_v_v_v
|
|
inst_vslw :: inst_vslw_v_v_v
|
|
emit_vslw :: emit_vslw_v_v_v
|
|
inst_vsld :: inst_vsld_v_v_v
|
|
emit_vsld :: emit_vsld_v_v_v
|
|
inst_vsrb :: inst_vsrb_v_v_v
|
|
emit_vsrb :: emit_vsrb_v_v_v
|
|
inst_vsrh :: inst_vsrh_v_v_v
|
|
emit_vsrh :: emit_vsrh_v_v_v
|
|
inst_vsrw :: inst_vsrw_v_v_v
|
|
emit_vsrw :: emit_vsrw_v_v_v
|
|
inst_vsrd :: inst_vsrd_v_v_v
|
|
emit_vsrd :: emit_vsrd_v_v_v
|
|
inst_vsrab :: inst_vsrab_v_v_v
|
|
emit_vsrab :: emit_vsrab_v_v_v
|
|
inst_vsrah :: inst_vsrah_v_v_v
|
|
emit_vsrah :: emit_vsrah_v_v_v
|
|
inst_vsraw :: inst_vsraw_v_v_v
|
|
emit_vsraw :: emit_vsraw_v_v_v
|
|
inst_vsrad :: inst_vsrad_v_v_v
|
|
emit_vsrad :: emit_vsrad_v_v_v
|
|
inst_vrlb :: inst_vrlb_v_v_v
|
|
emit_vrlb :: emit_vrlb_v_v_v
|
|
inst_vrlh :: inst_vrlh_v_v_v
|
|
emit_vrlh :: emit_vrlh_v_v_v
|
|
inst_vrlw :: inst_vrlw_v_v_v
|
|
emit_vrlw :: emit_vrlw_v_v_v
|
|
inst_vrld :: inst_vrld_v_v_v
|
|
emit_vrld :: emit_vrld_v_v_v
|
|
inst_vperm :: inst_vperm_v_v_v_v
|
|
emit_vperm :: emit_vperm_v_v_v_v
|
|
inst_vpermr :: inst_vpermr_v_v_v_v
|
|
emit_vpermr :: emit_vpermr_v_v_v_v
|
|
inst_vsldoi :: inst_vsldoi_v_v_v_imm
|
|
emit_vsldoi :: emit_vsldoi_v_v_v_imm
|
|
inst_vbpermq :: inst_vbpermq_v_v_v
|
|
emit_vbpermq :: emit_vbpermq_v_v_v
|
|
inst_vbpermd :: inst_vbpermd_v_v_v
|
|
emit_vbpermd :: emit_vbpermd_v_v_v
|
|
inst_vmrghb :: inst_vmrghb_v_v_v
|
|
emit_vmrghb :: emit_vmrghb_v_v_v
|
|
inst_vmrghh :: inst_vmrghh_v_v_v
|
|
emit_vmrghh :: emit_vmrghh_v_v_v
|
|
inst_vmrghw :: inst_vmrghw_v_v_v
|
|
emit_vmrghw :: emit_vmrghw_v_v_v
|
|
inst_vmrglb :: inst_vmrglb_v_v_v
|
|
emit_vmrglb :: emit_vmrglb_v_v_v
|
|
inst_vmrglh :: inst_vmrglh_v_v_v
|
|
emit_vmrglh :: emit_vmrglh_v_v_v
|
|
inst_vmrglw :: inst_vmrglw_v_v_v
|
|
emit_vmrglw :: emit_vmrglw_v_v_v
|
|
inst_vmrgew :: inst_vmrgew_v_v_v
|
|
emit_vmrgew :: emit_vmrgew_v_v_v
|
|
inst_vmrgow :: inst_vmrgow_v_v_v
|
|
emit_vmrgow :: emit_vmrgow_v_v_v
|
|
inst_vspltb :: inst_vspltb_v_v_imm
|
|
emit_vspltb :: emit_vspltb_v_v_imm
|
|
inst_vsplth :: inst_vsplth_v_v_imm
|
|
emit_vsplth :: emit_vsplth_v_v_imm
|
|
inst_vspltw :: inst_vspltw_v_v_imm
|
|
emit_vspltw :: emit_vspltw_v_v_imm
|
|
inst_vspltisb :: inst_vspltisb_v_simm
|
|
emit_vspltisb :: emit_vspltisb_v_simm
|
|
inst_vspltish :: inst_vspltish_v_simm
|
|
emit_vspltish :: emit_vspltish_v_simm
|
|
inst_vspltisw :: inst_vspltisw_v_simm
|
|
emit_vspltisw :: emit_vspltisw_v_simm
|
|
inst_vpkpx :: inst_vpkpx_v_v_v
|
|
emit_vpkpx :: emit_vpkpx_v_v_v
|
|
inst_vpkuhum :: inst_vpkuhum_v_v_v
|
|
emit_vpkuhum :: emit_vpkuhum_v_v_v
|
|
inst_vpkuwum :: inst_vpkuwum_v_v_v
|
|
emit_vpkuwum :: emit_vpkuwum_v_v_v
|
|
inst_vpkudum :: inst_vpkudum_v_v_v
|
|
emit_vpkudum :: emit_vpkudum_v_v_v
|
|
inst_vpkuhus :: inst_vpkuhus_v_v_v
|
|
emit_vpkuhus :: emit_vpkuhus_v_v_v
|
|
inst_vpkuwus :: inst_vpkuwus_v_v_v
|
|
emit_vpkuwus :: emit_vpkuwus_v_v_v
|
|
inst_vpkudus :: inst_vpkudus_v_v_v
|
|
emit_vpkudus :: emit_vpkudus_v_v_v
|
|
inst_vpkshus :: inst_vpkshus_v_v_v
|
|
emit_vpkshus :: emit_vpkshus_v_v_v
|
|
inst_vpkswus :: inst_vpkswus_v_v_v
|
|
emit_vpkswus :: emit_vpkswus_v_v_v
|
|
inst_vpksdus :: inst_vpksdus_v_v_v
|
|
emit_vpksdus :: emit_vpksdus_v_v_v
|
|
inst_vpkshss :: inst_vpkshss_v_v_v
|
|
emit_vpkshss :: emit_vpkshss_v_v_v
|
|
inst_vpkswss :: inst_vpkswss_v_v_v
|
|
emit_vpkswss :: emit_vpkswss_v_v_v
|
|
inst_vpksdss :: inst_vpksdss_v_v_v
|
|
emit_vpksdss :: emit_vpksdss_v_v_v
|
|
inst_vupkhsb :: inst_vupkhsb_v_v
|
|
emit_vupkhsb :: emit_vupkhsb_v_v
|
|
inst_vupkhsh :: inst_vupkhsh_v_v
|
|
emit_vupkhsh :: emit_vupkhsh_v_v
|
|
inst_vupkhsw :: inst_vupkhsw_v_v
|
|
emit_vupkhsw :: emit_vupkhsw_v_v
|
|
inst_vupklsb :: inst_vupklsb_v_v
|
|
emit_vupklsb :: emit_vupklsb_v_v
|
|
inst_vupklsh :: inst_vupklsh_v_v
|
|
emit_vupklsh :: emit_vupklsh_v_v
|
|
inst_vupklsw :: inst_vupklsw_v_v
|
|
emit_vupklsw :: emit_vupklsw_v_v
|
|
inst_vupkhpx :: inst_vupkhpx_v_v
|
|
emit_vupkhpx :: emit_vupkhpx_v_v
|
|
inst_vupklpx :: inst_vupklpx_v_v
|
|
emit_vupklpx :: emit_vupklpx_v_v
|
|
inst_vcipher :: inst_vcipher_v_v_v
|
|
emit_vcipher :: emit_vcipher_v_v_v
|
|
inst_vcipherlast :: inst_vcipherlast_v_v_v
|
|
emit_vcipherlast :: emit_vcipherlast_v_v_v
|
|
inst_vncipher :: inst_vncipher_v_v_v
|
|
emit_vncipher :: emit_vncipher_v_v_v
|
|
inst_vncipherlast :: inst_vncipherlast_v_v_v
|
|
emit_vncipherlast :: emit_vncipherlast_v_v_v
|
|
inst_vsbox :: inst_vsbox_v_v
|
|
emit_vsbox :: emit_vsbox_v_v
|
|
inst_vshasigmaw :: inst_vshasigmaw_v_v_imm_imm
|
|
emit_vshasigmaw :: emit_vshasigmaw_v_v_imm_imm
|
|
inst_vshasigmad :: inst_vshasigmad_v_v_imm_imm
|
|
emit_vshasigmad :: emit_vshasigmad_v_v_imm_imm
|
|
inst_vpmsumb :: inst_vpmsumb_v_v_v
|
|
emit_vpmsumb :: emit_vpmsumb_v_v_v
|
|
inst_vpmsumh :: inst_vpmsumh_v_v_v
|
|
emit_vpmsumh :: emit_vpmsumh_v_v_v
|
|
inst_vpmsumw :: inst_vpmsumw_v_v_v
|
|
emit_vpmsumw :: emit_vpmsumw_v_v_v
|
|
inst_vpmsumd :: inst_vpmsumd_v_v_v
|
|
emit_vpmsumd :: emit_vpmsumd_v_v_v
|
|
inst_vrfim :: inst_vrfim_v_v
|
|
emit_vrfim :: emit_vrfim_v_v
|
|
inst_vrfin :: inst_vrfin_v_v
|
|
emit_vrfin :: emit_vrfin_v_v
|
|
inst_vrfip :: inst_vrfip_v_v
|
|
emit_vrfip :: emit_vrfip_v_v
|
|
inst_vrfiz :: inst_vrfiz_v_v
|
|
emit_vrfiz :: emit_vrfiz_v_v
|
|
inst_vexptefp :: inst_vexptefp_v_v
|
|
emit_vexptefp :: emit_vexptefp_v_v
|
|
inst_vlogefp :: inst_vlogefp_v_v
|
|
emit_vlogefp :: emit_vlogefp_v_v
|
|
inst_vrefp :: inst_vrefp_v_v
|
|
emit_vrefp :: emit_vrefp_v_v
|
|
inst_vrsqrtefp :: inst_vrsqrtefp_v_v
|
|
emit_vrsqrtefp :: emit_vrsqrtefp_v_v
|
|
inst_vmaddfp :: inst_vmaddfp_v_v_v_v
|
|
emit_vmaddfp :: emit_vmaddfp_v_v_v_v
|
|
inst_vnmsubfp :: inst_vnmsubfp_v_v_v_v
|
|
emit_vnmsubfp :: emit_vnmsubfp_v_v_v_v
|
|
inst_vcfsx :: inst_vcfsx_v_v_imm
|
|
emit_vcfsx :: emit_vcfsx_v_v_imm
|
|
inst_vcfux :: inst_vcfux_v_v_imm
|
|
emit_vcfux :: emit_vcfux_v_v_imm
|
|
inst_vctsxs :: inst_vctsxs_v_v_imm
|
|
emit_vctsxs :: emit_vctsxs_v_v_imm
|
|
inst_vctuxs :: inst_vctuxs_v_v_imm
|
|
emit_vctuxs :: emit_vctuxs_v_v_imm
|
|
inst_lvx :: inst_lvx_v_mem
|
|
emit_lvx :: emit_lvx_v_mem
|
|
inst_lvxl :: inst_lvxl_v_mem
|
|
emit_lvxl :: emit_lvxl_v_mem
|
|
inst_lvebx :: inst_lvebx_v_mem
|
|
emit_lvebx :: emit_lvebx_v_mem
|
|
inst_lvehx :: inst_lvehx_v_mem
|
|
emit_lvehx :: emit_lvehx_v_mem
|
|
inst_lvewx :: inst_lvewx_v_mem
|
|
emit_lvewx :: emit_lvewx_v_mem
|
|
inst_lvsl :: inst_lvsl_v_mem
|
|
emit_lvsl :: emit_lvsl_v_mem
|
|
inst_lvsr :: inst_lvsr_v_mem
|
|
emit_lvsr :: emit_lvsr_v_mem
|
|
inst_stvx :: inst_stvx_v_mem
|
|
emit_stvx :: emit_stvx_v_mem
|
|
inst_stvxl :: inst_stvxl_v_mem
|
|
emit_stvxl :: emit_stvxl_v_mem
|
|
inst_stvebx :: inst_stvebx_v_mem
|
|
emit_stvebx :: emit_stvebx_v_mem
|
|
inst_stvehx :: inst_stvehx_v_mem
|
|
emit_stvehx :: emit_stvehx_v_mem
|
|
inst_stvewx :: inst_stvewx_v_mem
|
|
emit_stvewx :: emit_stvewx_v_mem
|
|
inst_mfvscr :: inst_mfvscr_v
|
|
emit_mfvscr :: emit_mfvscr_v
|
|
inst_mtvscr :: inst_mtvscr_v
|
|
emit_mtvscr :: emit_mtvscr_v
|
|
inst_vabsdub :: inst_vabsdub_v_v_v
|
|
emit_vabsdub :: emit_vabsdub_v_v_v
|
|
inst_vabsduh :: inst_vabsduh_v_v_v
|
|
emit_vabsduh :: emit_vabsduh_v_v_v
|
|
inst_vabsduw :: inst_vabsduw_v_v_v
|
|
emit_vabsduw :: emit_vabsduw_v_v_v
|
|
inst_vextsb2w :: inst_vextsb2w_v_v
|
|
emit_vextsb2w :: emit_vextsb2w_v_v
|
|
inst_vextsh2w :: inst_vextsh2w_v_v
|
|
emit_vextsh2w :: emit_vextsh2w_v_v
|
|
inst_vextsb2d :: inst_vextsb2d_v_v
|
|
emit_vextsb2d :: emit_vextsb2d_v_v
|
|
inst_vextsh2d :: inst_vextsh2d_v_v
|
|
emit_vextsh2d :: emit_vextsh2d_v_v
|
|
inst_vextsw2d :: inst_vextsw2d_v_v
|
|
emit_vextsw2d :: emit_vextsw2d_v_v
|
|
inst_vprtybw :: inst_vprtybw_v_v
|
|
emit_vprtybw :: emit_vprtybw_v_v
|
|
inst_vprtybd :: inst_vprtybd_v_v
|
|
emit_vprtybd :: emit_vprtybd_v_v
|
|
inst_vprtybq :: inst_vprtybq_v_v
|
|
emit_vprtybq :: emit_vprtybq_v_v
|
|
inst_vrlwnm :: inst_vrlwnm_v_v_v
|
|
emit_vrlwnm :: emit_vrlwnm_v_v_v
|
|
inst_vrldnm :: inst_vrldnm_v_v_v
|
|
emit_vrldnm :: emit_vrldnm_v_v_v
|
|
inst_vrlwmi :: inst_vrlwmi_v_v_v
|
|
emit_vrlwmi :: emit_vrlwmi_v_v_v
|
|
inst_vrldmi :: inst_vrldmi_v_v_v
|
|
emit_vrldmi :: emit_vrldmi_v_v_v
|
|
inst_vcmpnezb :: inst_vcmpnezb_v_v_v
|
|
emit_vcmpnezb :: emit_vcmpnezb_v_v_v
|
|
inst_vcmpnezb_dot :: inst_vcmpnezb_dot_v_v_v
|
|
emit_vcmpnezb_dot :: emit_vcmpnezb_dot_v_v_v
|
|
inst_vcmpnezh :: inst_vcmpnezh_v_v_v
|
|
emit_vcmpnezh :: emit_vcmpnezh_v_v_v
|
|
inst_vcmpnezh_dot :: inst_vcmpnezh_dot_v_v_v
|
|
emit_vcmpnezh_dot :: emit_vcmpnezh_dot_v_v_v
|
|
inst_vcmpnezw :: inst_vcmpnezw_v_v_v
|
|
emit_vcmpnezw :: emit_vcmpnezw_v_v_v
|
|
inst_vcmpnezw_dot :: inst_vcmpnezw_dot_v_v_v
|
|
emit_vcmpnezw_dot :: emit_vcmpnezw_dot_v_v_v
|
|
inst_vclzb :: inst_vclzb_v_v
|
|
emit_vclzb :: emit_vclzb_v_v
|
|
inst_vclzh :: inst_vclzh_v_v
|
|
emit_vclzh :: emit_vclzh_v_v
|
|
inst_vclzw :: inst_vclzw_v_v
|
|
emit_vclzw :: emit_vclzw_v_v
|
|
inst_vclzd :: inst_vclzd_v_v
|
|
emit_vclzd :: emit_vclzd_v_v
|
|
inst_vctzb :: inst_vctzb_v_v
|
|
emit_vctzb :: emit_vctzb_v_v
|
|
inst_vctzh :: inst_vctzh_v_v
|
|
emit_vctzh :: emit_vctzh_v_v
|
|
inst_vctzw :: inst_vctzw_v_v
|
|
emit_vctzw :: emit_vctzw_v_v
|
|
inst_vctzd :: inst_vctzd_v_v
|
|
emit_vctzd :: emit_vctzd_v_v
|
|
inst_vpopcntb :: inst_vpopcntb_v_v
|
|
emit_vpopcntb :: emit_vpopcntb_v_v
|
|
inst_vpopcnth :: inst_vpopcnth_v_v
|
|
emit_vpopcnth :: emit_vpopcnth_v_v
|
|
inst_vpopcntw :: inst_vpopcntw_v_v
|
|
emit_vpopcntw :: emit_vpopcntw_v_v
|
|
inst_vpopcntd :: inst_vpopcntd_v_v
|
|
emit_vpopcntd :: emit_vpopcntd_v_v
|
|
inst_vextractub :: inst_vextractub_v_v_imm
|
|
emit_vextractub :: emit_vextractub_v_v_imm
|
|
inst_vextractuh :: inst_vextractuh_v_v_imm
|
|
emit_vextractuh :: emit_vextractuh_v_v_imm
|
|
inst_vextractuw :: inst_vextractuw_v_v_imm
|
|
emit_vextractuw :: emit_vextractuw_v_v_imm
|
|
inst_vextractd :: inst_vextractd_v_v_imm
|
|
emit_vextractd :: emit_vextractd_v_v_imm
|
|
inst_vinsertb :: inst_vinsertb_v_v_imm
|
|
emit_vinsertb :: emit_vinsertb_v_v_imm
|
|
inst_vinserth :: inst_vinserth_v_v_imm
|
|
emit_vinserth :: emit_vinserth_v_v_imm
|
|
inst_vinsertw :: inst_vinsertw_v_v_imm
|
|
emit_vinsertw :: emit_vinsertw_v_v_imm
|
|
inst_vinsertd :: inst_vinsertd_v_v_imm
|
|
emit_vinsertd :: emit_vinsertd_v_v_imm
|
|
inst_vslv :: inst_vslv_v_v_v
|
|
emit_vslv :: emit_vslv_v_v_v
|
|
inst_vsrv :: inst_vsrv_v_v_v
|
|
emit_vsrv :: emit_vsrv_v_v_v
|
|
inst_vmul10uq :: inst_vmul10uq_v_v
|
|
emit_vmul10uq :: emit_vmul10uq_v_v
|
|
inst_vmul10cuq :: inst_vmul10cuq_v_v
|
|
emit_vmul10cuq :: emit_vmul10cuq_v_v
|
|
inst_vmul10euq :: inst_vmul10euq_v_v_v
|
|
emit_vmul10euq :: emit_vmul10euq_v_v_v
|
|
inst_vmul10ecuq :: inst_vmul10ecuq_v_v_v
|
|
emit_vmul10ecuq :: emit_vmul10ecuq_v_v_v
|
|
inst_lxsdx :: inst_lxsdx_vs_mem
|
|
emit_lxsdx :: emit_lxsdx_vs_mem
|
|
inst_lxsiwax :: inst_lxsiwax_vs_mem
|
|
emit_lxsiwax :: emit_lxsiwax_vs_mem
|
|
inst_lxsiwzx :: inst_lxsiwzx_vs_mem
|
|
emit_lxsiwzx :: emit_lxsiwzx_vs_mem
|
|
inst_lxvd2x :: inst_lxvd2x_vs_mem
|
|
emit_lxvd2x :: emit_lxvd2x_vs_mem
|
|
inst_lxvdsx :: inst_lxvdsx_vs_mem
|
|
emit_lxvdsx :: emit_lxvdsx_vs_mem
|
|
inst_lxvw4x :: inst_lxvw4x_vs_mem
|
|
emit_lxvw4x :: emit_lxvw4x_vs_mem
|
|
inst_stxsdx :: inst_stxsdx_vs_mem
|
|
emit_stxsdx :: emit_stxsdx_vs_mem
|
|
inst_stxsiwx :: inst_stxsiwx_vs_mem
|
|
emit_stxsiwx :: emit_stxsiwx_vs_mem
|
|
inst_stxvd2x :: inst_stxvd2x_vs_mem
|
|
emit_stxvd2x :: emit_stxvd2x_vs_mem
|
|
inst_stxvw4x :: inst_stxvw4x_vs_mem
|
|
emit_stxvw4x :: emit_stxvw4x_vs_mem
|
|
inst_lxsspx :: inst_lxsspx_vs_mem
|
|
emit_lxsspx :: emit_lxsspx_vs_mem
|
|
inst_stxsspx :: inst_stxsspx_vs_mem
|
|
emit_stxsspx :: emit_stxsspx_vs_mem
|
|
inst_lxv :: inst_lxv_vs_mem
|
|
emit_lxv :: emit_lxv_vs_mem
|
|
inst_stxv :: inst_stxv_vs_mem
|
|
emit_stxv :: emit_stxv_vs_mem
|
|
inst_lxvh8x :: inst_lxvh8x_vs_mem
|
|
emit_lxvh8x :: emit_lxvh8x_vs_mem
|
|
inst_lxvb16x :: inst_lxvb16x_vs_mem
|
|
emit_lxvb16x :: emit_lxvb16x_vs_mem
|
|
inst_lxvl :: inst_lxvl_vs_r_r
|
|
emit_lxvl :: emit_lxvl_vs_r_r
|
|
inst_lxvll :: inst_lxvll_vs_r_r
|
|
emit_lxvll :: emit_lxvll_vs_r_r
|
|
inst_stxvh8x :: inst_stxvh8x_vs_mem
|
|
emit_stxvh8x :: emit_stxvh8x_vs_mem
|
|
inst_stxvb16x :: inst_stxvb16x_vs_mem
|
|
emit_stxvb16x :: emit_stxvb16x_vs_mem
|
|
inst_stxvl :: inst_stxvl_vs_r_r
|
|
emit_stxvl :: emit_stxvl_vs_r_r
|
|
inst_stxvll :: inst_stxvll_vs_r_r
|
|
emit_stxvll :: emit_stxvll_vs_r_r
|
|
inst_lxvx :: inst_lxvx_vs_mem
|
|
emit_lxvx :: emit_lxvx_vs_mem
|
|
inst_stxvx :: inst_stxvx_vs_mem
|
|
emit_stxvx :: emit_stxvx_vs_mem
|
|
inst_lxsibzx :: inst_lxsibzx_vs_mem
|
|
emit_lxsibzx :: emit_lxsibzx_vs_mem
|
|
inst_lxsihzx :: inst_lxsihzx_vs_mem
|
|
emit_lxsihzx :: emit_lxsihzx_vs_mem
|
|
inst_stxsibx :: inst_stxsibx_vs_mem
|
|
emit_stxsibx :: emit_stxsibx_vs_mem
|
|
inst_stxsihx :: inst_stxsihx_vs_mem
|
|
emit_stxsihx :: emit_stxsihx_vs_mem
|
|
inst_lxsd :: inst_lxsd_v_mem
|
|
emit_lxsd :: emit_lxsd_v_mem
|
|
inst_stxsd :: inst_stxsd_v_mem
|
|
emit_stxsd :: emit_stxsd_v_mem
|
|
inst_lxssp :: inst_lxssp_v_mem
|
|
emit_lxssp :: emit_lxssp_v_mem
|
|
inst_stxssp :: inst_stxssp_v_mem
|
|
emit_stxssp :: emit_stxssp_v_mem
|
|
inst_xsaddsp :: inst_xsaddsp_vs_vs_vs
|
|
emit_xsaddsp :: emit_xsaddsp_vs_vs_vs
|
|
inst_xsadddp :: inst_xsadddp_vs_vs_vs
|
|
emit_xsadddp :: emit_xsadddp_vs_vs_vs
|
|
inst_xssubsp :: inst_xssubsp_vs_vs_vs
|
|
emit_xssubsp :: emit_xssubsp_vs_vs_vs
|
|
inst_xssubdp :: inst_xssubdp_vs_vs_vs
|
|
emit_xssubdp :: emit_xssubdp_vs_vs_vs
|
|
inst_xsmulsp :: inst_xsmulsp_vs_vs_vs
|
|
emit_xsmulsp :: emit_xsmulsp_vs_vs_vs
|
|
inst_xsmuldp :: inst_xsmuldp_vs_vs_vs
|
|
emit_xsmuldp :: emit_xsmuldp_vs_vs_vs
|
|
inst_xsdivsp :: inst_xsdivsp_vs_vs_vs
|
|
emit_xsdivsp :: emit_xsdivsp_vs_vs_vs
|
|
inst_xsdivdp :: inst_xsdivdp_vs_vs_vs
|
|
emit_xsdivdp :: emit_xsdivdp_vs_vs_vs
|
|
inst_xssqrtsp :: inst_xssqrtsp_vs_vs
|
|
emit_xssqrtsp :: emit_xssqrtsp_vs_vs
|
|
inst_xssqrtdp :: inst_xssqrtdp_vs_vs
|
|
emit_xssqrtdp :: emit_xssqrtdp_vs_vs
|
|
inst_xsresp :: inst_xsresp_vs_vs
|
|
emit_xsresp :: emit_xsresp_vs_vs
|
|
inst_xsredp :: inst_xsredp_vs_vs
|
|
emit_xsredp :: emit_xsredp_vs_vs
|
|
inst_xsrsqrtesp :: inst_xsrsqrtesp_vs_vs
|
|
emit_xsrsqrtesp :: emit_xsrsqrtesp_vs_vs
|
|
inst_xsrsqrtedp :: inst_xsrsqrtedp_vs_vs
|
|
emit_xsrsqrtedp :: emit_xsrsqrtedp_vs_vs
|
|
inst_xsmaddasp :: inst_xsmaddasp_vs_vs_vs
|
|
emit_xsmaddasp :: emit_xsmaddasp_vs_vs_vs
|
|
inst_xsmaddadp :: inst_xsmaddadp_vs_vs_vs
|
|
emit_xsmaddadp :: emit_xsmaddadp_vs_vs_vs
|
|
inst_xsmaddmsp :: inst_xsmaddmsp_vs_vs_vs
|
|
emit_xsmaddmsp :: emit_xsmaddmsp_vs_vs_vs
|
|
inst_xsmaddmdp :: inst_xsmaddmdp_vs_vs_vs
|
|
emit_xsmaddmdp :: emit_xsmaddmdp_vs_vs_vs
|
|
inst_xsmsubasp :: inst_xsmsubasp_vs_vs_vs
|
|
emit_xsmsubasp :: emit_xsmsubasp_vs_vs_vs
|
|
inst_xsmsubadp :: inst_xsmsubadp_vs_vs_vs
|
|
emit_xsmsubadp :: emit_xsmsubadp_vs_vs_vs
|
|
inst_xsmsubmsp :: inst_xsmsubmsp_vs_vs_vs
|
|
emit_xsmsubmsp :: emit_xsmsubmsp_vs_vs_vs
|
|
inst_xsmsubmdp :: inst_xsmsubmdp_vs_vs_vs
|
|
emit_xsmsubmdp :: emit_xsmsubmdp_vs_vs_vs
|
|
inst_xsnmaddasp :: inst_xsnmaddasp_vs_vs_vs
|
|
emit_xsnmaddasp :: emit_xsnmaddasp_vs_vs_vs
|
|
inst_xsnmaddadp :: inst_xsnmaddadp_vs_vs_vs
|
|
emit_xsnmaddadp :: emit_xsnmaddadp_vs_vs_vs
|
|
inst_xsnmaddmsp :: inst_xsnmaddmsp_vs_vs_vs
|
|
emit_xsnmaddmsp :: emit_xsnmaddmsp_vs_vs_vs
|
|
inst_xsnmaddmdp :: inst_xsnmaddmdp_vs_vs_vs
|
|
emit_xsnmaddmdp :: emit_xsnmaddmdp_vs_vs_vs
|
|
inst_xsnmsubasp :: inst_xsnmsubasp_vs_vs_vs
|
|
emit_xsnmsubasp :: emit_xsnmsubasp_vs_vs_vs
|
|
inst_xsnmsubadp :: inst_xsnmsubadp_vs_vs_vs
|
|
emit_xsnmsubadp :: emit_xsnmsubadp_vs_vs_vs
|
|
inst_xsnmsubmsp :: inst_xsnmsubmsp_vs_vs_vs
|
|
emit_xsnmsubmsp :: emit_xsnmsubmsp_vs_vs_vs
|
|
inst_xsnmsubmdp :: inst_xsnmsubmdp_vs_vs_vs
|
|
emit_xsnmsubmdp :: emit_xsnmsubmdp_vs_vs_vs
|
|
inst_xsmaxdp :: inst_xsmaxdp_vs_vs_vs
|
|
emit_xsmaxdp :: emit_xsmaxdp_vs_vs_vs
|
|
inst_xsmindp :: inst_xsmindp_vs_vs_vs
|
|
emit_xsmindp :: emit_xsmindp_vs_vs_vs
|
|
inst_xsmaxcdp :: inst_xsmaxcdp_vs_vs_vs
|
|
emit_xsmaxcdp :: emit_xsmaxcdp_vs_vs_vs
|
|
inst_xsmincdp :: inst_xsmincdp_vs_vs_vs
|
|
emit_xsmincdp :: emit_xsmincdp_vs_vs_vs
|
|
inst_xsmaxjdp :: inst_xsmaxjdp_vs_vs_vs
|
|
emit_xsmaxjdp :: emit_xsmaxjdp_vs_vs_vs
|
|
inst_xsminjdp :: inst_xsminjdp_vs_vs_vs
|
|
emit_xsminjdp :: emit_xsminjdp_vs_vs_vs
|
|
inst_xscmpodp :: inst_xscmpodp_crf_vs_vs
|
|
emit_xscmpodp :: emit_xscmpodp_crf_vs_vs
|
|
inst_xscmpudp :: inst_xscmpudp_crf_vs_vs
|
|
emit_xscmpudp :: emit_xscmpudp_crf_vs_vs
|
|
inst_xscmpeqdp :: inst_xscmpeqdp_vs_vs_vs
|
|
emit_xscmpeqdp :: emit_xscmpeqdp_vs_vs_vs
|
|
inst_xscmpgtdp :: inst_xscmpgtdp_vs_vs_vs
|
|
emit_xscmpgtdp :: emit_xscmpgtdp_vs_vs_vs
|
|
inst_xscmpgedp :: inst_xscmpgedp_vs_vs_vs
|
|
emit_xscmpgedp :: emit_xscmpgedp_vs_vs_vs
|
|
inst_xscpsgndp :: inst_xscpsgndp_vs_vs_vs
|
|
emit_xscpsgndp :: emit_xscpsgndp_vs_vs_vs
|
|
inst_xsabsdp :: inst_xsabsdp_vs_vs
|
|
emit_xsabsdp :: emit_xsabsdp_vs_vs
|
|
inst_xsnabsdp :: inst_xsnabsdp_vs_vs
|
|
emit_xsnabsdp :: emit_xsnabsdp_vs_vs
|
|
inst_xsnegdp :: inst_xsnegdp_vs_vs
|
|
emit_xsnegdp :: emit_xsnegdp_vs_vs
|
|
inst_xscvdpsp :: inst_xscvdpsp_vs_vs
|
|
emit_xscvdpsp :: emit_xscvdpsp_vs_vs
|
|
inst_xscvspdp :: inst_xscvspdp_vs_vs
|
|
emit_xscvspdp :: emit_xscvspdp_vs_vs
|
|
inst_xscvdpsxds :: inst_xscvdpsxds_vs_vs
|
|
emit_xscvdpsxds :: emit_xscvdpsxds_vs_vs
|
|
inst_xscvdpuxds :: inst_xscvdpuxds_vs_vs
|
|
emit_xscvdpuxds :: emit_xscvdpuxds_vs_vs
|
|
inst_xscvsxddp :: inst_xscvsxddp_vs_vs
|
|
emit_xscvsxddp :: emit_xscvsxddp_vs_vs
|
|
inst_xscvuxddp :: inst_xscvuxddp_vs_vs
|
|
emit_xscvuxddp :: emit_xscvuxddp_vs_vs
|
|
inst_xscvdpsxws :: inst_xscvdpsxws_vs_vs
|
|
emit_xscvdpsxws :: emit_xscvdpsxws_vs_vs
|
|
inst_xscvdpuxws :: inst_xscvdpuxws_vs_vs
|
|
emit_xscvdpuxws :: emit_xscvdpuxws_vs_vs
|
|
inst_xscvdphp :: inst_xscvdphp_vs_vs
|
|
emit_xscvdphp :: emit_xscvdphp_vs_vs
|
|
inst_xscvhpdp :: inst_xscvhpdp_vs_vs
|
|
emit_xscvhpdp :: emit_xscvhpdp_vs_vs
|
|
inst_xscvspdpn :: inst_xscvspdpn_vs_vs
|
|
emit_xscvspdpn :: emit_xscvspdpn_vs_vs
|
|
inst_xscvdpspn :: inst_xscvdpspn_vs_vs
|
|
emit_xscvdpspn :: emit_xscvdpspn_vs_vs
|
|
inst_xsrdpi :: inst_xsrdpi_vs_vs
|
|
emit_xsrdpi :: emit_xsrdpi_vs_vs
|
|
inst_xsrdpim :: inst_xsrdpim_vs_vs
|
|
emit_xsrdpim :: emit_xsrdpim_vs_vs
|
|
inst_xsrdpip :: inst_xsrdpip_vs_vs
|
|
emit_xsrdpip :: emit_xsrdpip_vs_vs
|
|
inst_xsrdpiz :: inst_xsrdpiz_vs_vs
|
|
emit_xsrdpiz :: emit_xsrdpiz_vs_vs
|
|
inst_xsrdpic :: inst_xsrdpic_vs_vs
|
|
emit_xsrdpic :: emit_xsrdpic_vs_vs
|
|
inst_xsrsp :: inst_xsrsp_vs_vs
|
|
emit_xsrsp :: emit_xsrsp_vs_vs
|
|
inst_xsiexpdp :: inst_xsiexpdp_vs_r_r
|
|
emit_xsiexpdp :: emit_xsiexpdp_vs_r_r
|
|
inst_xsxexpdp :: inst_xsxexpdp_r_vs
|
|
emit_xsxexpdp :: emit_xsxexpdp_r_vs
|
|
inst_xsxsigdp :: inst_xsxsigdp_r_vs
|
|
emit_xsxsigdp :: emit_xsxsigdp_r_vs
|
|
inst_xvaddsp :: inst_xvaddsp_vs_vs_vs
|
|
emit_xvaddsp :: emit_xvaddsp_vs_vs_vs
|
|
inst_xvadddp :: inst_xvadddp_vs_vs_vs
|
|
emit_xvadddp :: emit_xvadddp_vs_vs_vs
|
|
inst_xvsubsp :: inst_xvsubsp_vs_vs_vs
|
|
emit_xvsubsp :: emit_xvsubsp_vs_vs_vs
|
|
inst_xvsubdp :: inst_xvsubdp_vs_vs_vs
|
|
emit_xvsubdp :: emit_xvsubdp_vs_vs_vs
|
|
inst_xvmulsp :: inst_xvmulsp_vs_vs_vs
|
|
emit_xvmulsp :: emit_xvmulsp_vs_vs_vs
|
|
inst_xvmuldp :: inst_xvmuldp_vs_vs_vs
|
|
emit_xvmuldp :: emit_xvmuldp_vs_vs_vs
|
|
inst_xvdivsp :: inst_xvdivsp_vs_vs_vs
|
|
emit_xvdivsp :: emit_xvdivsp_vs_vs_vs
|
|
inst_xvdivdp :: inst_xvdivdp_vs_vs_vs
|
|
emit_xvdivdp :: emit_xvdivdp_vs_vs_vs
|
|
inst_xvsqrtsp :: inst_xvsqrtsp_vs_vs
|
|
emit_xvsqrtsp :: emit_xvsqrtsp_vs_vs
|
|
inst_xvsqrtdp :: inst_xvsqrtdp_vs_vs
|
|
emit_xvsqrtdp :: emit_xvsqrtdp_vs_vs
|
|
inst_xvresp :: inst_xvresp_vs_vs
|
|
emit_xvresp :: emit_xvresp_vs_vs
|
|
inst_xvredp :: inst_xvredp_vs_vs
|
|
emit_xvredp :: emit_xvredp_vs_vs
|
|
inst_xvrsqrtesp :: inst_xvrsqrtesp_vs_vs
|
|
emit_xvrsqrtesp :: emit_xvrsqrtesp_vs_vs
|
|
inst_xvrsqrtedp :: inst_xvrsqrtedp_vs_vs
|
|
emit_xvrsqrtedp :: emit_xvrsqrtedp_vs_vs
|
|
inst_xvmaddasp :: inst_xvmaddasp_vs_vs_vs
|
|
emit_xvmaddasp :: emit_xvmaddasp_vs_vs_vs
|
|
inst_xvmaddadp :: inst_xvmaddadp_vs_vs_vs
|
|
emit_xvmaddadp :: emit_xvmaddadp_vs_vs_vs
|
|
inst_xvmaddmsp :: inst_xvmaddmsp_vs_vs_vs
|
|
emit_xvmaddmsp :: emit_xvmaddmsp_vs_vs_vs
|
|
inst_xvmaddmdp :: inst_xvmaddmdp_vs_vs_vs
|
|
emit_xvmaddmdp :: emit_xvmaddmdp_vs_vs_vs
|
|
inst_xvmsubasp :: inst_xvmsubasp_vs_vs_vs
|
|
emit_xvmsubasp :: emit_xvmsubasp_vs_vs_vs
|
|
inst_xvmsubadp :: inst_xvmsubadp_vs_vs_vs
|
|
emit_xvmsubadp :: emit_xvmsubadp_vs_vs_vs
|
|
inst_xvmsubmsp :: inst_xvmsubmsp_vs_vs_vs
|
|
emit_xvmsubmsp :: emit_xvmsubmsp_vs_vs_vs
|
|
inst_xvmsubmdp :: inst_xvmsubmdp_vs_vs_vs
|
|
emit_xvmsubmdp :: emit_xvmsubmdp_vs_vs_vs
|
|
inst_xvnmaddasp :: inst_xvnmaddasp_vs_vs_vs
|
|
emit_xvnmaddasp :: emit_xvnmaddasp_vs_vs_vs
|
|
inst_xvnmaddadp :: inst_xvnmaddadp_vs_vs_vs
|
|
emit_xvnmaddadp :: emit_xvnmaddadp_vs_vs_vs
|
|
inst_xvnmaddmsp :: inst_xvnmaddmsp_vs_vs_vs
|
|
emit_xvnmaddmsp :: emit_xvnmaddmsp_vs_vs_vs
|
|
inst_xvnmaddmdp :: inst_xvnmaddmdp_vs_vs_vs
|
|
emit_xvnmaddmdp :: emit_xvnmaddmdp_vs_vs_vs
|
|
inst_xvnmsubasp :: inst_xvnmsubasp_vs_vs_vs
|
|
emit_xvnmsubasp :: emit_xvnmsubasp_vs_vs_vs
|
|
inst_xvnmsubadp :: inst_xvnmsubadp_vs_vs_vs
|
|
emit_xvnmsubadp :: emit_xvnmsubadp_vs_vs_vs
|
|
inst_xvnmsubmsp :: inst_xvnmsubmsp_vs_vs_vs
|
|
emit_xvnmsubmsp :: emit_xvnmsubmsp_vs_vs_vs
|
|
inst_xvnmsubmdp :: inst_xvnmsubmdp_vs_vs_vs
|
|
emit_xvnmsubmdp :: emit_xvnmsubmdp_vs_vs_vs
|
|
inst_xvmaxsp :: inst_xvmaxsp_vs_vs_vs
|
|
emit_xvmaxsp :: emit_xvmaxsp_vs_vs_vs
|
|
inst_xvmaxdp :: inst_xvmaxdp_vs_vs_vs
|
|
emit_xvmaxdp :: emit_xvmaxdp_vs_vs_vs
|
|
inst_xvminsp :: inst_xvminsp_vs_vs_vs
|
|
emit_xvminsp :: emit_xvminsp_vs_vs_vs
|
|
inst_xvmindp :: inst_xvmindp_vs_vs_vs
|
|
emit_xvmindp :: emit_xvmindp_vs_vs_vs
|
|
inst_xvcmpeqsp :: inst_xvcmpeqsp_vs_vs_vs
|
|
emit_xvcmpeqsp :: emit_xvcmpeqsp_vs_vs_vs
|
|
inst_xvcmpeqsp_dot :: inst_xvcmpeqsp_dot_vs_vs_vs
|
|
emit_xvcmpeqsp_dot :: emit_xvcmpeqsp_dot_vs_vs_vs
|
|
inst_xvcmpeqdp :: inst_xvcmpeqdp_vs_vs_vs
|
|
emit_xvcmpeqdp :: emit_xvcmpeqdp_vs_vs_vs
|
|
inst_xvcmpeqdp_dot :: inst_xvcmpeqdp_dot_vs_vs_vs
|
|
emit_xvcmpeqdp_dot :: emit_xvcmpeqdp_dot_vs_vs_vs
|
|
inst_xvcmpgtsp :: inst_xvcmpgtsp_vs_vs_vs
|
|
emit_xvcmpgtsp :: emit_xvcmpgtsp_vs_vs_vs
|
|
inst_xvcmpgtsp_dot :: inst_xvcmpgtsp_dot_vs_vs_vs
|
|
emit_xvcmpgtsp_dot :: emit_xvcmpgtsp_dot_vs_vs_vs
|
|
inst_xvcmpgtdp :: inst_xvcmpgtdp_vs_vs_vs
|
|
emit_xvcmpgtdp :: emit_xvcmpgtdp_vs_vs_vs
|
|
inst_xvcmpgtdp_dot :: inst_xvcmpgtdp_dot_vs_vs_vs
|
|
emit_xvcmpgtdp_dot :: emit_xvcmpgtdp_dot_vs_vs_vs
|
|
inst_xvcmpgesp :: inst_xvcmpgesp_vs_vs_vs
|
|
emit_xvcmpgesp :: emit_xvcmpgesp_vs_vs_vs
|
|
inst_xvcmpgesp_dot :: inst_xvcmpgesp_dot_vs_vs_vs
|
|
emit_xvcmpgesp_dot :: emit_xvcmpgesp_dot_vs_vs_vs
|
|
inst_xvcmpgedp :: inst_xvcmpgedp_vs_vs_vs
|
|
emit_xvcmpgedp :: emit_xvcmpgedp_vs_vs_vs
|
|
inst_xvcmpgedp_dot :: inst_xvcmpgedp_dot_vs_vs_vs
|
|
emit_xvcmpgedp_dot :: emit_xvcmpgedp_dot_vs_vs_vs
|
|
inst_xvcpsgnsp :: inst_xvcpsgnsp_vs_vs_vs
|
|
emit_xvcpsgnsp :: emit_xvcpsgnsp_vs_vs_vs
|
|
inst_xvcpsgndp :: inst_xvcpsgndp_vs_vs_vs
|
|
emit_xvcpsgndp :: emit_xvcpsgndp_vs_vs_vs
|
|
inst_xvabssp :: inst_xvabssp_vs_vs
|
|
emit_xvabssp :: emit_xvabssp_vs_vs
|
|
inst_xvabsdp :: inst_xvabsdp_vs_vs
|
|
emit_xvabsdp :: emit_xvabsdp_vs_vs
|
|
inst_xvnabssp :: inst_xvnabssp_vs_vs
|
|
emit_xvnabssp :: emit_xvnabssp_vs_vs
|
|
inst_xvnabsdp :: inst_xvnabsdp_vs_vs
|
|
emit_xvnabsdp :: emit_xvnabsdp_vs_vs
|
|
inst_xvnegsp :: inst_xvnegsp_vs_vs
|
|
emit_xvnegsp :: emit_xvnegsp_vs_vs
|
|
inst_xvnegdp :: inst_xvnegdp_vs_vs
|
|
emit_xvnegdp :: emit_xvnegdp_vs_vs
|
|
inst_xvcvspdp :: inst_xvcvspdp_vs_vs
|
|
emit_xvcvspdp :: emit_xvcvspdp_vs_vs
|
|
inst_xvcvdpsp :: inst_xvcvdpsp_vs_vs
|
|
emit_xvcvdpsp :: emit_xvcvdpsp_vs_vs
|
|
inst_xvcvspsxds :: inst_xvcvspsxds_vs_vs
|
|
emit_xvcvspsxds :: emit_xvcvspsxds_vs_vs
|
|
inst_xvcvspuxds :: inst_xvcvspuxds_vs_vs
|
|
emit_xvcvspuxds :: emit_xvcvspuxds_vs_vs
|
|
inst_xvcvdpsxds :: inst_xvcvdpsxds_vs_vs
|
|
emit_xvcvdpsxds :: emit_xvcvdpsxds_vs_vs
|
|
inst_xvcvdpuxds :: inst_xvcvdpuxds_vs_vs
|
|
emit_xvcvdpuxds :: emit_xvcvdpuxds_vs_vs
|
|
inst_xvcvspsxws :: inst_xvcvspsxws_vs_vs
|
|
emit_xvcvspsxws :: emit_xvcvspsxws_vs_vs
|
|
inst_xvcvspuxws :: inst_xvcvspuxws_vs_vs
|
|
emit_xvcvspuxws :: emit_xvcvspuxws_vs_vs
|
|
inst_xvcvdpsxws :: inst_xvcvdpsxws_vs_vs
|
|
emit_xvcvdpsxws :: emit_xvcvdpsxws_vs_vs
|
|
inst_xvcvdpuxws :: inst_xvcvdpuxws_vs_vs
|
|
emit_xvcvdpuxws :: emit_xvcvdpuxws_vs_vs
|
|
inst_xvcvsxdsp :: inst_xvcvsxdsp_vs_vs
|
|
emit_xvcvsxdsp :: emit_xvcvsxdsp_vs_vs
|
|
inst_xvcvuxdsp :: inst_xvcvuxdsp_vs_vs
|
|
emit_xvcvuxdsp :: emit_xvcvuxdsp_vs_vs
|
|
inst_xvcvsxddp :: inst_xvcvsxddp_vs_vs
|
|
emit_xvcvsxddp :: emit_xvcvsxddp_vs_vs
|
|
inst_xvcvuxddp :: inst_xvcvuxddp_vs_vs
|
|
emit_xvcvuxddp :: emit_xvcvuxddp_vs_vs
|
|
inst_xvcvsxwsp :: inst_xvcvsxwsp_vs_vs
|
|
emit_xvcvsxwsp :: emit_xvcvsxwsp_vs_vs
|
|
inst_xvcvuxwsp :: inst_xvcvuxwsp_vs_vs
|
|
emit_xvcvuxwsp :: emit_xvcvuxwsp_vs_vs
|
|
inst_xvcvsxwdp :: inst_xvcvsxwdp_vs_vs
|
|
emit_xvcvsxwdp :: emit_xvcvsxwdp_vs_vs
|
|
inst_xvcvuxwdp :: inst_xvcvuxwdp_vs_vs
|
|
emit_xvcvuxwdp :: emit_xvcvuxwdp_vs_vs
|
|
inst_xvrspi :: inst_xvrspi_vs_vs
|
|
emit_xvrspi :: emit_xvrspi_vs_vs
|
|
inst_xvrspim :: inst_xvrspim_vs_vs
|
|
emit_xvrspim :: emit_xvrspim_vs_vs
|
|
inst_xvrspip :: inst_xvrspip_vs_vs
|
|
emit_xvrspip :: emit_xvrspip_vs_vs
|
|
inst_xvrspiz :: inst_xvrspiz_vs_vs
|
|
emit_xvrspiz :: emit_xvrspiz_vs_vs
|
|
inst_xvrspic :: inst_xvrspic_vs_vs
|
|
emit_xvrspic :: emit_xvrspic_vs_vs
|
|
inst_xvrdpi :: inst_xvrdpi_vs_vs
|
|
emit_xvrdpi :: emit_xvrdpi_vs_vs
|
|
inst_xvrdpim :: inst_xvrdpim_vs_vs
|
|
emit_xvrdpim :: emit_xvrdpim_vs_vs
|
|
inst_xvrdpip :: inst_xvrdpip_vs_vs
|
|
emit_xvrdpip :: emit_xvrdpip_vs_vs
|
|
inst_xvrdpiz :: inst_xvrdpiz_vs_vs
|
|
emit_xvrdpiz :: emit_xvrdpiz_vs_vs
|
|
inst_xvrdpic :: inst_xvrdpic_vs_vs
|
|
emit_xvrdpic :: emit_xvrdpic_vs_vs
|
|
inst_xviexpsp :: inst_xviexpsp_vs_vs_vs
|
|
emit_xviexpsp :: emit_xviexpsp_vs_vs_vs
|
|
inst_xviexpdp :: inst_xviexpdp_vs_vs_vs
|
|
emit_xviexpdp :: emit_xviexpdp_vs_vs_vs
|
|
inst_xvxexpsp :: inst_xvxexpsp_vs_vs
|
|
emit_xvxexpsp :: emit_xvxexpsp_vs_vs
|
|
inst_xvxexpdp :: inst_xvxexpdp_vs_vs
|
|
emit_xvxexpdp :: emit_xvxexpdp_vs_vs
|
|
inst_xvxsigsp :: inst_xvxsigsp_vs_vs
|
|
emit_xvxsigsp :: emit_xvxsigsp_vs_vs
|
|
inst_xvxsigdp :: inst_xvxsigdp_vs_vs
|
|
emit_xvxsigdp :: emit_xvxsigdp_vs_vs
|
|
inst_xvtstdcsp :: inst_xvtstdcsp_vs_vs_imm
|
|
emit_xvtstdcsp :: emit_xvtstdcsp_vs_vs_imm
|
|
inst_xvtstdcdp :: inst_xvtstdcdp_vs_vs_imm
|
|
emit_xvtstdcdp :: emit_xvtstdcdp_vs_vs_imm
|
|
inst_xststdcsp :: inst_xststdcsp_crf_vs_imm
|
|
emit_xststdcsp :: emit_xststdcsp_crf_vs_imm
|
|
inst_xststdcdp :: inst_xststdcdp_crf_vs_imm
|
|
emit_xststdcdp :: emit_xststdcdp_crf_vs_imm
|
|
inst_xstsqrtdp :: inst_xstsqrtdp_crf_vs
|
|
emit_xstsqrtdp :: emit_xstsqrtdp_crf_vs
|
|
inst_xvtsqrtsp :: inst_xvtsqrtsp_crf_vs
|
|
emit_xvtsqrtsp :: emit_xvtsqrtsp_crf_vs
|
|
inst_xvtsqrtdp :: inst_xvtsqrtdp_crf_vs
|
|
emit_xvtsqrtdp :: emit_xvtsqrtdp_crf_vs
|
|
inst_xstdivdp :: inst_xstdivdp_crf_vs_vs
|
|
emit_xstdivdp :: emit_xstdivdp_crf_vs_vs
|
|
inst_xvtdivsp :: inst_xvtdivsp_crf_vs_vs
|
|
emit_xvtdivsp :: emit_xvtdivsp_crf_vs_vs
|
|
inst_xvtdivdp :: inst_xvtdivdp_crf_vs_vs
|
|
emit_xvtdivdp :: emit_xvtdivdp_crf_vs_vs
|
|
inst_xxland :: inst_xxland_vs_vs_vs
|
|
emit_xxland :: emit_xxland_vs_vs_vs
|
|
inst_xxlandc :: inst_xxlandc_vs_vs_vs
|
|
emit_xxlandc :: emit_xxlandc_vs_vs_vs
|
|
inst_xxlor :: inst_xxlor_vs_vs_vs
|
|
emit_xxlor :: emit_xxlor_vs_vs_vs
|
|
inst_xxlxor :: inst_xxlxor_vs_vs_vs
|
|
emit_xxlxor :: emit_xxlxor_vs_vs_vs
|
|
inst_xxlnor :: inst_xxlnor_vs_vs_vs
|
|
emit_xxlnor :: emit_xxlnor_vs_vs_vs
|
|
inst_xxleqv :: inst_xxleqv_vs_vs_vs
|
|
emit_xxleqv :: emit_xxleqv_vs_vs_vs
|
|
inst_xxlnand :: inst_xxlnand_vs_vs_vs
|
|
emit_xxlnand :: emit_xxlnand_vs_vs_vs
|
|
inst_xxlorc :: inst_xxlorc_vs_vs_vs
|
|
emit_xxlorc :: emit_xxlorc_vs_vs_vs
|
|
inst_xxsel :: inst_xxsel_vs_vs_vs_vs
|
|
emit_xxsel :: emit_xxsel_vs_vs_vs_vs
|
|
inst_xxspltw :: inst_xxspltw_vs_vs_imm
|
|
emit_xxspltw :: emit_xxspltw_vs_vs_imm
|
|
inst_xxspltib :: inst_xxspltib_vs_uimm
|
|
emit_xxspltib :: emit_xxspltib_vs_uimm
|
|
inst_xxsldwi :: inst_xxsldwi_vs_vs_vs_imm
|
|
emit_xxsldwi :: emit_xxsldwi_vs_vs_vs_imm
|
|
inst_xxpermdi :: inst_xxpermdi_vs_vs_vs_imm
|
|
emit_xxpermdi :: emit_xxpermdi_vs_vs_vs_imm
|
|
inst_xxmrghw :: inst_xxmrghw_vs_vs_vs
|
|
emit_xxmrghw :: emit_xxmrghw_vs_vs_vs
|
|
inst_xxmrglw :: inst_xxmrglw_vs_vs_vs
|
|
emit_xxmrglw :: emit_xxmrglw_vs_vs_vs
|
|
inst_xxextractuw :: inst_xxextractuw_vs_vs_imm
|
|
emit_xxextractuw :: emit_xxextractuw_vs_vs_imm
|
|
inst_xxinsertw :: inst_xxinsertw_vs_vs_imm
|
|
emit_xxinsertw :: emit_xxinsertw_vs_vs_imm
|
|
inst_xxspltiw :: inst_xxspltiw_vs_simm
|
|
emit_xxspltiw :: emit_xxspltiw_vs_simm
|
|
inst_xxspltidp :: inst_xxspltidp_vs_simm
|
|
emit_xxspltidp :: emit_xxspltidp_vs_simm
|
|
inst_xxsplti32dx :: inst_xxsplti32dx_vs_simm
|
|
emit_xxsplti32dx :: emit_xxsplti32dx_vs_simm
|
|
inst_xscmpeqqp :: inst_xscmpeqqp_crf_v_v
|
|
emit_xscmpeqqp :: emit_xscmpeqqp_crf_v_v
|
|
inst_xscmpgtqp :: inst_xscmpgtqp_crf_v_v
|
|
emit_xscmpgtqp :: emit_xscmpgtqp_crf_v_v
|
|
inst_xscmpgeqp :: inst_xscmpgeqp_crf_v_v
|
|
emit_xscmpgeqp :: emit_xscmpgeqp_crf_v_v
|
|
inst_xsaddqp :: inst_xsaddqp_v_v_v
|
|
emit_xsaddqp :: emit_xsaddqp_v_v_v
|
|
inst_xsaddqpo :: inst_xsaddqpo_v_v_v
|
|
emit_xsaddqpo :: emit_xsaddqpo_v_v_v
|
|
inst_xssubqp :: inst_xssubqp_v_v_v
|
|
emit_xssubqp :: emit_xssubqp_v_v_v
|
|
inst_xssubqpo :: inst_xssubqpo_v_v_v
|
|
emit_xssubqpo :: emit_xssubqpo_v_v_v
|
|
inst_xsmulqp :: inst_xsmulqp_v_v_v
|
|
emit_xsmulqp :: emit_xsmulqp_v_v_v
|
|
inst_xsmulqpo :: inst_xsmulqpo_v_v_v
|
|
emit_xsmulqpo :: emit_xsmulqpo_v_v_v
|
|
inst_xsdivqp :: inst_xsdivqp_v_v_v
|
|
emit_xsdivqp :: emit_xsdivqp_v_v_v
|
|
inst_xsdivqpo :: inst_xsdivqpo_v_v_v
|
|
emit_xsdivqpo :: emit_xsdivqpo_v_v_v
|
|
inst_xssqrtqp :: inst_xssqrtqp_v_v
|
|
emit_xssqrtqp :: emit_xssqrtqp_v_v
|
|
inst_xssqrtqpo :: inst_xssqrtqpo_v_v
|
|
emit_xssqrtqpo :: emit_xssqrtqpo_v_v
|
|
inst_xsmaddqp :: inst_xsmaddqp_v_v_v
|
|
emit_xsmaddqp :: emit_xsmaddqp_v_v_v
|
|
inst_xsmaddqpo :: inst_xsmaddqpo_v_v_v
|
|
emit_xsmaddqpo :: emit_xsmaddqpo_v_v_v
|
|
inst_xsmsubqp :: inst_xsmsubqp_v_v_v
|
|
emit_xsmsubqp :: emit_xsmsubqp_v_v_v
|
|
inst_xsmsubqpo :: inst_xsmsubqpo_v_v_v
|
|
emit_xsmsubqpo :: emit_xsmsubqpo_v_v_v
|
|
inst_xsnmaddqp :: inst_xsnmaddqp_v_v_v
|
|
emit_xsnmaddqp :: emit_xsnmaddqp_v_v_v
|
|
inst_xsnmaddqpo :: inst_xsnmaddqpo_v_v_v
|
|
emit_xsnmaddqpo :: emit_xsnmaddqpo_v_v_v
|
|
inst_xsnmsubqp :: inst_xsnmsubqp_v_v_v
|
|
emit_xsnmsubqp :: emit_xsnmsubqp_v_v_v
|
|
inst_xsnmsubqpo :: inst_xsnmsubqpo_v_v_v
|
|
emit_xsnmsubqpo :: emit_xsnmsubqpo_v_v_v
|
|
inst_xsabsqp :: inst_xsabsqp_v_v
|
|
emit_xsabsqp :: emit_xsabsqp_v_v
|
|
inst_xsnabsqp :: inst_xsnabsqp_v_v
|
|
emit_xsnabsqp :: emit_xsnabsqp_v_v
|
|
inst_xsnegqp :: inst_xsnegqp_v_v
|
|
emit_xsnegqp :: emit_xsnegqp_v_v
|
|
inst_xscpsgnqp :: inst_xscpsgnqp_v_v_v
|
|
emit_xscpsgnqp :: emit_xscpsgnqp_v_v_v
|
|
inst_xscmpoqp :: inst_xscmpoqp_crf_v_v
|
|
emit_xscmpoqp :: emit_xscmpoqp_crf_v_v
|
|
inst_xscmpuqp :: inst_xscmpuqp_crf_v_v
|
|
emit_xscmpuqp :: emit_xscmpuqp_crf_v_v
|
|
inst_xststdcqp :: inst_xststdcqp_crf_v_imm
|
|
emit_xststdcqp :: emit_xststdcqp_crf_v_imm
|
|
inst_xsrqpi :: inst_xsrqpi_imm_v_v_imm
|
|
emit_xsrqpi :: emit_xsrqpi_imm_v_v_imm
|
|
inst_xsrqpix :: inst_xsrqpix_imm_v_v_imm
|
|
emit_xsrqpix :: emit_xsrqpix_imm_v_v_imm
|
|
inst_xsrqpxp :: inst_xsrqpxp_imm_v_v_imm
|
|
emit_xsrqpxp :: emit_xsrqpxp_imm_v_v_imm
|
|
inst_xsxexpqp :: inst_xsxexpqp_v_v
|
|
emit_xsxexpqp :: emit_xsxexpqp_v_v
|
|
inst_xsxsigqp :: inst_xsxsigqp_v_v
|
|
emit_xsxsigqp :: emit_xsxsigqp_v_v
|
|
inst_xsiexpqp :: inst_xsiexpqp_v_v_v
|
|
emit_xsiexpqp :: emit_xsiexpqp_v_v_v
|
|
inst_xscvqpdp :: inst_xscvqpdp_v_v
|
|
emit_xscvqpdp :: emit_xscvqpdp_v_v
|
|
inst_xscvqpdpo :: inst_xscvqpdpo_v_v
|
|
emit_xscvqpdpo :: emit_xscvqpdpo_v_v
|
|
inst_xscvdpqp :: inst_xscvdpqp_v_v
|
|
emit_xscvdpqp :: emit_xscvdpqp_v_v
|
|
inst_xscvqpsdz :: inst_xscvqpsdz_v_v
|
|
emit_xscvqpsdz :: emit_xscvqpsdz_v_v
|
|
inst_xscvqpswz :: inst_xscvqpswz_v_v
|
|
emit_xscvqpswz :: emit_xscvqpswz_v_v
|
|
inst_xscvqpudz :: inst_xscvqpudz_v_v
|
|
emit_xscvqpudz :: emit_xscvqpudz_v_v
|
|
inst_xscvqpuwz :: inst_xscvqpuwz_v_v
|
|
emit_xscvqpuwz :: emit_xscvqpuwz_v_v
|
|
inst_xscvsdqp :: inst_xscvsdqp_v_v
|
|
emit_xscvsdqp :: emit_xscvsdqp_v_v
|
|
inst_xscvudqp :: inst_xscvudqp_v_v
|
|
emit_xscvudqp :: emit_xscvudqp_v_v
|
|
inst_dadd :: inst_dadd_fr_fr_fr
|
|
emit_dadd :: emit_dadd_fr_fr_fr
|
|
inst_dadd_dot :: inst_dadd_dot_fr_fr_fr
|
|
emit_dadd_dot :: emit_dadd_dot_fr_fr_fr
|
|
inst_dsub :: inst_dsub_fr_fr_fr
|
|
emit_dsub :: emit_dsub_fr_fr_fr
|
|
inst_dsub_dot :: inst_dsub_dot_fr_fr_fr
|
|
emit_dsub_dot :: emit_dsub_dot_fr_fr_fr
|
|
inst_dmul :: inst_dmul_fr_fr_fr
|
|
emit_dmul :: emit_dmul_fr_fr_fr
|
|
inst_dmul_dot :: inst_dmul_dot_fr_fr_fr
|
|
emit_dmul_dot :: emit_dmul_dot_fr_fr_fr
|
|
inst_ddiv :: inst_ddiv_fr_fr_fr
|
|
emit_ddiv :: emit_ddiv_fr_fr_fr
|
|
inst_ddiv_dot :: inst_ddiv_dot_fr_fr_fr
|
|
emit_ddiv_dot :: emit_ddiv_dot_fr_fr_fr
|
|
inst_dcmpu :: inst_dcmpu_crf_fr_fr
|
|
emit_dcmpu :: emit_dcmpu_crf_fr_fr
|
|
inst_dcmpo :: inst_dcmpo_crf_fr_fr
|
|
emit_dcmpo :: emit_dcmpo_crf_fr_fr
|
|
inst_drsp :: inst_drsp_fr_fr
|
|
emit_drsp :: emit_drsp_fr_fr
|
|
inst_drsp_dot :: inst_drsp_dot_fr_fr
|
|
emit_drsp_dot :: emit_drsp_dot_fr_fr
|
|
inst_dctdp :: inst_dctdp_fr_fr
|
|
emit_dctdp :: emit_dctdp_fr_fr
|
|
inst_dctdp_dot :: inst_dctdp_dot_fr_fr
|
|
emit_dctdp_dot :: emit_dctdp_dot_fr_fr
|
|
inst_dxex :: inst_dxex_fr_fr
|
|
emit_dxex :: emit_dxex_fr_fr
|
|
inst_dxex_dot :: inst_dxex_dot_fr_fr
|
|
emit_dxex_dot :: emit_dxex_dot_fr_fr
|
|
inst_diex :: inst_diex_fr_fr_fr
|
|
emit_diex :: emit_diex_fr_fr_fr
|
|
inst_diex_dot :: inst_diex_dot_fr_fr_fr
|
|
emit_diex_dot :: emit_diex_dot_fr_fr_fr
|
|
inst_drrnd :: inst_drrnd_fr_fr_fr_imm
|
|
emit_drrnd :: emit_drrnd_fr_fr_fr_imm
|
|
inst_drrnd_dot :: inst_drrnd_dot_fr_fr_fr_imm
|
|
emit_drrnd_dot :: emit_drrnd_dot_fr_fr_fr_imm
|
|
inst_drintx :: inst_drintx_imm_fr_fr_imm
|
|
emit_drintx :: emit_drintx_imm_fr_fr_imm
|
|
inst_drintx_dot :: inst_drintx_dot_imm_fr_fr_imm
|
|
emit_drintx_dot :: emit_drintx_dot_imm_fr_fr_imm
|
|
inst_drintn :: inst_drintn_imm_fr_fr_imm
|
|
emit_drintn :: emit_drintn_imm_fr_fr_imm
|
|
inst_drintn_dot :: inst_drintn_dot_imm_fr_fr_imm
|
|
emit_drintn_dot :: emit_drintn_dot_imm_fr_fr_imm
|
|
inst_dqua :: inst_dqua_fr_fr_fr_imm
|
|
emit_dqua :: emit_dqua_fr_fr_fr_imm
|
|
inst_dqua_dot :: inst_dqua_dot_fr_fr_fr_imm
|
|
emit_dqua_dot :: emit_dqua_dot_fr_fr_fr_imm
|
|
inst_dquai :: inst_dquai_imm_fr_fr_imm
|
|
emit_dquai :: emit_dquai_imm_fr_fr_imm
|
|
inst_dquai_dot :: inst_dquai_dot_imm_fr_fr_imm
|
|
emit_dquai_dot :: emit_dquai_dot_imm_fr_fr_imm
|
|
inst_dscli :: inst_dscli_fr_fr_imm
|
|
emit_dscli :: emit_dscli_fr_fr_imm
|
|
inst_dscli_dot :: inst_dscli_dot_fr_fr_imm
|
|
emit_dscli_dot :: emit_dscli_dot_fr_fr_imm
|
|
inst_dscri :: inst_dscri_fr_fr_imm
|
|
emit_dscri :: emit_dscri_fr_fr_imm
|
|
inst_dscri_dot :: inst_dscri_dot_fr_fr_imm
|
|
emit_dscri_dot :: emit_dscri_dot_fr_fr_imm
|
|
inst_dcffix :: inst_dcffix_fr_fr
|
|
emit_dcffix :: emit_dcffix_fr_fr
|
|
inst_dcffix_dot :: inst_dcffix_dot_fr_fr
|
|
emit_dcffix_dot :: emit_dcffix_dot_fr_fr
|
|
inst_dctfix :: inst_dctfix_fr_fr
|
|
emit_dctfix :: emit_dctfix_fr_fr
|
|
inst_dctfix_dot :: inst_dctfix_dot_fr_fr
|
|
emit_dctfix_dot :: emit_dctfix_dot_fr_fr
|
|
inst_dtstdc :: inst_dtstdc_crf_fr_imm
|
|
emit_dtstdc :: emit_dtstdc_crf_fr_imm
|
|
inst_dtstdg :: inst_dtstdg_crf_fr_imm
|
|
emit_dtstdg :: emit_dtstdg_crf_fr_imm
|
|
inst_dtstex :: inst_dtstex_crf_fr_fr
|
|
emit_dtstex :: emit_dtstex_crf_fr_fr
|
|
inst_dtstsf :: inst_dtstsf_crf_fr_fr
|
|
emit_dtstsf :: emit_dtstsf_crf_fr_fr
|
|
inst_denbcd :: inst_denbcd_imm_fr_fr
|
|
emit_denbcd :: emit_denbcd_imm_fr_fr
|
|
inst_denbcd_dot :: inst_denbcd_dot_imm_fr_fr
|
|
emit_denbcd_dot :: emit_denbcd_dot_imm_fr_fr
|
|
inst_ddedpd :: inst_ddedpd_imm_fr_fr
|
|
emit_ddedpd :: emit_ddedpd_imm_fr_fr
|
|
inst_ddedpd_dot :: inst_ddedpd_dot_imm_fr_fr
|
|
emit_ddedpd_dot :: emit_ddedpd_dot_imm_fr_fr
|
|
inst_daddq :: inst_daddq_fr_fr_fr
|
|
emit_daddq :: emit_daddq_fr_fr_fr
|
|
inst_daddq_dot :: inst_daddq_dot_fr_fr_fr
|
|
emit_daddq_dot :: emit_daddq_dot_fr_fr_fr
|
|
inst_dsubq :: inst_dsubq_fr_fr_fr
|
|
emit_dsubq :: emit_dsubq_fr_fr_fr
|
|
inst_dsubq_dot :: inst_dsubq_dot_fr_fr_fr
|
|
emit_dsubq_dot :: emit_dsubq_dot_fr_fr_fr
|
|
inst_dmulq :: inst_dmulq_fr_fr_fr
|
|
emit_dmulq :: emit_dmulq_fr_fr_fr
|
|
inst_dmulq_dot :: inst_dmulq_dot_fr_fr_fr
|
|
emit_dmulq_dot :: emit_dmulq_dot_fr_fr_fr
|
|
inst_ddivq :: inst_ddivq_fr_fr_fr
|
|
emit_ddivq :: emit_ddivq_fr_fr_fr
|
|
inst_ddivq_dot :: inst_ddivq_dot_fr_fr_fr
|
|
emit_ddivq_dot :: emit_ddivq_dot_fr_fr_fr
|
|
inst_dcmpuq :: inst_dcmpuq_crf_fr_fr
|
|
emit_dcmpuq :: emit_dcmpuq_crf_fr_fr
|
|
inst_dcmpoq :: inst_dcmpoq_crf_fr_fr
|
|
emit_dcmpoq :: emit_dcmpoq_crf_fr_fr
|
|
inst_dctfixq :: inst_dctfixq_fr_fr
|
|
emit_dctfixq :: emit_dctfixq_fr_fr
|
|
inst_dctfixq_dot :: inst_dctfixq_dot_fr_fr
|
|
emit_dctfixq_dot :: emit_dctfixq_dot_fr_fr
|
|
inst_xxmtacc :: inst_xxmtacc_imm
|
|
emit_xxmtacc :: emit_xxmtacc_imm
|
|
inst_xxmfacc :: inst_xxmfacc_imm
|
|
emit_xxmfacc :: emit_xxmfacc_imm
|
|
inst_xxsetaccz :: inst_xxsetaccz_imm
|
|
emit_xxsetaccz :: emit_xxsetaccz_imm
|
|
inst_xvf16ger2 :: inst_xvf16ger2_imm_vs_vs
|
|
emit_xvf16ger2 :: emit_xvf16ger2_imm_vs_vs
|
|
inst_xvf16ger2pp :: inst_xvf16ger2pp_imm_vs_vs
|
|
emit_xvf16ger2pp :: emit_xvf16ger2pp_imm_vs_vs
|
|
inst_xvf16ger2pn :: inst_xvf16ger2pn_imm_vs_vs
|
|
emit_xvf16ger2pn :: emit_xvf16ger2pn_imm_vs_vs
|
|
inst_xvf16ger2np :: inst_xvf16ger2np_imm_vs_vs
|
|
emit_xvf16ger2np :: emit_xvf16ger2np_imm_vs_vs
|
|
inst_xvf16ger2nn :: inst_xvf16ger2nn_imm_vs_vs
|
|
emit_xvf16ger2nn :: emit_xvf16ger2nn_imm_vs_vs
|
|
inst_xvf32ger :: inst_xvf32ger_imm_vs_vs
|
|
emit_xvf32ger :: emit_xvf32ger_imm_vs_vs
|
|
inst_xvf32gerpp :: inst_xvf32gerpp_imm_vs_vs
|
|
emit_xvf32gerpp :: emit_xvf32gerpp_imm_vs_vs
|
|
inst_xvf32gerpn :: inst_xvf32gerpn_imm_vs_vs
|
|
emit_xvf32gerpn :: emit_xvf32gerpn_imm_vs_vs
|
|
inst_xvf32gernp :: inst_xvf32gernp_imm_vs_vs
|
|
emit_xvf32gernp :: emit_xvf32gernp_imm_vs_vs
|
|
inst_xvf32gernn :: inst_xvf32gernn_imm_vs_vs
|
|
emit_xvf32gernn :: emit_xvf32gernn_imm_vs_vs
|
|
inst_xvf64ger :: inst_xvf64ger_imm_vs_vs
|
|
emit_xvf64ger :: emit_xvf64ger_imm_vs_vs
|
|
inst_xvf64gerpp :: inst_xvf64gerpp_imm_vs_vs
|
|
emit_xvf64gerpp :: emit_xvf64gerpp_imm_vs_vs
|
|
inst_xvf64gerpn :: inst_xvf64gerpn_imm_vs_vs
|
|
emit_xvf64gerpn :: emit_xvf64gerpn_imm_vs_vs
|
|
inst_xvf64gernp :: inst_xvf64gernp_imm_vs_vs
|
|
emit_xvf64gernp :: emit_xvf64gernp_imm_vs_vs
|
|
inst_xvf64gernn :: inst_xvf64gernn_imm_vs_vs
|
|
emit_xvf64gernn :: emit_xvf64gernn_imm_vs_vs
|
|
inst_xvbf16ger2 :: inst_xvbf16ger2_imm_vs_vs
|
|
emit_xvbf16ger2 :: emit_xvbf16ger2_imm_vs_vs
|
|
inst_xvbf16ger2pp :: inst_xvbf16ger2pp_imm_vs_vs
|
|
emit_xvbf16ger2pp :: emit_xvbf16ger2pp_imm_vs_vs
|
|
inst_xvbf16ger2pn :: inst_xvbf16ger2pn_imm_vs_vs
|
|
emit_xvbf16ger2pn :: emit_xvbf16ger2pn_imm_vs_vs
|
|
inst_xvbf16ger2np :: inst_xvbf16ger2np_imm_vs_vs
|
|
emit_xvbf16ger2np :: emit_xvbf16ger2np_imm_vs_vs
|
|
inst_xvbf16ger2nn :: inst_xvbf16ger2nn_imm_vs_vs
|
|
emit_xvbf16ger2nn :: emit_xvbf16ger2nn_imm_vs_vs
|
|
inst_xvi4ger8 :: inst_xvi4ger8_imm_vs_vs
|
|
emit_xvi4ger8 :: emit_xvi4ger8_imm_vs_vs
|
|
inst_xvi4ger8pp :: inst_xvi4ger8pp_imm_vs_vs
|
|
emit_xvi4ger8pp :: emit_xvi4ger8pp_imm_vs_vs
|
|
inst_xvi8ger4 :: inst_xvi8ger4_imm_vs_vs
|
|
emit_xvi8ger4 :: emit_xvi8ger4_imm_vs_vs
|
|
inst_xvi8ger4pp :: inst_xvi8ger4pp_imm_vs_vs
|
|
emit_xvi8ger4pp :: emit_xvi8ger4pp_imm_vs_vs
|
|
inst_xvi8ger4spp :: inst_xvi8ger4spp_imm_vs_vs
|
|
emit_xvi8ger4spp :: emit_xvi8ger4spp_imm_vs_vs
|
|
inst_xvi16ger2 :: inst_xvi16ger2_imm_vs_vs
|
|
emit_xvi16ger2 :: emit_xvi16ger2_imm_vs_vs
|
|
inst_xvi16ger2pp :: inst_xvi16ger2pp_imm_vs_vs
|
|
emit_xvi16ger2pp :: emit_xvi16ger2pp_imm_vs_vs
|
|
inst_xvi16ger2s :: inst_xvi16ger2s_imm_vs_vs
|
|
emit_xvi16ger2s :: emit_xvi16ger2s_imm_vs_vs
|
|
inst_xvi16ger2spp :: inst_xvi16ger2spp_imm_vs_vs
|
|
emit_xvi16ger2spp :: emit_xvi16ger2spp_imm_vs_vs
|
|
inst_vstribl :: inst_vstribl_v_v
|
|
emit_vstribl :: emit_vstribl_v_v
|
|
inst_vstribr :: inst_vstribr_v_v
|
|
emit_vstribr :: emit_vstribr_v_v
|
|
inst_vstribl_dot :: inst_vstribl_dot_v_v
|
|
emit_vstribl_dot :: emit_vstribl_dot_v_v
|
|
inst_vstribr_dot :: inst_vstribr_dot_v_v
|
|
emit_vstribr_dot :: emit_vstribr_dot_v_v
|
|
inst_vstrihl :: inst_vstrihl_v_v
|
|
emit_vstrihl :: emit_vstrihl_v_v
|
|
inst_vstrihr :: inst_vstrihr_v_v
|
|
emit_vstrihr :: emit_vstrihr_v_v
|
|
inst_vstrihl_dot :: inst_vstrihl_dot_v_v
|
|
emit_vstrihl_dot :: emit_vstrihl_dot_v_v
|
|
inst_vstrihr_dot :: inst_vstrihr_dot_v_v
|
|
emit_vstrihr_dot :: emit_vstrihr_dot_v_v
|
|
inst_vmsumcud :: inst_vmsumcud_v_v_v_v
|
|
emit_vmsumcud :: emit_vmsumcud_v_v_v_v
|
|
inst_vcfuged :: inst_vcfuged_v_v_v
|
|
emit_vcfuged :: emit_vcfuged_v_v_v
|
|
inst_vpdepd :: inst_vpdepd_v_v_v
|
|
emit_vpdepd :: emit_vpdepd_v_v_v
|
|
inst_vpextd :: inst_vpextd_v_v_v
|
|
emit_vpextd :: emit_vpextd_v_v_v
|
|
inst_vgnb :: inst_vgnb_r_v_imm
|
|
emit_vgnb :: emit_vgnb_r_v_imm
|
|
inst_vsldbi :: inst_vsldbi_v_v_v_imm
|
|
emit_vsldbi :: emit_vsldbi_v_v_v_imm
|
|
inst_vsrdbi :: inst_vsrdbi_v_v_v_imm
|
|
emit_vsrdbi :: emit_vsrdbi_v_v_v_imm
|
|
inst_vclzdm :: inst_vclzdm_v_v_v
|
|
emit_vclzdm :: emit_vclzdm_v_v_v
|
|
inst_vctzdm :: inst_vctzdm_v_v_v
|
|
emit_vctzdm :: emit_vctzdm_v_v_v
|
|
inst_vclrlb :: inst_vclrlb_v_v_r
|
|
emit_vclrlb :: emit_vclrlb_v_v_r
|
|
inst_vclrrb :: inst_vclrrb_v_v_r
|
|
emit_vclrrb :: emit_vclrrb_v_v_r
|
|
inst_vexpandbm :: inst_vexpandbm_v_v
|
|
emit_vexpandbm :: emit_vexpandbm_v_v
|
|
inst_vexpandhm :: inst_vexpandhm_v_v
|
|
emit_vexpandhm :: emit_vexpandhm_v_v
|
|
inst_vexpandwm :: inst_vexpandwm_v_v
|
|
emit_vexpandwm :: emit_vexpandwm_v_v
|
|
inst_vexpanddm :: inst_vexpanddm_v_v
|
|
emit_vexpanddm :: emit_vexpanddm_v_v
|
|
inst_vexpandqm :: inst_vexpandqm_v_v
|
|
emit_vexpandqm :: emit_vexpandqm_v_v
|
|
inst_vextractbm :: inst_vextractbm_r_v
|
|
emit_vextractbm :: emit_vextractbm_r_v
|
|
inst_vextracthm :: inst_vextracthm_r_v
|
|
emit_vextracthm :: emit_vextracthm_r_v
|
|
inst_vextractwm :: inst_vextractwm_r_v
|
|
emit_vextractwm :: emit_vextractwm_r_v
|
|
inst_vextractdm :: inst_vextractdm_r_v
|
|
emit_vextractdm :: emit_vextractdm_r_v
|
|
inst_vextractqm :: inst_vextractqm_r_v
|
|
emit_vextractqm :: emit_vextractqm_r_v
|
|
inst_vcntmbb :: inst_vcntmbb_r_v_imm
|
|
emit_vcntmbb :: emit_vcntmbb_r_v_imm
|
|
inst_vcntmbh :: inst_vcntmbh_r_v_imm
|
|
emit_vcntmbh :: emit_vcntmbh_r_v_imm
|
|
inst_vcntmbw :: inst_vcntmbw_r_v_imm
|
|
emit_vcntmbw :: emit_vcntmbw_r_v_imm
|
|
inst_vcntmbd :: inst_vcntmbd_r_v_imm
|
|
emit_vcntmbd :: emit_vcntmbd_r_v_imm
|
|
inst_mtvsrbm :: inst_mtvsrbm_vs_r
|
|
emit_mtvsrbm :: emit_mtvsrbm_vs_r
|
|
inst_mtvsrhm :: inst_mtvsrhm_vs_r
|
|
emit_mtvsrhm :: emit_mtvsrhm_vs_r
|
|
inst_mtvsrwm :: inst_mtvsrwm_vs_r
|
|
emit_mtvsrwm :: emit_mtvsrwm_vs_r
|
|
inst_mtvsrdm :: inst_mtvsrdm_vs_r
|
|
emit_mtvsrdm :: emit_mtvsrdm_vs_r
|
|
inst_mtvsrqm :: inst_mtvsrqm_vs_r
|
|
emit_mtvsrqm :: emit_mtvsrqm_vs_r
|
|
inst_copy :: inst_copy_r_r
|
|
emit_copy :: emit_copy_r_r
|
|
inst_paste_dot :: inst_paste_dot_r_r
|
|
emit_paste_dot :: emit_paste_dot_r_r
|
|
inst_lbzcix :: inst_lbzcix_r_r_r
|
|
emit_lbzcix :: emit_lbzcix_r_r_r
|
|
inst_lhzcix :: inst_lhzcix_r_r_r
|
|
emit_lhzcix :: emit_lhzcix_r_r_r
|
|
inst_lwzcix :: inst_lwzcix_r_r_r
|
|
emit_lwzcix :: emit_lwzcix_r_r_r
|
|
inst_ldcix :: inst_ldcix_r_r_r
|
|
emit_ldcix :: emit_ldcix_r_r_r
|
|
inst_stbcix :: inst_stbcix_r_r_r
|
|
emit_stbcix :: emit_stbcix_r_r_r
|
|
inst_sthcix :: inst_sthcix_r_r_r
|
|
emit_sthcix :: emit_sthcix_r_r_r
|
|
inst_stwcix :: inst_stwcix_r_r_r
|
|
emit_stwcix :: emit_stwcix_r_r_r
|
|
inst_stdcix :: inst_stdcix_r_r_r
|
|
emit_stdcix :: emit_stdcix_r_r_r
|
|
inst_tbegin_dot :: inst_tbegin_dot_imm
|
|
emit_tbegin_dot :: emit_tbegin_dot_imm
|
|
inst_tend_dot :: inst_tend_dot_none
|
|
emit_tend_dot :: emit_tend_dot_none
|
|
inst_tabort_dot :: inst_tabort_dot_r
|
|
emit_tabort_dot :: emit_tabort_dot_r
|
|
inst_tabortwc_dot :: inst_tabortwc_dot_imm_r_r
|
|
emit_tabortwc_dot :: emit_tabortwc_dot_imm_r_r
|
|
inst_tabortwci_dot :: inst_tabortwci_dot_imm_r_imm
|
|
emit_tabortwci_dot :: emit_tabortwci_dot_imm_r_imm
|
|
inst_tabortdc_dot :: inst_tabortdc_dot_imm_r_r
|
|
emit_tabortdc_dot :: emit_tabortdc_dot_imm_r_r
|
|
inst_tabortdci_dot :: inst_tabortdci_dot_imm_r_imm
|
|
emit_tabortdci_dot :: emit_tabortdci_dot_imm_r_imm
|
|
inst_treclaim_dot :: inst_treclaim_dot_r
|
|
emit_treclaim_dot :: emit_treclaim_dot_r
|
|
inst_trechkpt_dot :: inst_trechkpt_dot_none
|
|
emit_trechkpt_dot :: emit_trechkpt_dot_none
|
|
inst_tsuspend_dot :: inst_tsuspend_dot_none
|
|
emit_tsuspend_dot :: emit_tsuspend_dot_none
|
|
inst_tresume_dot :: inst_tresume_dot_none
|
|
emit_tresume_dot :: emit_tresume_dot_none
|
|
inst_tcheck :: inst_tcheck_crf
|
|
emit_tcheck :: emit_tcheck_crf
|
|
inst_addg6s :: inst_addg6s_r_r_r
|
|
emit_addg6s :: emit_addg6s_r_r_r
|
|
inst_cbcdtd :: inst_cbcdtd_r_r
|
|
emit_cbcdtd :: emit_cbcdtd_r_r
|
|
inst_cdtbcd :: inst_cdtbcd_r_r
|
|
emit_cdtbcd :: emit_cdtbcd_r_r
|
|
inst_rfebb :: inst_rfebb_imm
|
|
emit_rfebb :: emit_rfebb_imm
|
|
inst_rfdi :: inst_rfdi_none
|
|
emit_rfdi :: emit_rfdi_none
|
|
inst_msgsync :: inst_msgsync_none
|
|
emit_msgsync :: emit_msgsync_none
|
|
inst_isel :: inst_isel_r_rz_r_crb
|
|
emit_isel :: emit_isel_r_rz_r_crb
|
|
inst_dcbtt :: inst_dcbtt_mem
|
|
emit_dcbtt :: emit_dcbtt_mem
|
|
inst_dcbtstt :: inst_dcbtstt_mem
|
|
emit_dcbtstt :: emit_dcbtstt_mem
|
|
inst_vextublx :: inst_vextublx_r_r_v
|
|
emit_vextublx :: emit_vextublx_r_r_v
|
|
inst_vextuhlx :: inst_vextuhlx_r_r_v
|
|
emit_vextuhlx :: emit_vextuhlx_r_r_v
|
|
inst_vextuwlx :: inst_vextuwlx_r_r_v
|
|
emit_vextuwlx :: emit_vextuwlx_r_r_v
|
|
inst_vextubrx :: inst_vextubrx_r_r_v
|
|
emit_vextubrx :: emit_vextubrx_r_r_v
|
|
inst_vextuhrx :: inst_vextuhrx_r_r_v
|
|
emit_vextuhrx :: emit_vextuhrx_r_r_v
|
|
inst_vextuwrx :: inst_vextuwrx_r_r_v
|
|
emit_vextuwrx :: emit_vextuwrx_r_r_v
|
|
inst_vinsbvlx :: inst_vinsbvlx_v_r_v
|
|
emit_vinsbvlx :: emit_vinsbvlx_v_r_v
|
|
inst_vinshvlx :: inst_vinshvlx_v_r_v
|
|
emit_vinshvlx :: emit_vinshvlx_v_r_v
|
|
inst_vinswvlx :: inst_vinswvlx_v_r_v
|
|
emit_vinswvlx :: emit_vinswvlx_v_r_v
|
|
inst_vinsbvrx :: inst_vinsbvrx_v_r_v
|
|
emit_vinsbvrx :: emit_vinsbvrx_v_r_v
|
|
inst_vinshvrx :: inst_vinshvrx_v_r_v
|
|
emit_vinshvrx :: emit_vinshvrx_v_r_v
|
|
inst_vinswvrx :: inst_vinswvrx_v_r_v
|
|
emit_vinswvrx :: emit_vinswvrx_v_r_v
|
|
inst_vinsblx :: inst_vinsblx_v_r_r
|
|
emit_vinsblx :: emit_vinsblx_v_r_r
|
|
inst_vinshlx :: inst_vinshlx_v_r_r
|
|
emit_vinshlx :: emit_vinshlx_v_r_r
|
|
inst_vinswlx :: inst_vinswlx_v_r_r
|
|
emit_vinswlx :: emit_vinswlx_v_r_r
|
|
inst_vinsdlx :: inst_vinsdlx_v_r_r
|
|
emit_vinsdlx :: emit_vinsdlx_v_r_r
|
|
inst_vinsbrx :: inst_vinsbrx_v_r_r
|
|
emit_vinsbrx :: emit_vinsbrx_v_r_r
|
|
inst_vinshrx :: inst_vinshrx_v_r_r
|
|
emit_vinshrx :: emit_vinshrx_v_r_r
|
|
inst_vinswrx :: inst_vinswrx_v_r_r
|
|
emit_vinswrx :: emit_vinswrx_v_r_r
|
|
inst_vinsdrx :: inst_vinsdrx_v_r_r
|
|
emit_vinsdrx :: emit_vinsdrx_v_r_r
|
|
inst_vinsw :: inst_vinsw_v_r_imm
|
|
emit_vinsw :: emit_vinsw_v_r_imm
|
|
inst_vinsd :: inst_vinsd_v_r_imm
|
|
emit_vinsd :: emit_vinsd_v_r_imm
|
|
inst_vextdubvlx :: inst_vextdubvlx_v_v_v_r
|
|
emit_vextdubvlx :: emit_vextdubvlx_v_v_v_r
|
|
inst_vextduhvlx :: inst_vextduhvlx_v_v_v_r
|
|
emit_vextduhvlx :: emit_vextduhvlx_v_v_v_r
|
|
inst_vextduwvlx :: inst_vextduwvlx_v_v_v_r
|
|
emit_vextduwvlx :: emit_vextduwvlx_v_v_v_r
|
|
inst_vextddvlx :: inst_vextddvlx_v_v_v_r
|
|
emit_vextddvlx :: emit_vextddvlx_v_v_v_r
|
|
inst_vextdubvrx :: inst_vextdubvrx_v_v_v_r
|
|
emit_vextdubvrx :: emit_vextdubvrx_v_v_v_r
|
|
inst_vextduhvrx :: inst_vextduhvrx_v_v_v_r
|
|
emit_vextduhvrx :: emit_vextduhvrx_v_v_v_r
|
|
inst_vextduwvrx :: inst_vextduwvrx_v_v_v_r
|
|
emit_vextduwvrx :: emit_vextduwvrx_v_v_v_r
|
|
inst_vextddvrx :: inst_vextddvrx_v_v_v_r
|
|
emit_vextddvrx :: emit_vextddvrx_v_v_v_r
|
|
inst_lxvrbx :: inst_lxvrbx_vs_r_r
|
|
emit_lxvrbx :: emit_lxvrbx_vs_r_r
|
|
inst_lxvrhx :: inst_lxvrhx_vs_r_r
|
|
emit_lxvrhx :: emit_lxvrhx_vs_r_r
|
|
inst_lxvrwx :: inst_lxvrwx_vs_r_r
|
|
emit_lxvrwx :: emit_lxvrwx_vs_r_r
|
|
inst_lxvrdx :: inst_lxvrdx_vs_r_r
|
|
emit_lxvrdx :: emit_lxvrdx_vs_r_r
|
|
inst_stxvrbx :: inst_stxvrbx_vs_r_r
|
|
emit_stxvrbx :: emit_stxvrbx_vs_r_r
|
|
inst_stxvrhx :: inst_stxvrhx_vs_r_r
|
|
emit_stxvrhx :: emit_stxvrhx_vs_r_r
|
|
inst_stxvrwx :: inst_stxvrwx_vs_r_r
|
|
emit_stxvrwx :: emit_stxvrwx_vs_r_r
|
|
inst_stxvrdx :: inst_stxvrdx_vs_r_r
|
|
emit_stxvrdx :: emit_stxvrdx_vs_r_r
|
|
inst_lxvkq :: inst_lxvkq_vs_imm
|
|
emit_lxvkq :: emit_lxvkq_vs_imm
|
|
inst_xsmaxcqp :: inst_xsmaxcqp_v_v_v
|
|
emit_xsmaxcqp :: emit_xsmaxcqp_v_v_v
|
|
inst_xsmincqp :: inst_xsmincqp_v_v_v
|
|
emit_xsmincqp :: emit_xsmincqp_v_v_v
|
|
inst_vrlq :: inst_vrlq_v_v_v
|
|
emit_vrlq :: emit_vrlq_v_v_v
|
|
inst_vrlqmi :: inst_vrlqmi_v_v_v
|
|
emit_vrlqmi :: emit_vrlqmi_v_v_v
|
|
inst_vrlqnm :: inst_vrlqnm_v_v_v
|
|
emit_vrlqnm :: emit_vrlqnm_v_v_v
|
|
inst_vslq :: inst_vslq_v_v_v
|
|
emit_vslq :: emit_vslq_v_v_v
|
|
inst_vsrq :: inst_vsrq_v_v_v
|
|
emit_vsrq :: emit_vsrq_v_v_v
|
|
inst_vsraq :: inst_vsraq_v_v_v
|
|
emit_vsraq :: emit_vsraq_v_v_v
|
|
inst_vmulesd :: inst_vmulesd_v_v_v
|
|
emit_vmulesd :: emit_vmulesd_v_v_v
|
|
inst_vmuleud :: inst_vmuleud_v_v_v
|
|
emit_vmuleud :: emit_vmuleud_v_v_v
|
|
inst_vmulosd :: inst_vmulosd_v_v_v
|
|
emit_vmulosd :: emit_vmulosd_v_v_v
|
|
inst_vmuloud :: inst_vmuloud_v_v_v
|
|
emit_vmuloud :: emit_vmuloud_v_v_v
|
|
inst_vmulld :: inst_vmulld_v_v_v
|
|
emit_vmulld :: emit_vmulld_v_v_v
|
|
inst_vmulhsw :: inst_vmulhsw_v_v_v
|
|
emit_vmulhsw :: emit_vmulhsw_v_v_v
|
|
inst_vmulhsd :: inst_vmulhsd_v_v_v
|
|
emit_vmulhsd :: emit_vmulhsd_v_v_v
|
|
inst_vmulhuw :: inst_vmulhuw_v_v_v
|
|
emit_vmulhuw :: emit_vmulhuw_v_v_v
|
|
inst_vmulhud :: inst_vmulhud_v_v_v
|
|
emit_vmulhud :: emit_vmulhud_v_v_v
|
|
inst_vdivsw :: inst_vdivsw_v_v_v
|
|
emit_vdivsw :: emit_vdivsw_v_v_v
|
|
inst_vdivuw :: inst_vdivuw_v_v_v
|
|
emit_vdivuw :: emit_vdivuw_v_v_v
|
|
inst_vdivsd :: inst_vdivsd_v_v_v
|
|
emit_vdivsd :: emit_vdivsd_v_v_v
|
|
inst_vdivud :: inst_vdivud_v_v_v
|
|
emit_vdivud :: emit_vdivud_v_v_v
|
|
inst_vdivsq :: inst_vdivsq_v_v_v
|
|
emit_vdivsq :: emit_vdivsq_v_v_v
|
|
inst_vdivuq :: inst_vdivuq_v_v_v
|
|
emit_vdivuq :: emit_vdivuq_v_v_v
|
|
inst_vdivesw :: inst_vdivesw_v_v_v
|
|
emit_vdivesw :: emit_vdivesw_v_v_v
|
|
inst_vdiveuw :: inst_vdiveuw_v_v_v
|
|
emit_vdiveuw :: emit_vdiveuw_v_v_v
|
|
inst_vdivesd :: inst_vdivesd_v_v_v
|
|
emit_vdivesd :: emit_vdivesd_v_v_v
|
|
inst_vdiveud :: inst_vdiveud_v_v_v
|
|
emit_vdiveud :: emit_vdiveud_v_v_v
|
|
inst_vdivesq :: inst_vdivesq_v_v_v
|
|
emit_vdivesq :: emit_vdivesq_v_v_v
|
|
inst_vdiveuq :: inst_vdiveuq_v_v_v
|
|
emit_vdiveuq :: emit_vdiveuq_v_v_v
|
|
inst_vmodsw :: inst_vmodsw_v_v_v
|
|
emit_vmodsw :: emit_vmodsw_v_v_v
|
|
inst_vmoduw :: inst_vmoduw_v_v_v
|
|
emit_vmoduw :: emit_vmoduw_v_v_v
|
|
inst_vmodsd :: inst_vmodsd_v_v_v
|
|
emit_vmodsd :: emit_vmodsd_v_v_v
|
|
inst_vmodud :: inst_vmodud_v_v_v
|
|
emit_vmodud :: emit_vmodud_v_v_v
|
|
inst_vmodsq :: inst_vmodsq_v_v_v
|
|
emit_vmodsq :: emit_vmodsq_v_v_v
|
|
inst_vmoduq :: inst_vmoduq_v_v_v
|
|
emit_vmoduq :: emit_vmoduq_v_v_v
|
|
inst_setb :: inst_setb_r_crf
|
|
emit_setb :: emit_setb_r_crf
|
|
inst_mcrxrx :: inst_mcrxrx_crf
|
|
emit_mcrxrx :: emit_mcrxrx_crf
|
|
inst_xvcvbf16spn :: inst_xvcvbf16spn_vs_vs
|
|
emit_xvcvbf16spn :: emit_xvcvbf16spn_vs_vs
|
|
inst_xvcvspbf16 :: inst_xvcvspbf16_vs_vs
|
|
emit_xvcvspbf16 :: emit_xvcvspbf16_vs_vs
|
|
inst_xxgenpcvbm :: inst_xxgenpcvbm_vs_v_imm
|
|
emit_xxgenpcvbm :: emit_xxgenpcvbm_vs_v_imm
|
|
inst_xxgenpcvhm :: inst_xxgenpcvhm_vs_v_imm
|
|
emit_xxgenpcvhm :: emit_xxgenpcvhm_vs_v_imm
|
|
inst_xxgenpcvwm :: inst_xxgenpcvwm_vs_v_imm
|
|
emit_xxgenpcvwm :: emit_xxgenpcvwm_vs_v_imm
|
|
inst_xxgenpcvdm :: inst_xxgenpcvdm_vs_v_imm
|
|
emit_xxgenpcvdm :: emit_xxgenpcvdm_vs_v_imm
|
|
inst_xxblendvb :: inst_xxblendvb_vs_vs_vs_vs
|
|
emit_xxblendvb :: emit_xxblendvb_vs_vs_vs_vs
|
|
inst_xxblendvh :: inst_xxblendvh_vs_vs_vs_vs
|
|
emit_xxblendvh :: emit_xxblendvh_vs_vs_vs_vs
|
|
inst_xxblendvw :: inst_xxblendvw_vs_vs_vs_vs
|
|
emit_xxblendvw :: emit_xxblendvw_vs_vs_vs_vs
|
|
inst_xxblendvd :: inst_xxblendvd_vs_vs_vs_vs
|
|
emit_xxblendvd :: emit_xxblendvd_vs_vs_vs_vs
|
|
inst_xxpermx :: inst_xxpermx_vs_vs_vs_vs
|
|
emit_xxpermx :: emit_xxpermx_vs_vs_vs_vs
|
|
inst_xxeval :: inst_xxeval_vs_vs_vs_vs
|
|
emit_xxeval :: emit_xxeval_vs_vs_vs_vs
|
|
inst_xxperm :: inst_xxperm_vs_vs_vs
|
|
emit_xxperm :: emit_xxperm_vs_vs_vs
|
|
inst_pld :: inst_pld_r_mem
|
|
emit_pld :: emit_pld_r_mem
|
|
inst_pstd :: inst_pstd_r_mem
|
|
emit_pstd :: emit_pstd_r_mem
|
|
inst_plwz :: inst_plwz_r_mem
|
|
emit_plwz :: emit_plwz_r_mem
|
|
inst_pstw :: inst_pstw_r_mem
|
|
emit_pstw :: emit_pstw_r_mem
|
|
inst_plbz :: inst_plbz_r_mem
|
|
emit_plbz :: emit_plbz_r_mem
|
|
inst_pstb :: inst_pstb_r_mem
|
|
emit_pstb :: emit_pstb_r_mem
|
|
inst_plhz :: inst_plhz_r_mem
|
|
emit_plhz :: emit_plhz_r_mem
|
|
inst_psth :: inst_psth_r_mem
|
|
emit_psth :: emit_psth_r_mem
|
|
inst_plha :: inst_plha_r_mem
|
|
emit_plha :: emit_plha_r_mem
|
|
inst_plwa :: inst_plwa_r_mem
|
|
emit_plwa :: emit_plwa_r_mem
|
|
inst_plfd :: inst_plfd_fr_mem
|
|
emit_plfd :: emit_plfd_fr_mem
|
|
inst_pstfd :: inst_pstfd_fr_mem
|
|
emit_pstfd :: emit_pstfd_fr_mem
|
|
inst_plfs :: inst_plfs_fr_mem
|
|
emit_plfs :: emit_plfs_fr_mem
|
|
inst_pstfs :: inst_pstfs_fr_mem
|
|
emit_pstfs :: emit_pstfs_fr_mem
|
|
inst_plxv :: inst_plxv_vs_mem
|
|
emit_plxv :: emit_plxv_vs_mem
|
|
inst_pstxv :: inst_pstxv_vs_mem
|
|
emit_pstxv :: emit_pstxv_vs_mem
|
|
inst_plxsd :: inst_plxsd_v_mem
|
|
emit_plxsd :: emit_plxsd_v_mem
|
|
inst_pstxsd :: inst_pstxsd_v_mem
|
|
emit_pstxsd :: emit_pstxsd_v_mem
|
|
inst_plxssp :: inst_plxssp_v_mem
|
|
emit_plxssp :: emit_plxssp_v_mem
|
|
inst_pstxssp :: inst_pstxssp_v_mem
|
|
emit_pstxssp :: emit_pstxssp_v_mem
|
|
inst_paddi :: inst_paddi_r_rz_simm
|
|
emit_paddi :: emit_paddi_r_rz_simm
|
|
inst_pli :: inst_pli_r_simm
|
|
emit_pli :: emit_pli_r_simm
|
|
inst_psubi :: inst_psubi_r_r_simm
|
|
emit_psubi :: emit_psubi_r_r_simm
|
|
inst_pmxvf32ger :: inst_pmxvf32ger_imm_vs_vs
|
|
emit_pmxvf32ger :: emit_pmxvf32ger_imm_vs_vs
|
|
inst_pmxvf64ger :: inst_pmxvf64ger_imm_vs_vs
|
|
emit_pmxvf64ger :: emit_pmxvf64ger_imm_vs_vs
|
|
inst_pmxvi4ger8 :: inst_pmxvi4ger8_imm_vs_vs
|
|
emit_pmxvi4ger8 :: emit_pmxvi4ger8_imm_vs_vs
|
|
inst_pmxvi8ger4 :: inst_pmxvi8ger4_imm_vs_vs
|
|
emit_pmxvi8ger4 :: emit_pmxvi8ger4_imm_vs_vs
|
|
inst_pmxvi16ger2 :: inst_pmxvi16ger2_imm_vs_vs
|
|
emit_pmxvi16ger2 :: emit_pmxvi16ger2_imm_vs_vs
|
|
inst_pmxvf16ger2 :: inst_pmxvf16ger2_imm_vs_vs
|
|
emit_pmxvf16ger2 :: emit_pmxvf16ger2_imm_vs_vs
|
|
inst_pmxvf16ger2pp :: inst_pmxvf16ger2pp_imm_vs_vs
|
|
emit_pmxvf16ger2pp :: emit_pmxvf16ger2pp_imm_vs_vs
|
|
inst_pmxvf16ger2pn :: inst_pmxvf16ger2pn_imm_vs_vs
|
|
emit_pmxvf16ger2pn :: emit_pmxvf16ger2pn_imm_vs_vs
|
|
inst_pmxvf16ger2np :: inst_pmxvf16ger2np_imm_vs_vs
|
|
emit_pmxvf16ger2np :: emit_pmxvf16ger2np_imm_vs_vs
|
|
inst_pmxvf16ger2nn :: inst_pmxvf16ger2nn_imm_vs_vs
|
|
emit_pmxvf16ger2nn :: emit_pmxvf16ger2nn_imm_vs_vs
|
|
inst_pmxvf32gerpp :: inst_pmxvf32gerpp_imm_vs_vs
|
|
emit_pmxvf32gerpp :: emit_pmxvf32gerpp_imm_vs_vs
|
|
inst_pmxvf32gerpn :: inst_pmxvf32gerpn_imm_vs_vs
|
|
emit_pmxvf32gerpn :: emit_pmxvf32gerpn_imm_vs_vs
|
|
inst_pmxvf32gernp :: inst_pmxvf32gernp_imm_vs_vs
|
|
emit_pmxvf32gernp :: emit_pmxvf32gernp_imm_vs_vs
|
|
inst_pmxvf32gernn :: inst_pmxvf32gernn_imm_vs_vs
|
|
emit_pmxvf32gernn :: emit_pmxvf32gernn_imm_vs_vs
|
|
inst_pmxvf64gerpp :: inst_pmxvf64gerpp_imm_vs_vs
|
|
emit_pmxvf64gerpp :: emit_pmxvf64gerpp_imm_vs_vs
|
|
inst_pmxvf64gerpn :: inst_pmxvf64gerpn_imm_vs_vs
|
|
emit_pmxvf64gerpn :: emit_pmxvf64gerpn_imm_vs_vs
|
|
inst_pmxvf64gernp :: inst_pmxvf64gernp_imm_vs_vs
|
|
emit_pmxvf64gernp :: emit_pmxvf64gernp_imm_vs_vs
|
|
inst_pmxvf64gernn :: inst_pmxvf64gernn_imm_vs_vs
|
|
emit_pmxvf64gernn :: emit_pmxvf64gernn_imm_vs_vs
|
|
inst_pmxvbf16ger2 :: inst_pmxvbf16ger2_imm_vs_vs
|
|
emit_pmxvbf16ger2 :: emit_pmxvbf16ger2_imm_vs_vs
|
|
inst_pmxvbf16ger2pp :: inst_pmxvbf16ger2pp_imm_vs_vs
|
|
emit_pmxvbf16ger2pp :: emit_pmxvbf16ger2pp_imm_vs_vs
|
|
inst_pmxvbf16ger2pn :: inst_pmxvbf16ger2pn_imm_vs_vs
|
|
emit_pmxvbf16ger2pn :: emit_pmxvbf16ger2pn_imm_vs_vs
|
|
inst_pmxvbf16ger2np :: inst_pmxvbf16ger2np_imm_vs_vs
|
|
emit_pmxvbf16ger2np :: emit_pmxvbf16ger2np_imm_vs_vs
|
|
inst_pmxvbf16ger2nn :: inst_pmxvbf16ger2nn_imm_vs_vs
|
|
emit_pmxvbf16ger2nn :: emit_pmxvbf16ger2nn_imm_vs_vs
|
|
inst_pmxvi4ger8pp :: inst_pmxvi4ger8pp_imm_vs_vs
|
|
emit_pmxvi4ger8pp :: emit_pmxvi4ger8pp_imm_vs_vs
|
|
inst_pmxvi8ger4pp :: inst_pmxvi8ger4pp_imm_vs_vs
|
|
emit_pmxvi8ger4pp :: emit_pmxvi8ger4pp_imm_vs_vs
|
|
inst_pmxvi8ger4spp :: inst_pmxvi8ger4spp_imm_vs_vs
|
|
emit_pmxvi8ger4spp :: emit_pmxvi8ger4spp_imm_vs_vs
|
|
inst_pmxvi16ger2pp :: inst_pmxvi16ger2pp_imm_vs_vs
|
|
emit_pmxvi16ger2pp :: emit_pmxvi16ger2pp_imm_vs_vs
|
|
inst_pmxvi16ger2s :: inst_pmxvi16ger2s_imm_vs_vs
|
|
emit_pmxvi16ger2s :: emit_pmxvi16ger2s_imm_vs_vs
|
|
inst_pmxvi16ger2spp :: inst_pmxvi16ger2spp_imm_vs_vs
|
|
emit_pmxvi16ger2spp :: emit_pmxvi16ger2spp_imm_vs_vs
|
|
inst_lxvp :: inst_lxvp_vs_mem
|
|
emit_lxvp :: emit_lxvp_vs_mem
|
|
inst_stxvp :: inst_stxvp_vs_mem
|
|
emit_stxvp :: emit_stxvp_vs_mem
|
|
inst_lxvpx :: inst_lxvpx_vs_r_r
|
|
emit_lxvpx :: emit_lxvpx_vs_r_r
|
|
inst_stxvpx :: inst_stxvpx_vs_r_r
|
|
emit_stxvpx :: emit_stxvpx_vs_r_r
|
|
inst_dcbi :: inst_dcbi_r_r
|
|
emit_dcbi :: emit_dcbi_r_r
|
|
inst_icbiep :: inst_icbiep_r_r
|
|
emit_icbiep :: emit_icbiep_r_r
|
|
inst_dcbtep :: inst_dcbtep_imm_r_r
|
|
emit_dcbtep :: emit_dcbtep_imm_r_r
|
|
inst_dcbtstep :: inst_dcbtstep_imm_r_r
|
|
emit_dcbtstep :: emit_dcbtstep_imm_r_r
|
|
inst_lbepx :: inst_lbepx_r_r_r
|
|
emit_lbepx :: emit_lbepx_r_r_r
|
|
inst_lhepx :: inst_lhepx_r_r_r
|
|
emit_lhepx :: emit_lhepx_r_r_r
|
|
inst_lwepx :: inst_lwepx_r_r_r
|
|
emit_lwepx :: emit_lwepx_r_r_r
|
|
inst_stbepx :: inst_stbepx_r_r_r
|
|
emit_stbepx :: emit_stbepx_r_r_r
|
|
inst_sthepx :: inst_sthepx_r_r_r
|
|
emit_sthepx :: emit_sthepx_r_r_r
|
|
inst_stwepx :: inst_stwepx_r_r_r
|
|
emit_stwepx :: emit_stwepx_r_r_r
|
|
inst_lfdepx :: inst_lfdepx_fr_r_r
|
|
emit_lfdepx :: emit_lfdepx_fr_r_r
|
|
inst_stfdepx :: inst_stfdepx_fr_r_r
|
|
emit_stfdepx :: emit_stfdepx_fr_r_r
|
|
inst_tlbsx :: inst_tlbsx_r_r
|
|
emit_tlbsx :: emit_tlbsx_r_r
|
|
inst_dccci :: inst_dccci_r_r
|
|
emit_dccci :: emit_dccci_r_r
|
|
inst_iccci :: inst_iccci_r_r
|
|
emit_iccci :: emit_iccci_r_r
|
|
inst_wrtee :: inst_wrtee_r
|
|
emit_wrtee :: emit_wrtee_r
|
|
inst_wrteei :: inst_wrteei_imm
|
|
emit_wrteei :: emit_wrteei_imm
|
|
inst_tlbre :: inst_tlbre_none
|
|
emit_tlbre :: emit_tlbre_none
|
|
inst_tlbwe :: inst_tlbwe_none
|
|
emit_tlbwe :: emit_tlbwe_none
|
|
inst_tlbivax :: inst_tlbivax_r_r
|
|
emit_tlbivax :: emit_tlbivax_r_r
|
|
inst_tlbilx :: inst_tlbilx_imm_r_r
|
|
emit_tlbilx :: emit_tlbilx_imm_r_r
|
|
inst_tlbld :: inst_tlbld_r
|
|
emit_tlbld :: emit_tlbld_r
|
|
inst_tlbli :: inst_tlbli_r
|
|
emit_tlbli :: emit_tlbli_r
|
|
inst_mfpmr :: inst_mfpmr_r_spr
|
|
emit_mfpmr :: emit_mfpmr_r_spr
|
|
inst_mtpmr :: inst_mtpmr_spr_r
|
|
emit_mtpmr :: emit_mtpmr_spr_r
|
|
inst_mfsr :: inst_mfsr_r_imm
|
|
emit_mfsr :: emit_mfsr_r_imm
|
|
inst_mtsr :: inst_mtsr_imm_r
|
|
emit_mtsr :: emit_mtsr_imm_r
|
|
inst_mfsrin :: inst_mfsrin_r_r
|
|
emit_mfsrin :: emit_mfsrin_r_r
|
|
inst_mtsrin :: inst_mtsrin_r_r
|
|
emit_mtsrin :: emit_mtsrin_r_r
|
|
inst_dst :: inst_dst_r_r_imm
|
|
emit_dst :: emit_dst_r_r_imm
|
|
inst_dstt :: inst_dstt_r_r_imm
|
|
emit_dstt :: emit_dstt_r_r_imm
|
|
inst_dstst :: inst_dstst_r_r_imm
|
|
emit_dstst :: emit_dstst_r_r_imm
|
|
inst_dststt :: inst_dststt_r_r_imm
|
|
emit_dststt :: emit_dststt_r_r_imm
|
|
inst_dss :: inst_dss_imm
|
|
emit_dss :: emit_dss_imm
|
|
inst_dssall :: inst_dssall_none
|
|
emit_dssall :: emit_dssall_none
|
|
inst_vsumsws :: inst_vsumsws_v_v_v
|
|
emit_vsumsws :: emit_vsumsws_v_v_v
|
|
inst_vsum2sws :: inst_vsum2sws_v_v_v
|
|
emit_vsum2sws :: emit_vsum2sws_v_v_v
|
|
inst_vsum4sbs :: inst_vsum4sbs_v_v_v
|
|
emit_vsum4sbs :: emit_vsum4sbs_v_v_v
|
|
inst_vsum4shs :: inst_vsum4shs_v_v_v
|
|
emit_vsum4shs :: emit_vsum4shs_v_v_v
|
|
inst_vsum4ubs :: inst_vsum4ubs_v_v_v
|
|
emit_vsum4ubs :: emit_vsum4ubs_v_v_v
|
|
inst_mffsce :: inst_mffsce_fr
|
|
emit_mffsce :: emit_mffsce_fr
|
|
inst_mffscdrn :: inst_mffscdrn_fr_fr
|
|
emit_mffscdrn :: emit_mffscdrn_fr_fr
|
|
inst_mffscdrni :: inst_mffscdrni_fr_imm
|
|
emit_mffscdrni :: emit_mffscdrni_fr_imm
|
|
inst_mffscrn :: inst_mffscrn_fr_fr
|
|
emit_mffscrn :: emit_mffscrn_fr_fr
|
|
inst_mffscrni :: inst_mffscrni_fr_imm
|
|
emit_mffscrni :: emit_mffscrni_fr_imm
|
|
inst_mffsl :: inst_mffsl_fr
|
|
emit_mffsl :: emit_mffsl_fr
|
|
inst_stop :: inst_stop_none
|
|
emit_stop :: emit_stop_none
|
|
inst_cpabort :: inst_cpabort_none
|
|
emit_cpabort :: emit_cpabort_none
|
|
inst_attn :: inst_attn_none
|
|
emit_attn :: emit_attn_none
|
|
inst_mtfprd :: inst_mtfprd_fr_r
|
|
emit_mtfprd :: emit_mtfprd_fr_r
|
|
inst_mffprd :: inst_mffprd_r_fr
|
|
emit_mffprd :: emit_mffprd_r_fr
|
|
inst_mtfprwa :: inst_mtfprwa_fr_r
|
|
emit_mtfprwa :: emit_mtfprwa_fr_r
|
|
inst_mtfprwz :: inst_mtfprwz_fr_r
|
|
emit_mtfprwz :: emit_mtfprwz_fr_r
|
|
inst_mffprwz :: inst_mffprwz_r_fr
|
|
emit_mffprwz :: emit_mffprwz_r_fr
|
|
inst_mfvsrld :: inst_mfvsrld_r_vs
|
|
emit_mfvsrld :: emit_mfvsrld_r_vs
|
|
inst_mtvsrdd :: inst_mtvsrdd_vs_r_r
|
|
emit_mtvsrdd :: emit_mtvsrdd_vs_r_r
|
|
inst_mtvsrws :: inst_mtvsrws_vs_r
|
|
emit_mtvsrws :: emit_mtvsrws_vs_r
|
|
inst_extswsli :: inst_extswsli_r_r_imm
|
|
emit_extswsli :: emit_extswsli_r_r_imm
|
|
inst_extswsli_dot :: inst_extswsli_dot_r_r_imm
|
|
emit_extswsli_dot :: emit_extswsli_dot_r_r_imm
|
|
inst_isellt :: inst_isellt_r_r_r
|
|
emit_isellt :: emit_isellt_r_r_r
|
|
inst_iselgt :: inst_iselgt_r_r_r
|
|
emit_iselgt :: emit_iselgt_r_r_r
|
|
inst_iseleq :: inst_iseleq_r_r_r
|
|
emit_iseleq :: emit_iseleq_r_r_r
|
|
inst_tweq :: inst_tweq_r_r
|
|
emit_tweq :: emit_tweq_r_r
|
|
inst_twne :: inst_twne_r_r
|
|
emit_twne :: emit_twne_r_r
|
|
inst_twgt :: inst_twgt_r_r
|
|
emit_twgt :: emit_twgt_r_r
|
|
inst_twlt :: inst_twlt_r_r
|
|
emit_twlt :: emit_twlt_r_r
|
|
inst_twgti :: inst_twgti_r_simm
|
|
emit_twgti :: emit_twgti_r_simm
|
|
inst_twlti :: inst_twlti_r_simm
|
|
emit_twlti :: emit_twlti_r_simm
|
|
inst_tweqi :: inst_tweqi_r_simm
|
|
emit_tweqi :: emit_tweqi_r_simm
|
|
inst_twnei :: inst_twnei_r_simm
|
|
emit_twnei :: emit_twnei_r_simm
|
|
inst_twui :: inst_twui_r_simm
|
|
emit_twui :: emit_twui_r_simm
|
|
inst_tdeq :: inst_tdeq_r_r
|
|
emit_tdeq :: emit_tdeq_r_r
|
|
inst_tdne :: inst_tdne_r_r
|
|
emit_tdne :: emit_tdne_r_r
|
|
inst_tdgt :: inst_tdgt_r_r
|
|
emit_tdgt :: emit_tdgt_r_r
|
|
inst_tdlt :: inst_tdlt_r_r
|
|
emit_tdlt :: emit_tdlt_r_r
|
|
inst_tdgti :: inst_tdgti_r_simm
|
|
emit_tdgti :: emit_tdgti_r_simm
|
|
inst_tdlti :: inst_tdlti_r_simm
|
|
emit_tdlti :: emit_tdlti_r_simm
|
|
inst_tdeqi :: inst_tdeqi_r_simm
|
|
emit_tdeqi :: emit_tdeqi_r_simm
|
|
inst_tdnei :: inst_tdnei_r_simm
|
|
emit_tdnei :: emit_tdnei_r_simm
|
|
inst_tdui :: inst_tdui_r_simm
|
|
emit_tdui :: emit_tdui_r_simm
|
|
inst_bcdadd_dot :: inst_bcdadd_dot_v_v_v_imm
|
|
emit_bcdadd_dot :: emit_bcdadd_dot_v_v_v_imm
|
|
inst_bcdsub_dot :: inst_bcdsub_dot_v_v_v_imm
|
|
emit_bcdsub_dot :: emit_bcdsub_dot_v_v_v_imm
|
|
inst_bcds_dot :: inst_bcds_dot_v_v_v_imm
|
|
emit_bcds_dot :: emit_bcds_dot_v_v_v_imm
|
|
inst_bcdus_dot :: inst_bcdus_dot_v_v_v
|
|
emit_bcdus_dot :: emit_bcdus_dot_v_v_v
|
|
inst_bcdsr_dot :: inst_bcdsr_dot_v_v_v_imm
|
|
emit_bcdsr_dot :: emit_bcdsr_dot_v_v_v_imm
|
|
inst_bcdcfn_dot :: inst_bcdcfn_dot_v_v_imm
|
|
emit_bcdcfn_dot :: emit_bcdcfn_dot_v_v_imm
|
|
inst_bcdctn_dot :: inst_bcdctn_dot_v_v
|
|
emit_bcdctn_dot :: emit_bcdctn_dot_v_v
|
|
inst_bcdcfz_dot :: inst_bcdcfz_dot_v_v_imm
|
|
emit_bcdcfz_dot :: emit_bcdcfz_dot_v_v_imm
|
|
inst_bcdctz_dot :: inst_bcdctz_dot_v_v_imm
|
|
emit_bcdctz_dot :: emit_bcdctz_dot_v_v_imm
|
|
inst_bcdcpsgn_dot :: inst_bcdcpsgn_dot_v_v_v
|
|
emit_bcdcpsgn_dot :: emit_bcdcpsgn_dot_v_v_v
|
|
inst_bcdtrunc_dot :: inst_bcdtrunc_dot_v_v_v_imm
|
|
emit_bcdtrunc_dot :: emit_bcdtrunc_dot_v_v_v_imm
|
|
inst_bcdutrunc_dot :: inst_bcdutrunc_dot_v_v_v
|
|
emit_bcdutrunc_dot :: emit_bcdutrunc_dot_v_v_v
|
|
inst_bcdcfsq_dot :: inst_bcdcfsq_dot_v_v_imm
|
|
emit_bcdcfsq_dot :: emit_bcdcfsq_dot_v_v_imm
|
|
inst_bcdctsq_dot :: inst_bcdctsq_dot_v_v
|
|
emit_bcdctsq_dot :: emit_bcdctsq_dot_v_v
|
|
inst_scv :: inst_scv_imm
|
|
emit_scv :: emit_scv_imm
|
|
inst_bdnztl :: inst_bdnztl_crb_rel
|
|
emit_bdnztl :: emit_bdnztl_crb_rel
|
|
inst_bdztl :: inst_bdztl_crb_rel
|
|
emit_bdztl :: emit_bdztl_crb_rel
|
|
inst_bdnzfl :: inst_bdnzfl_crb_rel
|
|
emit_bdnzfl :: emit_bdnzfl_crb_rel
|
|
inst_bdzfl :: inst_bdzfl_crb_rel
|
|
emit_bdzfl :: emit_bdzfl_crb_rel
|
|
inst_bdnztlr :: inst_bdnztlr_crb
|
|
emit_bdnztlr :: emit_bdnztlr_crb
|
|
inst_bdztlr :: inst_bdztlr_crb
|
|
emit_bdztlr :: emit_bdztlr_crb
|
|
inst_bdnzflr :: inst_bdnzflr_crb
|
|
emit_bdnzflr :: emit_bdnzflr_crb
|
|
inst_bdzflr :: inst_bdzflr_crb
|
|
emit_bdzflr :: emit_bdzflr_crb
|
|
inst_bdnztlrl :: inst_bdnztlrl_crb
|
|
emit_bdnztlrl :: emit_bdnztlrl_crb
|
|
inst_bdztlrl :: inst_bdztlrl_crb
|
|
emit_bdztlrl :: emit_bdztlrl_crb
|
|
inst_bdnzflrl :: inst_bdnzflrl_crb
|
|
emit_bdnzflrl :: emit_bdnzflrl_crb
|
|
inst_bdzflrl :: inst_bdzflrl_crb
|
|
emit_bdzflrl :: emit_bdzflrl_crb
|
|
inst_mtcr :: inst_mtcr_r
|
|
emit_mtcr :: emit_mtcr_r
|
|
inst_mfdscr :: inst_mfdscr_r
|
|
emit_mfdscr :: emit_mfdscr_r
|
|
inst_mtdscr :: inst_mtdscr_r
|
|
emit_mtdscr :: emit_mtdscr_r
|
|
inst_mfcfar :: inst_mfcfar_r
|
|
emit_mfcfar :: emit_mfcfar_r
|
|
inst_mtcfar :: inst_mtcfar_r
|
|
emit_mtcfar :: emit_mtcfar_r
|
|
inst_mfppr :: inst_mfppr_r
|
|
emit_mfppr :: emit_mfppr_r
|
|
inst_mtppr :: inst_mtppr_r
|
|
emit_mtppr :: emit_mtppr_r
|
|
inst_mfdec :: inst_mfdec_r
|
|
emit_mfdec :: emit_mfdec_r
|
|
inst_mtdec :: inst_mtdec_r
|
|
emit_mtdec :: emit_mtdec_r
|
|
inst_mfsrr0 :: inst_mfsrr0_r
|
|
emit_mfsrr0 :: emit_mfsrr0_r
|
|
inst_mtsrr0 :: inst_mtsrr0_r
|
|
emit_mtsrr0 :: emit_mtsrr0_r
|
|
inst_mfsrr1 :: inst_mfsrr1_r
|
|
emit_mfsrr1 :: emit_mfsrr1_r
|
|
inst_mtsrr1 :: inst_mtsrr1_r
|
|
emit_mtsrr1 :: emit_mtsrr1_r
|
|
inst_mfdar :: inst_mfdar_r
|
|
emit_mfdar :: emit_mfdar_r
|
|
inst_mtdar :: inst_mtdar_r
|
|
emit_mtdar :: emit_mtdar_r
|
|
inst_mfdsisr :: inst_mfdsisr_r
|
|
emit_mfdsisr :: emit_mfdsisr_r
|
|
inst_mtdsisr :: inst_mtdsisr_r
|
|
emit_mtdsisr :: emit_mtdsisr_r
|
|
inst_mfasr :: inst_mfasr_r
|
|
emit_mfasr :: emit_mfasr_r
|
|
inst_mtasr :: inst_mtasr_r
|
|
emit_mtasr :: emit_mtasr_r
|
|
inst_mfamr :: inst_mfamr_r
|
|
emit_mfamr :: emit_mfamr_r
|
|
inst_mtamr :: inst_mtamr_r
|
|
emit_mtamr :: emit_mtamr_r
|
|
inst_mftcr :: inst_mftcr_r
|
|
emit_mftcr :: emit_mftcr_r
|
|
inst_mttcr :: inst_mttcr_r
|
|
emit_mttcr :: emit_mttcr_r
|
|
inst_mfesr :: inst_mfesr_r
|
|
emit_mfesr :: emit_mfesr_r
|
|
inst_mtesr :: inst_mtesr_r
|
|
emit_mtesr :: emit_mtesr_r
|
|
inst_mfdccr :: inst_mfdccr_r
|
|
emit_mfdccr :: emit_mfdccr_r
|
|
inst_mtdccr :: inst_mtdccr_r
|
|
emit_mtdccr :: emit_mtdccr_r
|
|
inst_mtbr0 :: inst_mtbr0_r
|
|
emit_mtbr0 :: emit_mtbr0_r
|
|
inst_mtbr1 :: inst_mtbr1_r
|
|
emit_mtbr1 :: emit_mtbr1_r
|
|
inst_mttbl :: inst_mttbl_r
|
|
emit_mttbl :: emit_mttbl_r
|
|
inst_mttbu :: inst_mttbu_r
|
|
emit_mttbu :: emit_mttbu_r
|
|
inst_lwat :: inst_lwat_r_r_imm
|
|
emit_lwat :: emit_lwat_r_r_imm
|
|
inst_ldat :: inst_ldat_r_r_imm
|
|
emit_ldat :: emit_ldat_r_r_imm
|
|
inst_stwat :: inst_stwat_r_r_imm
|
|
emit_stwat :: emit_stwat_r_r_imm
|
|
inst_stdat :: inst_stdat_r_r_imm
|
|
emit_stdat :: emit_stdat_r_r_imm
|
|
inst_vextsd2q :: inst_vextsd2q_v_v
|
|
emit_vextsd2q :: emit_vextsd2q_v_v
|
|
inst_lxvprl :: inst_lxvprl_vs_r_r
|
|
emit_lxvprl :: emit_lxvprl_vs_r_r
|
|
inst_lxvprll :: inst_lxvprll_vs_r_r
|
|
emit_lxvprll :: emit_lxvprll_vs_r_r
|
|
inst_stxvprl :: inst_stxvprl_vs_r_r
|
|
emit_stxvprl :: emit_stxvprl_vs_r_r
|
|
inst_stxvprll :: inst_stxvprll_vs_r_r
|
|
emit_stxvprll :: emit_stxvprll_vs_r_r
|
|
inst_lxvrl :: inst_lxvrl_vs_r_r
|
|
emit_lxvrl :: emit_lxvrl_vs_r_r
|
|
inst_lxvrll :: inst_lxvrll_vs_r_r
|
|
emit_lxvrll :: emit_lxvrll_vs_r_r
|
|
inst_stxvrl :: inst_stxvrl_vs_r_r
|
|
emit_stxvrl :: emit_stxvrl_vs_r_r
|
|
inst_stxvrll :: inst_stxvrll_vs_r_r
|
|
emit_stxvrll :: emit_stxvrll_vs_r_r
|
|
inst_rfmci :: inst_rfmci_none
|
|
emit_rfmci :: emit_rfmci_none
|
|
inst_nop :: inst_nop_none
|
|
emit_nop :: emit_nop_none
|
|
inst_xnop :: inst_xnop_none
|
|
emit_xnop :: emit_xnop_none
|
|
inst_li :: inst_li_r_simm
|
|
emit_li :: emit_li_r_simm
|
|
inst_lis :: inst_lis_r_simm
|
|
emit_lis :: emit_lis_r_simm
|
|
inst_la :: inst_la_r_mem
|
|
emit_la :: emit_la_r_mem
|
|
inst_mr :: inst_mr_r_r
|
|
emit_mr :: emit_mr_r_r
|
|
inst_mr_dot :: inst_mr_dot_r_r
|
|
emit_mr_dot :: emit_mr_dot_r_r
|
|
inst_not :: inst_not_r_r
|
|
emit_not :: emit_not_r_r
|
|
inst_not_dot :: inst_not_dot_r_r
|
|
emit_not_dot :: emit_not_dot_r_r
|
|
inst_blr :: inst_blr_none
|
|
emit_blr :: emit_blr_none
|
|
inst_blrl :: inst_blrl_none
|
|
emit_blrl :: emit_blrl_none
|
|
inst_bctr :: inst_bctr_none
|
|
emit_bctr :: emit_bctr_none
|
|
inst_bctrl :: inst_bctrl_none
|
|
emit_bctrl :: emit_bctrl_none
|
|
inst_beq :: inst_beq_rel
|
|
emit_beq :: emit_beq_rel
|
|
inst_bne :: inst_bne_rel
|
|
emit_bne :: emit_bne_rel
|
|
inst_blt :: inst_blt_rel
|
|
emit_blt :: emit_blt_rel
|
|
inst_ble :: inst_ble_rel
|
|
emit_ble :: emit_ble_rel
|
|
inst_bgt :: inst_bgt_rel
|
|
emit_bgt :: emit_bgt_rel
|
|
inst_bge :: inst_bge_rel
|
|
emit_bge :: emit_bge_rel
|
|
inst_bso :: inst_bso_rel
|
|
emit_bso :: emit_bso_rel
|
|
inst_bns :: inst_bns_rel
|
|
emit_bns :: emit_bns_rel
|
|
inst_beql :: inst_beql_rel
|
|
emit_beql :: emit_beql_rel
|
|
inst_bnel :: inst_bnel_rel
|
|
emit_bnel :: emit_bnel_rel
|
|
inst_bltl :: inst_bltl_rel
|
|
emit_bltl :: emit_bltl_rel
|
|
inst_blel :: inst_blel_rel
|
|
emit_blel :: emit_blel_rel
|
|
inst_bgtl :: inst_bgtl_rel
|
|
emit_bgtl :: emit_bgtl_rel
|
|
inst_bgel :: inst_bgel_rel
|
|
emit_bgel :: emit_bgel_rel
|
|
inst_bsol :: inst_bsol_rel
|
|
emit_bsol :: emit_bsol_rel
|
|
inst_bnsl :: inst_bnsl_rel
|
|
emit_bnsl :: emit_bnsl_rel
|
|
inst_beqlr :: inst_beqlr_none
|
|
emit_beqlr :: emit_beqlr_none
|
|
inst_bnelr :: inst_bnelr_none
|
|
emit_bnelr :: emit_bnelr_none
|
|
inst_bltlr :: inst_bltlr_none
|
|
emit_bltlr :: emit_bltlr_none
|
|
inst_blelr :: inst_blelr_none
|
|
emit_blelr :: emit_blelr_none
|
|
inst_bgtlr :: inst_bgtlr_none
|
|
emit_bgtlr :: emit_bgtlr_none
|
|
inst_bgelr :: inst_bgelr_none
|
|
emit_bgelr :: emit_bgelr_none
|
|
inst_bsolr :: inst_bsolr_none
|
|
emit_bsolr :: emit_bsolr_none
|
|
inst_bnslr :: inst_bnslr_none
|
|
emit_bnslr :: emit_bnslr_none
|
|
inst_beqctr :: inst_beqctr_none
|
|
emit_beqctr :: emit_beqctr_none
|
|
inst_bnectr :: inst_bnectr_none
|
|
emit_bnectr :: emit_bnectr_none
|
|
inst_bltctr :: inst_bltctr_none
|
|
emit_bltctr :: emit_bltctr_none
|
|
inst_blectr :: inst_blectr_none
|
|
emit_blectr :: emit_blectr_none
|
|
inst_bgtctr :: inst_bgtctr_none
|
|
emit_bgtctr :: emit_bgtctr_none
|
|
inst_bgectr :: inst_bgectr_none
|
|
emit_bgectr :: emit_bgectr_none
|
|
inst_bsoctr :: inst_bsoctr_none
|
|
emit_bsoctr :: emit_bsoctr_none
|
|
inst_bnsctr :: inst_bnsctr_none
|
|
emit_bnsctr :: emit_bnsctr_none
|
|
inst_bdz :: inst_bdz_rel
|
|
emit_bdz :: emit_bdz_rel
|
|
inst_bdnz :: inst_bdnz_rel
|
|
emit_bdnz :: emit_bdnz_rel
|
|
inst_bdzl :: inst_bdzl_rel
|
|
emit_bdzl :: emit_bdzl_rel
|
|
inst_bdnzl :: inst_bdnzl_rel
|
|
emit_bdnzl :: emit_bdnzl_rel
|
|
inst_bdzlr :: inst_bdzlr_none
|
|
emit_bdzlr :: emit_bdzlr_none
|
|
inst_bdnzlr :: inst_bdnzlr_none
|
|
emit_bdnzlr :: emit_bdnzlr_none
|
|
inst_bdzlrl :: inst_bdzlrl_none
|
|
emit_bdzlrl :: emit_bdzlrl_none
|
|
inst_bdnzlrl :: inst_bdnzlrl_none
|
|
emit_bdnzlrl :: emit_bdnzlrl_none
|
|
inst_bdzf :: inst_bdzf_crb_rel
|
|
emit_bdzf :: emit_bdzf_crb_rel
|
|
inst_bdzt :: inst_bdzt_crb_rel
|
|
emit_bdzt :: emit_bdzt_crb_rel
|
|
inst_bdnzf :: inst_bdnzf_crb_rel
|
|
emit_bdnzf :: emit_bdnzf_crb_rel
|
|
inst_bdnzt :: inst_bdnzt_crb_rel
|
|
emit_bdnzt :: emit_bdnzt_crb_rel
|
|
inst_trap :: inst_trap_none
|
|
emit_trap :: emit_trap_none
|
|
inst_mflr :: inst_mflr_r
|
|
emit_mflr :: emit_mflr_r
|
|
inst_mtlr :: inst_mtlr_r
|
|
emit_mtlr :: emit_mtlr_r
|
|
inst_mfctr :: inst_mfctr_r
|
|
emit_mfctr :: emit_mfctr_r
|
|
inst_mtctr :: inst_mtctr_r
|
|
emit_mtctr :: emit_mtctr_r
|
|
inst_mfxer :: inst_mfxer_r
|
|
emit_mfxer :: emit_mfxer_r
|
|
inst_mtxer :: inst_mtxer_r
|
|
emit_mtxer :: emit_mtxer_r
|
|
inst_slwi :: inst_slwi_r_r_imm
|
|
emit_slwi :: emit_slwi_r_r_imm
|
|
inst_srwi :: inst_srwi_r_r_imm
|
|
emit_srwi :: emit_srwi_r_r_imm
|
|
inst_sldi :: inst_sldi_r_r_imm
|
|
emit_sldi :: emit_sldi_r_r_imm
|
|
inst_srdi :: inst_srdi_r_r_imm
|
|
emit_srdi :: emit_srdi_r_r_imm
|
|
inst_clrrwi :: inst_clrrwi_r_r_imm
|
|
emit_clrrwi :: emit_clrrwi_r_r_imm
|
|
inst_clrlwi :: inst_clrlwi_r_r_imm
|
|
emit_clrlwi :: emit_clrlwi_r_r_imm
|
|
inst_clrrdi :: inst_clrrdi_r_r_imm
|
|
emit_clrrdi :: emit_clrrdi_r_r_imm
|
|
inst_clrldi :: inst_clrldi_r_r_imm
|
|
emit_clrldi :: emit_clrldi_r_r_imm
|
|
inst_extldi :: inst_extldi_r_r_imm_imm
|
|
emit_extldi :: emit_extldi_r_r_imm_imm
|
|
inst_extrdi :: inst_extrdi_r_r_imm_imm
|
|
emit_extrdi :: emit_extrdi_r_r_imm_imm
|
|
inst_extlwi :: inst_extlwi_r_r_imm_imm
|
|
emit_extlwi :: emit_extlwi_r_r_imm_imm
|
|
inst_extrwi :: inst_extrwi_r_r_imm_imm
|
|
emit_extrwi :: emit_extrwi_r_r_imm_imm
|
|
inst_inslwi :: inst_inslwi_r_r_imm_imm
|
|
emit_inslwi :: emit_inslwi_r_r_imm_imm
|
|
inst_insrwi :: inst_insrwi_r_r_imm_imm
|
|
emit_insrwi :: emit_insrwi_r_r_imm_imm
|
|
inst_rotlw :: inst_rotlw_r_r_r
|
|
emit_rotlw :: emit_rotlw_r_r_r
|
|
inst_rotlwi :: inst_rotlwi_r_r_imm
|
|
emit_rotlwi :: emit_rotlwi_r_r_imm
|
|
inst_rotrw :: inst_rotrw_r_r_r
|
|
emit_rotrw :: emit_rotrw_r_r_r
|
|
inst_rotld :: inst_rotld_r_r_r
|
|
emit_rotld :: emit_rotld_r_r_r
|
|
inst_rotldi :: inst_rotldi_r_r_imm
|
|
emit_rotldi :: emit_rotldi_r_r_imm
|
|
inst_rotrdi :: inst_rotrdi_r_r_imm
|
|
emit_rotrdi :: emit_rotrdi_r_r_imm
|
|
inst_sub :: inst_sub_r_r_r
|
|
emit_sub :: emit_sub_r_r_r
|
|
inst_sub_dot :: inst_sub_dot_r_r_r
|
|
emit_sub_dot :: emit_sub_dot_r_r_r
|
|
inst_sub_o :: inst_sub_o_r_r_r
|
|
emit_sub_o :: emit_sub_o_r_r_r
|
|
inst_sub_o_dot :: inst_sub_o_dot_r_r_r
|
|
emit_sub_o_dot :: emit_sub_o_dot_r_r_r
|
|
inst_subc :: inst_subc_r_r_r
|
|
emit_subc :: emit_subc_r_r_r
|
|
inst_subc_dot :: inst_subc_dot_r_r_r
|
|
emit_subc_dot :: emit_subc_dot_r_r_r
|
|
inst_subc_o :: inst_subc_o_r_r_r
|
|
emit_subc_o :: emit_subc_o_r_r_r
|
|
inst_subc_o_dot :: inst_subc_o_dot_r_r_r
|
|
emit_subc_o_dot :: emit_subc_o_dot_r_r_r
|
|
inst_cmpw :: inst_cmpw_crf_r_r
|
|
emit_cmpw :: emit_cmpw_crf_r_r
|
|
inst_cmplw :: inst_cmplw_crf_r_r
|
|
emit_cmplw :: emit_cmplw_crf_r_r
|
|
inst_cmpd :: inst_cmpd_crf_r_r
|
|
emit_cmpd :: emit_cmpd_crf_r_r
|
|
inst_cmpld :: inst_cmpld_crf_r_r
|
|
emit_cmpld :: emit_cmpld_crf_r_r
|
|
inst_cmpwi :: inst_cmpwi_crf_r_simm
|
|
emit_cmpwi :: emit_cmpwi_crf_r_simm
|
|
inst_cmplwi :: inst_cmplwi_crf_r_uimm
|
|
emit_cmplwi :: emit_cmplwi_crf_r_uimm
|
|
inst_cmpdi :: inst_cmpdi_crf_r_simm
|
|
emit_cmpdi :: emit_cmpdi_crf_r_simm
|
|
inst_cmpldi :: inst_cmpldi_crf_r_uimm
|
|
emit_cmpldi :: emit_cmpldi_crf_r_uimm
|
|
inst_evaddw :: inst_evaddw_r_r_r
|
|
emit_evaddw :: emit_evaddw_r_r_r
|
|
inst_evaddiw :: inst_evaddiw_r_r_imm
|
|
emit_evaddiw :: emit_evaddiw_r_r_imm
|
|
inst_evsubfw :: inst_evsubfw_r_r_r
|
|
emit_evsubfw :: emit_evsubfw_r_r_r
|
|
inst_evsubifw :: inst_evsubifw_r_r_imm
|
|
emit_evsubifw :: emit_evsubifw_r_r_imm
|
|
inst_evabs :: inst_evabs_r_r
|
|
emit_evabs :: emit_evabs_r_r
|
|
inst_evextsh :: inst_evextsh_r_r
|
|
emit_evextsh :: emit_evextsh_r_r
|
|
inst_evextsb :: inst_evextsb_r_r
|
|
emit_evextsb :: emit_evextsb_r_r
|
|
inst_evcntlzw :: inst_evcntlzw_r_r
|
|
emit_evcntlzw :: emit_evcntlzw_r_r
|
|
inst_evcntlsw :: inst_evcntlsw_r_r
|
|
emit_evcntlsw :: emit_evcntlsw_r_r
|
|
inst_evrlw :: inst_evrlw_r_r_r
|
|
emit_evrlw :: emit_evrlw_r_r_r
|
|
inst_evrlwi :: inst_evrlwi_r_r_imm
|
|
emit_evrlwi :: emit_evrlwi_r_r_imm
|
|
inst_evslw :: inst_evslw_r_r_r
|
|
emit_evslw :: emit_evslw_r_r_r
|
|
inst_evslwi :: inst_evslwi_r_r_imm
|
|
emit_evslwi :: emit_evslwi_r_r_imm
|
|
inst_evsplati :: inst_evsplati_r_imm
|
|
emit_evsplati :: emit_evsplati_r_imm
|
|
inst_evsplatfi :: inst_evsplatfi_r_imm
|
|
emit_evsplatfi :: emit_evsplatfi_r_imm
|
|
inst_evsrwu :: inst_evsrwu_r_r_r
|
|
emit_evsrwu :: emit_evsrwu_r_r_r
|
|
inst_evsrws :: inst_evsrws_r_r_r
|
|
emit_evsrws :: emit_evsrws_r_r_r
|
|
inst_evsrwiu :: inst_evsrwiu_r_r_imm
|
|
emit_evsrwiu :: emit_evsrwiu_r_r_imm
|
|
inst_evsrwis :: inst_evsrwis_r_r_imm
|
|
emit_evsrwis :: emit_evsrwis_r_r_imm
|
|
inst_evand :: inst_evand_r_r_r
|
|
emit_evand :: emit_evand_r_r_r
|
|
inst_evor :: inst_evor_r_r_r
|
|
emit_evor :: emit_evor_r_r_r
|
|
inst_evxor :: inst_evxor_r_r_r
|
|
emit_evxor :: emit_evxor_r_r_r
|
|
inst_evnand :: inst_evnand_r_r_r
|
|
emit_evnand :: emit_evnand_r_r_r
|
|
inst_evnor :: inst_evnor_r_r_r
|
|
emit_evnor :: emit_evnor_r_r_r
|
|
inst_evandc :: inst_evandc_r_r_r
|
|
emit_evandc :: emit_evandc_r_r_r
|
|
inst_evorc :: inst_evorc_r_r_r
|
|
emit_evorc :: emit_evorc_r_r_r
|
|
inst_eveqv :: inst_eveqv_r_r_r
|
|
emit_eveqv :: emit_eveqv_r_r_r
|
|
inst_evcmpgts :: inst_evcmpgts_crf_r_r
|
|
emit_evcmpgts :: emit_evcmpgts_crf_r_r
|
|
inst_evcmpgtu :: inst_evcmpgtu_crf_r_r
|
|
emit_evcmpgtu :: emit_evcmpgtu_crf_r_r
|
|
inst_evcmplts :: inst_evcmplts_crf_r_r
|
|
emit_evcmplts :: emit_evcmplts_crf_r_r
|
|
inst_evcmpltu :: inst_evcmpltu_crf_r_r
|
|
emit_evcmpltu :: emit_evcmpltu_crf_r_r
|
|
inst_evcmpeq :: inst_evcmpeq_crf_r_r
|
|
emit_evcmpeq :: emit_evcmpeq_crf_r_r
|
|
inst_evsel :: inst_evsel_r_r_r_crf
|
|
emit_evsel :: emit_evsel_r_r_r_crf
|
|
inst_evmergehi :: inst_evmergehi_r_r_r
|
|
emit_evmergehi :: emit_evmergehi_r_r_r
|
|
inst_evmergelo :: inst_evmergelo_r_r_r
|
|
emit_evmergelo :: emit_evmergelo_r_r_r
|
|
inst_evmergehilo :: inst_evmergehilo_r_r_r
|
|
emit_evmergehilo :: emit_evmergehilo_r_r_r
|
|
inst_evmergelohi :: inst_evmergelohi_r_r_r
|
|
emit_evmergelohi :: emit_evmergelohi_r_r_r
|
|
inst_evdivws :: inst_evdivws_r_r_r
|
|
emit_evdivws :: emit_evdivws_r_r_r
|
|
inst_evdivwu :: inst_evdivwu_r_r_r
|
|
emit_evdivwu :: emit_evdivwu_r_r_r
|
|
inst_evmra :: inst_evmra_r_r
|
|
emit_evmra :: emit_evmra_r_r
|
|
inst_evldd :: inst_evldd_r_mem
|
|
emit_evldd :: emit_evldd_r_mem
|
|
inst_evlddx :: inst_evlddx_r_r_r
|
|
emit_evlddx :: emit_evlddx_r_r_r
|
|
inst_evldw :: inst_evldw_r_mem
|
|
emit_evldw :: emit_evldw_r_mem
|
|
inst_evldwx :: inst_evldwx_r_r_r
|
|
emit_evldwx :: emit_evldwx_r_r_r
|
|
inst_evldh :: inst_evldh_r_mem
|
|
emit_evldh :: emit_evldh_r_mem
|
|
inst_evldhx :: inst_evldhx_r_r_r
|
|
emit_evldhx :: emit_evldhx_r_r_r
|
|
inst_evstdd :: inst_evstdd_r_mem
|
|
emit_evstdd :: emit_evstdd_r_mem
|
|
inst_evstddx :: inst_evstddx_r_r_r
|
|
emit_evstddx :: emit_evstddx_r_r_r
|
|
inst_evstdw :: inst_evstdw_r_mem
|
|
emit_evstdw :: emit_evstdw_r_mem
|
|
inst_evstdwx :: inst_evstdwx_r_r_r
|
|
emit_evstdwx :: emit_evstdwx_r_r_r
|
|
inst_evstdh :: inst_evstdh_r_mem
|
|
emit_evstdh :: emit_evstdh_r_mem
|
|
inst_evstdhx :: inst_evstdhx_r_r_r
|
|
emit_evstdhx :: emit_evstdhx_r_r_r
|
|
inst_evlwwsplat :: inst_evlwwsplat_r_mem
|
|
emit_evlwwsplat :: emit_evlwwsplat_r_mem
|
|
inst_evlwhsplat :: inst_evlwhsplat_r_mem
|
|
emit_evlwhsplat :: emit_evlwhsplat_r_mem
|
|
inst_evlhhesplat :: inst_evlhhesplat_r_mem
|
|
emit_evlhhesplat :: emit_evlhhesplat_r_mem
|
|
inst_evlhhossplat :: inst_evlhhossplat_r_mem
|
|
emit_evlhhossplat :: emit_evlhhossplat_r_mem
|
|
inst_evlhhousplat :: inst_evlhhousplat_r_mem
|
|
emit_evlhhousplat :: emit_evlhhousplat_r_mem
|
|
inst_evlwhe :: inst_evlwhe_r_mem
|
|
emit_evlwhe :: emit_evlwhe_r_mem
|
|
inst_evlwhou :: inst_evlwhou_r_mem
|
|
emit_evlwhou :: emit_evlwhou_r_mem
|
|
inst_evlwhos :: inst_evlwhos_r_mem
|
|
emit_evlwhos :: emit_evlwhos_r_mem
|
|
inst_evlwhex :: inst_evlwhex_r_r_r
|
|
emit_evlwhex :: emit_evlwhex_r_r_r
|
|
inst_evstwwe :: inst_evstwwe_r_mem
|
|
emit_evstwwe :: emit_evstwwe_r_mem
|
|
inst_evstwwo :: inst_evstwwo_r_mem
|
|
emit_evstwwo :: emit_evstwwo_r_mem
|
|
inst_evstwhe :: inst_evstwhe_r_mem
|
|
emit_evstwhe :: emit_evstwhe_r_mem
|
|
inst_evstwho :: inst_evstwho_r_mem
|
|
emit_evstwho :: emit_evstwho_r_mem
|
|
inst_evstwhex :: inst_evstwhex_r_r_r
|
|
emit_evstwhex :: emit_evstwhex_r_r_r
|
|
inst_evfsadd :: inst_evfsadd_r_r_r
|
|
emit_evfsadd :: emit_evfsadd_r_r_r
|
|
inst_evfssub :: inst_evfssub_r_r_r
|
|
emit_evfssub :: emit_evfssub_r_r_r
|
|
inst_evfsabs :: inst_evfsabs_r_r
|
|
emit_evfsabs :: emit_evfsabs_r_r
|
|
inst_evfsnabs :: inst_evfsnabs_r_r
|
|
emit_evfsnabs :: emit_evfsnabs_r_r
|
|
inst_evfsneg :: inst_evfsneg_r_r
|
|
emit_evfsneg :: emit_evfsneg_r_r
|
|
inst_evfsmul :: inst_evfsmul_r_r_r
|
|
emit_evfsmul :: emit_evfsmul_r_r_r
|
|
inst_evfsdiv :: inst_evfsdiv_r_r_r
|
|
emit_evfsdiv :: emit_evfsdiv_r_r_r
|
|
inst_evfscmpgt :: inst_evfscmpgt_crf_r_r
|
|
emit_evfscmpgt :: emit_evfscmpgt_crf_r_r
|
|
inst_evfscmplt :: inst_evfscmplt_crf_r_r
|
|
emit_evfscmplt :: emit_evfscmplt_crf_r_r
|
|
inst_evfscmpeq :: inst_evfscmpeq_crf_r_r
|
|
emit_evfscmpeq :: emit_evfscmpeq_crf_r_r
|
|
inst_evfststgt :: inst_evfststgt_crf_r_r
|
|
emit_evfststgt :: emit_evfststgt_crf_r_r
|
|
inst_evfststlt :: inst_evfststlt_crf_r_r
|
|
emit_evfststlt :: emit_evfststlt_crf_r_r
|
|
inst_evfststeq :: inst_evfststeq_crf_r_r
|
|
emit_evfststeq :: emit_evfststeq_crf_r_r
|
|
inst_evfscfui :: inst_evfscfui_r_r
|
|
emit_evfscfui :: emit_evfscfui_r_r
|
|
inst_evfscfsi :: inst_evfscfsi_r_r
|
|
emit_evfscfsi :: emit_evfscfsi_r_r
|
|
inst_evfscfuf :: inst_evfscfuf_r_r
|
|
emit_evfscfuf :: emit_evfscfuf_r_r
|
|
inst_evfscfsf :: inst_evfscfsf_r_r
|
|
emit_evfscfsf :: emit_evfscfsf_r_r
|
|
inst_evfsctui :: inst_evfsctui_r_r
|
|
emit_evfsctui :: emit_evfsctui_r_r
|
|
inst_evfsctsi :: inst_evfsctsi_r_r
|
|
emit_evfsctsi :: emit_evfsctsi_r_r
|
|
inst_evfsctuf :: inst_evfsctuf_r_r
|
|
emit_evfsctuf :: emit_evfsctuf_r_r
|
|
inst_evfsctsf :: inst_evfsctsf_r_r
|
|
emit_evfsctsf :: emit_evfsctsf_r_r
|
|
inst_evfsctuiz :: inst_evfsctuiz_r_r
|
|
emit_evfsctuiz :: emit_evfsctuiz_r_r
|
|
inst_evfsctsiz :: inst_evfsctsiz_r_r
|
|
emit_evfsctsiz :: emit_evfsctsiz_r_r
|
|
inst_efsadd :: inst_efsadd_r_r_r
|
|
emit_efsadd :: emit_efsadd_r_r_r
|
|
inst_efssub :: inst_efssub_r_r_r
|
|
emit_efssub :: emit_efssub_r_r_r
|
|
inst_efsabs :: inst_efsabs_r_r
|
|
emit_efsabs :: emit_efsabs_r_r
|
|
inst_efsnabs :: inst_efsnabs_r_r
|
|
emit_efsnabs :: emit_efsnabs_r_r
|
|
inst_efsneg :: inst_efsneg_r_r
|
|
emit_efsneg :: emit_efsneg_r_r
|
|
inst_efsmul :: inst_efsmul_r_r_r
|
|
emit_efsmul :: emit_efsmul_r_r_r
|
|
inst_efsdiv :: inst_efsdiv_r_r_r
|
|
emit_efsdiv :: emit_efsdiv_r_r_r
|
|
inst_efscmpgt :: inst_efscmpgt_crf_r_r
|
|
emit_efscmpgt :: emit_efscmpgt_crf_r_r
|
|
inst_efscmplt :: inst_efscmplt_crf_r_r
|
|
emit_efscmplt :: emit_efscmplt_crf_r_r
|
|
inst_efscmpeq :: inst_efscmpeq_crf_r_r
|
|
emit_efscmpeq :: emit_efscmpeq_crf_r_r
|
|
inst_efststgt :: inst_efststgt_crf_r_r
|
|
emit_efststgt :: emit_efststgt_crf_r_r
|
|
inst_efststlt :: inst_efststlt_crf_r_r
|
|
emit_efststlt :: emit_efststlt_crf_r_r
|
|
inst_efststeq :: inst_efststeq_crf_r_r
|
|
emit_efststeq :: emit_efststeq_crf_r_r
|
|
inst_efscfui :: inst_efscfui_r_r
|
|
emit_efscfui :: emit_efscfui_r_r
|
|
inst_efscfsi :: inst_efscfsi_r_r
|
|
emit_efscfsi :: emit_efscfsi_r_r
|
|
inst_efscfuf :: inst_efscfuf_r_r
|
|
emit_efscfuf :: emit_efscfuf_r_r
|
|
inst_efscfsf :: inst_efscfsf_r_r
|
|
emit_efscfsf :: emit_efscfsf_r_r
|
|
inst_efsctui :: inst_efsctui_r_r
|
|
emit_efsctui :: emit_efsctui_r_r
|
|
inst_efsctsi :: inst_efsctsi_r_r
|
|
emit_efsctsi :: emit_efsctsi_r_r
|
|
inst_efsctuf :: inst_efsctuf_r_r
|
|
emit_efsctuf :: emit_efsctuf_r_r
|
|
inst_efsctsf :: inst_efsctsf_r_r
|
|
emit_efsctsf :: emit_efsctsf_r_r
|
|
inst_efsctuiz :: inst_efsctuiz_r_r
|
|
emit_efsctuiz :: emit_efsctuiz_r_r
|
|
inst_efsctsiz :: inst_efsctsiz_r_r
|
|
emit_efsctsiz :: emit_efsctsiz_r_r
|
|
inst_efscfd :: inst_efscfd_r_r
|
|
emit_efscfd :: emit_efscfd_r_r
|
|
inst_efdadd :: inst_efdadd_r_r_r
|
|
emit_efdadd :: emit_efdadd_r_r_r
|
|
inst_efdsub :: inst_efdsub_r_r_r
|
|
emit_efdsub :: emit_efdsub_r_r_r
|
|
inst_efdabs :: inst_efdabs_r_r
|
|
emit_efdabs :: emit_efdabs_r_r
|
|
inst_efdnabs :: inst_efdnabs_r_r
|
|
emit_efdnabs :: emit_efdnabs_r_r
|
|
inst_efdneg :: inst_efdneg_r_r
|
|
emit_efdneg :: emit_efdneg_r_r
|
|
inst_efdmul :: inst_efdmul_r_r_r
|
|
emit_efdmul :: emit_efdmul_r_r_r
|
|
inst_efddiv :: inst_efddiv_r_r_r
|
|
emit_efddiv :: emit_efddiv_r_r_r
|
|
inst_efdcmpgt :: inst_efdcmpgt_crf_r_r
|
|
emit_efdcmpgt :: emit_efdcmpgt_crf_r_r
|
|
inst_efdcmplt :: inst_efdcmplt_crf_r_r
|
|
emit_efdcmplt :: emit_efdcmplt_crf_r_r
|
|
inst_efdcmpeq :: inst_efdcmpeq_crf_r_r
|
|
emit_efdcmpeq :: emit_efdcmpeq_crf_r_r
|
|
inst_efdtstgt :: inst_efdtstgt_crf_r_r
|
|
emit_efdtstgt :: emit_efdtstgt_crf_r_r
|
|
inst_efdtstlt :: inst_efdtstlt_crf_r_r
|
|
emit_efdtstlt :: emit_efdtstlt_crf_r_r
|
|
inst_efdtsteq :: inst_efdtsteq_crf_r_r
|
|
emit_efdtsteq :: emit_efdtsteq_crf_r_r
|
|
inst_efdcfui :: inst_efdcfui_r_r
|
|
emit_efdcfui :: emit_efdcfui_r_r
|
|
inst_efdcfsi :: inst_efdcfsi_r_r
|
|
emit_efdcfsi :: emit_efdcfsi_r_r
|
|
inst_efdcfuf :: inst_efdcfuf_r_r
|
|
emit_efdcfuf :: emit_efdcfuf_r_r
|
|
inst_efdcfsf :: inst_efdcfsf_r_r
|
|
emit_efdcfsf :: emit_efdcfsf_r_r
|
|
inst_efdctui :: inst_efdctui_r_r
|
|
emit_efdctui :: emit_efdctui_r_r
|
|
inst_efdctsi :: inst_efdctsi_r_r
|
|
emit_efdctsi :: emit_efdctsi_r_r
|
|
inst_efdctuf :: inst_efdctuf_r_r
|
|
emit_efdctuf :: emit_efdctuf_r_r
|
|
inst_efdctsf :: inst_efdctsf_r_r
|
|
emit_efdctsf :: emit_efdctsf_r_r
|
|
inst_efdctuiz :: inst_efdctuiz_r_r
|
|
emit_efdctuiz :: emit_efdctuiz_r_r
|
|
inst_efdctsiz :: inst_efdctsiz_r_r
|
|
emit_efdctsiz :: emit_efdctsiz_r_r
|
|
inst_efdcfs :: inst_efdcfs_r_r
|
|
emit_efdcfs :: emit_efdcfs_r_r
|
|
inst_efdcfsid :: inst_efdcfsid_r_r
|
|
emit_efdcfsid :: emit_efdcfsid_r_r
|
|
inst_efdcfuid :: inst_efdcfuid_r_r
|
|
emit_efdcfuid :: emit_efdcfuid_r_r
|
|
inst_efdctsidz :: inst_efdctsidz_r_r
|
|
emit_efdctsidz :: emit_efdctsidz_r_r
|
|
inst_efdctuidz :: inst_efdctuidz_r_r
|
|
emit_efdctuidz :: emit_efdctuidz_r_r
|
|
inst_evmhossf :: inst_evmhossf_r_r_r
|
|
emit_evmhossf :: emit_evmhossf_r_r_r
|
|
inst_evmhossfa :: inst_evmhossfa_r_r_r
|
|
emit_evmhossfa :: emit_evmhossfa_r_r_r
|
|
inst_evmhossfaaw :: inst_evmhossfaaw_r_r_r
|
|
emit_evmhossfaaw :: emit_evmhossfaaw_r_r_r
|
|
inst_evmhossfanw :: inst_evmhossfanw_r_r_r
|
|
emit_evmhossfanw :: emit_evmhossfanw_r_r_r
|
|
inst_evmhossiaaw :: inst_evmhossiaaw_r_r_r
|
|
emit_evmhossiaaw :: emit_evmhossiaaw_r_r_r
|
|
inst_evmhossianw :: inst_evmhossianw_r_r_r
|
|
emit_evmhossianw :: emit_evmhossianw_r_r_r
|
|
inst_evmhosmf :: inst_evmhosmf_r_r_r
|
|
emit_evmhosmf :: emit_evmhosmf_r_r_r
|
|
inst_evmhosmfa :: inst_evmhosmfa_r_r_r
|
|
emit_evmhosmfa :: emit_evmhosmfa_r_r_r
|
|
inst_evmhosmfaaw :: inst_evmhosmfaaw_r_r_r
|
|
emit_evmhosmfaaw :: emit_evmhosmfaaw_r_r_r
|
|
inst_evmhosmfanw :: inst_evmhosmfanw_r_r_r
|
|
emit_evmhosmfanw :: emit_evmhosmfanw_r_r_r
|
|
inst_evmhosmi :: inst_evmhosmi_r_r_r
|
|
emit_evmhosmi :: emit_evmhosmi_r_r_r
|
|
inst_evmhosmia :: inst_evmhosmia_r_r_r
|
|
emit_evmhosmia :: emit_evmhosmia_r_r_r
|
|
inst_evmhosmiaaw :: inst_evmhosmiaaw_r_r_r
|
|
emit_evmhosmiaaw :: emit_evmhosmiaaw_r_r_r
|
|
inst_evmhosmianw :: inst_evmhosmianw_r_r_r
|
|
emit_evmhosmianw :: emit_evmhosmianw_r_r_r
|
|
inst_evmhesmf :: inst_evmhesmf_r_r_r
|
|
emit_evmhesmf :: emit_evmhesmf_r_r_r
|
|
inst_evmhesmfa :: inst_evmhesmfa_r_r_r
|
|
emit_evmhesmfa :: emit_evmhesmfa_r_r_r
|
|
inst_evmhesmfaaw :: inst_evmhesmfaaw_r_r_r
|
|
emit_evmhesmfaaw :: emit_evmhesmfaaw_r_r_r
|
|
inst_evmhesmfanw :: inst_evmhesmfanw_r_r_r
|
|
emit_evmhesmfanw :: emit_evmhesmfanw_r_r_r
|
|
inst_evmhesmi :: inst_evmhesmi_r_r_r
|
|
emit_evmhesmi :: emit_evmhesmi_r_r_r
|
|
inst_evmhesmia :: inst_evmhesmia_r_r_r
|
|
emit_evmhesmia :: emit_evmhesmia_r_r_r
|
|
inst_evmhesmiaaw :: inst_evmhesmiaaw_r_r_r
|
|
emit_evmhesmiaaw :: emit_evmhesmiaaw_r_r_r
|
|
inst_evmhesmianw :: inst_evmhesmianw_r_r_r
|
|
emit_evmhesmianw :: emit_evmhesmianw_r_r_r
|
|
inst_evmhessf :: inst_evmhessf_r_r_r
|
|
emit_evmhessf :: emit_evmhessf_r_r_r
|
|
inst_evmhessfa :: inst_evmhessfa_r_r_r
|
|
emit_evmhessfa :: emit_evmhessfa_r_r_r
|
|
inst_evmhessfaaw :: inst_evmhessfaaw_r_r_r
|
|
emit_evmhessfaaw :: emit_evmhessfaaw_r_r_r
|
|
inst_evmhessfanw :: inst_evmhessfanw_r_r_r
|
|
emit_evmhessfanw :: emit_evmhessfanw_r_r_r
|
|
inst_evmhessiaaw :: inst_evmhessiaaw_r_r_r
|
|
emit_evmhessiaaw :: emit_evmhessiaaw_r_r_r
|
|
inst_evmhessianw :: inst_evmhessianw_r_r_r
|
|
emit_evmhessianw :: emit_evmhessianw_r_r_r
|
|
inst_evmheumi :: inst_evmheumi_r_r_r
|
|
emit_evmheumi :: emit_evmheumi_r_r_r
|
|
inst_evmheumia :: inst_evmheumia_r_r_r
|
|
emit_evmheumia :: emit_evmheumia_r_r_r
|
|
inst_evmheumiaaw :: inst_evmheumiaaw_r_r_r
|
|
emit_evmheumiaaw :: emit_evmheumiaaw_r_r_r
|
|
inst_evmheumianw :: inst_evmheumianw_r_r_r
|
|
emit_evmheumianw :: emit_evmheumianw_r_r_r
|
|
inst_evmheusiaaw :: inst_evmheusiaaw_r_r_r
|
|
emit_evmheusiaaw :: emit_evmheusiaaw_r_r_r
|
|
inst_evmheusianw :: inst_evmheusianw_r_r_r
|
|
emit_evmheusianw :: emit_evmheusianw_r_r_r
|
|
inst_evmhoumi :: inst_evmhoumi_r_r_r
|
|
emit_evmhoumi :: emit_evmhoumi_r_r_r
|
|
inst_evmhoumia :: inst_evmhoumia_r_r_r
|
|
emit_evmhoumia :: emit_evmhoumia_r_r_r
|
|
inst_evmhoumiaaw :: inst_evmhoumiaaw_r_r_r
|
|
emit_evmhoumiaaw :: emit_evmhoumiaaw_r_r_r
|
|
inst_evmhoumianw :: inst_evmhoumianw_r_r_r
|
|
emit_evmhoumianw :: emit_evmhoumianw_r_r_r
|
|
inst_evmhousiaaw :: inst_evmhousiaaw_r_r_r
|
|
emit_evmhousiaaw :: emit_evmhousiaaw_r_r_r
|
|
inst_evmhousianw :: inst_evmhousianw_r_r_r
|
|
emit_evmhousianw :: emit_evmhousianw_r_r_r
|
|
inst_evmhogsmfaa :: inst_evmhogsmfaa_r_r_r
|
|
emit_evmhogsmfaa :: emit_evmhogsmfaa_r_r_r
|
|
inst_evmhogsmfan :: inst_evmhogsmfan_r_r_r
|
|
emit_evmhogsmfan :: emit_evmhogsmfan_r_r_r
|
|
inst_evmhogsmiaa :: inst_evmhogsmiaa_r_r_r
|
|
emit_evmhogsmiaa :: emit_evmhogsmiaa_r_r_r
|
|
inst_evmhogsmian :: inst_evmhogsmian_r_r_r
|
|
emit_evmhogsmian :: emit_evmhogsmian_r_r_r
|
|
inst_evmhogumiaa :: inst_evmhogumiaa_r_r_r
|
|
emit_evmhogumiaa :: emit_evmhogumiaa_r_r_r
|
|
inst_evmhogumian :: inst_evmhogumian_r_r_r
|
|
emit_evmhogumian :: emit_evmhogumian_r_r_r
|
|
inst_evmhegsmfaa :: inst_evmhegsmfaa_r_r_r
|
|
emit_evmhegsmfaa :: emit_evmhegsmfaa_r_r_r
|
|
inst_evmhegsmfan :: inst_evmhegsmfan_r_r_r
|
|
emit_evmhegsmfan :: emit_evmhegsmfan_r_r_r
|
|
inst_evmhegsmiaa :: inst_evmhegsmiaa_r_r_r
|
|
emit_evmhegsmiaa :: emit_evmhegsmiaa_r_r_r
|
|
inst_evmhegsmian :: inst_evmhegsmian_r_r_r
|
|
emit_evmhegsmian :: emit_evmhegsmian_r_r_r
|
|
inst_evmhegumiaa :: inst_evmhegumiaa_r_r_r
|
|
emit_evmhegumiaa :: emit_evmhegumiaa_r_r_r
|
|
inst_evmhegumian :: inst_evmhegumian_r_r_r
|
|
emit_evmhegumian :: emit_evmhegumian_r_r_r
|
|
inst_evmwhssf :: inst_evmwhssf_r_r_r
|
|
emit_evmwhssf :: emit_evmwhssf_r_r_r
|
|
inst_evmwhssfa :: inst_evmwhssfa_r_r_r
|
|
emit_evmwhssfa :: emit_evmwhssfa_r_r_r
|
|
inst_evmwlssiaaw :: inst_evmwlssiaaw_r_r_r
|
|
emit_evmwlssiaaw :: emit_evmwlssiaaw_r_r_r
|
|
inst_evmwlssianw :: inst_evmwlssianw_r_r_r
|
|
emit_evmwlssianw :: emit_evmwlssianw_r_r_r
|
|
inst_evmwhsmf :: inst_evmwhsmf_r_r_r
|
|
emit_evmwhsmf :: emit_evmwhsmf_r_r_r
|
|
inst_evmwhsmfa :: inst_evmwhsmfa_r_r_r
|
|
emit_evmwhsmfa :: emit_evmwhsmfa_r_r_r
|
|
inst_evmwhsmi :: inst_evmwhsmi_r_r_r
|
|
emit_evmwhsmi :: emit_evmwhsmi_r_r_r
|
|
inst_evmwhsmia :: inst_evmwhsmia_r_r_r
|
|
emit_evmwhsmia :: emit_evmwhsmia_r_r_r
|
|
inst_evmwhumi :: inst_evmwhumi_r_r_r
|
|
emit_evmwhumi :: emit_evmwhumi_r_r_r
|
|
inst_evmwhumia :: inst_evmwhumia_r_r_r
|
|
emit_evmwhumia :: emit_evmwhumia_r_r_r
|
|
inst_evmwlsmiaaw :: inst_evmwlsmiaaw_r_r_r
|
|
emit_evmwlsmiaaw :: emit_evmwlsmiaaw_r_r_r
|
|
inst_evmwlsmianw :: inst_evmwlsmianw_r_r_r
|
|
emit_evmwlsmianw :: emit_evmwlsmianw_r_r_r
|
|
inst_evmwlumi :: inst_evmwlumi_r_r_r
|
|
emit_evmwlumi :: emit_evmwlumi_r_r_r
|
|
inst_evmwlumia :: inst_evmwlumia_r_r_r
|
|
emit_evmwlumia :: emit_evmwlumia_r_r_r
|
|
inst_evmwlumiaaw :: inst_evmwlumiaaw_r_r_r
|
|
emit_evmwlumiaaw :: emit_evmwlumiaaw_r_r_r
|
|
inst_evmwlumianw :: inst_evmwlumianw_r_r_r
|
|
emit_evmwlumianw :: emit_evmwlumianw_r_r_r
|
|
inst_evmwlusiaaw :: inst_evmwlusiaaw_r_r_r
|
|
emit_evmwlusiaaw :: emit_evmwlusiaaw_r_r_r
|
|
inst_evmwlusianw :: inst_evmwlusianw_r_r_r
|
|
emit_evmwlusianw :: emit_evmwlusianw_r_r_r
|
|
inst_evmwsmf :: inst_evmwsmf_r_r_r
|
|
emit_evmwsmf :: emit_evmwsmf_r_r_r
|
|
inst_evmwsmfa :: inst_evmwsmfa_r_r_r
|
|
emit_evmwsmfa :: emit_evmwsmfa_r_r_r
|
|
inst_evmwsmfaa :: inst_evmwsmfaa_r_r_r
|
|
emit_evmwsmfaa :: emit_evmwsmfaa_r_r_r
|
|
inst_evmwsmfan :: inst_evmwsmfan_r_r_r
|
|
emit_evmwsmfan :: emit_evmwsmfan_r_r_r
|
|
inst_evmwsmi :: inst_evmwsmi_r_r_r
|
|
emit_evmwsmi :: emit_evmwsmi_r_r_r
|
|
inst_evmwsmia :: inst_evmwsmia_r_r_r
|
|
emit_evmwsmia :: emit_evmwsmia_r_r_r
|
|
inst_evmwsmiaa :: inst_evmwsmiaa_r_r_r
|
|
emit_evmwsmiaa :: emit_evmwsmiaa_r_r_r
|
|
inst_evmwsmian :: inst_evmwsmian_r_r_r
|
|
emit_evmwsmian :: emit_evmwsmian_r_r_r
|
|
inst_evmwssf :: inst_evmwssf_r_r_r
|
|
emit_evmwssf :: emit_evmwssf_r_r_r
|
|
inst_evmwssfa :: inst_evmwssfa_r_r_r
|
|
emit_evmwssfa :: emit_evmwssfa_r_r_r
|
|
inst_evmwssfaa :: inst_evmwssfaa_r_r_r
|
|
emit_evmwssfaa :: emit_evmwssfaa_r_r_r
|
|
inst_evmwssfan :: inst_evmwssfan_r_r_r
|
|
emit_evmwssfan :: emit_evmwssfan_r_r_r
|
|
inst_evmwumi :: inst_evmwumi_r_r_r
|
|
emit_evmwumi :: emit_evmwumi_r_r_r
|
|
inst_evmwumia :: inst_evmwumia_r_r_r
|
|
emit_evmwumia :: emit_evmwumia_r_r_r
|
|
inst_evmwumiaa :: inst_evmwumiaa_r_r_r
|
|
emit_evmwumiaa :: emit_evmwumiaa_r_r_r
|
|
inst_evmwumian :: inst_evmwumian_r_r_r
|
|
emit_evmwumian :: emit_evmwumian_r_r_r
|
|
inst_brinc :: inst_brinc_r_r_r
|
|
emit_brinc :: emit_brinc_r_r_r
|
|
inst_evlwhsplatx :: inst_evlwhsplatx_r_r_r
|
|
emit_evlwhsplatx :: emit_evlwhsplatx_r_r_r
|
|
inst_evlwwsplatx :: inst_evlwwsplatx_r_r_r
|
|
emit_evlwwsplatx :: emit_evlwwsplatx_r_r_r
|
|
inst_evlhhesplatx :: inst_evlhhesplatx_r_r_r
|
|
emit_evlhhesplatx :: emit_evlhhesplatx_r_r_r
|
|
inst_evlhhossplatx :: inst_evlhhossplatx_r_r_r
|
|
emit_evlhhossplatx :: emit_evlhhossplatx_r_r_r
|
|
inst_evlhhousplatx :: inst_evlhhousplatx_r_r_r
|
|
emit_evlhhousplatx :: emit_evlhhousplatx_r_r_r
|
|
inst_evlwhoux :: inst_evlwhoux_r_r_r
|
|
emit_evlwhoux :: emit_evlwhoux_r_r_r
|
|
inst_evlwhosx :: inst_evlwhosx_r_r_r
|
|
emit_evlwhosx :: emit_evlwhosx_r_r_r
|
|
inst_evstwwex :: inst_evstwwex_r_r_r
|
|
emit_evstwwex :: emit_evstwwex_r_r_r
|
|
inst_evstwwox :: inst_evstwwox_r_r_r
|
|
emit_evstwwox :: emit_evstwwox_r_r_r
|
|
inst_evstwhox :: inst_evstwhox_r_r_r
|
|
emit_evstwhox :: emit_evstwhox_r_r_r
|
|
inst_icbtls :: inst_icbtls_imm_r_r
|
|
emit_icbtls :: emit_icbtls_imm_r_r
|
|
inst_icblc :: inst_icblc_imm_r_r
|
|
emit_icblc :: emit_icblc_imm_r_r
|
|
inst_dcbst :: inst_dcbst_r_r
|
|
emit_dcbst :: emit_dcbst_r_r
|
|
inst_mbar :: inst_mbar_imm
|
|
emit_mbar :: emit_mbar_imm
|
|
inst_mtdcr :: inst_mtdcr_r_r
|
|
emit_mtdcr :: emit_mtdcr_r_r
|
|
inst_mfdcr :: inst_mfdcr_r_r
|
|
emit_mfdcr :: emit_mfdcr_r_r
|
|
inst_tlbilxva :: inst_tlbilxva_r_r
|
|
emit_tlbilxva :: emit_tlbilxva_r_r
|
|
inst_xscvsxdsp :: inst_xscvsxdsp_vs_vs
|
|
emit_xscvsxdsp :: emit_xscvsxdsp_vs_vs
|
|
inst_xscvuxdsp :: inst_xscvuxdsp_vs_vs
|
|
emit_xscvuxdsp :: emit_xscvuxdsp_vs_vs
|
|
inst_xxbrh :: inst_xxbrh_vs_vs
|
|
emit_xxbrh :: emit_xxbrh_vs_vs
|
|
inst_xxbrw :: inst_xxbrw_vs_vs
|
|
emit_xxbrw :: emit_xxbrw_vs_vs
|
|
inst_xxbrd :: inst_xxbrd_vs_vs
|
|
emit_xxbrd :: emit_xxbrd_vs_vs
|
|
inst_xxbrq :: inst_xxbrq_vs_vs
|
|
emit_xxbrq :: emit_xxbrq_vs_vs
|
|
inst_pdepd :: inst_pdepd_r_r_r
|
|
emit_pdepd :: emit_pdepd_r_r_r
|
|
inst_pextd :: inst_pextd_r_r_r
|
|
emit_pextd :: emit_pextd_r_r_r
|
|
inst_cntlzdm :: inst_cntlzdm_r_r_r
|
|
emit_cntlzdm :: emit_cntlzdm_r_r_r
|
|
inst_cnttzdm :: inst_cnttzdm_r_r_r
|
|
emit_cnttzdm :: emit_cnttzdm_r_r_r
|
|
inst_cfuged :: inst_cfuged_r_r_r
|
|
emit_cfuged :: emit_cfuged_r_r_r
|
|
inst_brh :: inst_brh_r_r
|
|
emit_brh :: emit_brh_r_r
|
|
inst_brw :: inst_brw_r_r
|
|
emit_brw :: emit_brw_r_r
|
|
inst_brd :: inst_brd_r_r
|
|
emit_brd :: emit_brd_r_r
|
|
inst_divweo :: inst_divweo_r_r_r
|
|
emit_divweo :: emit_divweo_r_r_r
|
|
inst_divweuo :: inst_divweuo_r_r_r
|
|
emit_divweuo :: emit_divweuo_r_r_r
|
|
inst_divdeo :: inst_divdeo_r_r_r
|
|
emit_divdeo :: emit_divdeo_r_r_r
|
|
inst_divdeuo :: inst_divdeuo_r_r_r
|
|
emit_divdeuo :: emit_divdeuo_r_r_r
|
|
inst_xvtlsbb :: inst_xvtlsbb_crf_vs
|
|
emit_xvtlsbb :: emit_xvtlsbb_crf_vs
|
|
inst_xvcvhpsp :: inst_xvcvhpsp_vs_vs
|
|
emit_xvcvhpsp :: emit_xvcvhpsp_vs_vs
|
|
inst_xvcvsphp :: inst_xvcvsphp_vs_vs
|
|
emit_xvcvsphp :: emit_xvcvsphp_vs_vs
|
|
inst_xxpermr :: inst_xxpermr_vs_vs_vs
|
|
emit_xxpermr :: emit_xxpermr_vs_vs_vs
|
|
inst_evfsmadd :: inst_evfsmadd_r_r_r
|
|
emit_evfsmadd :: emit_evfsmadd_r_r_r
|
|
inst_evfsmsub :: inst_evfsmsub_r_r_r
|
|
emit_evfsmsub :: emit_evfsmsub_r_r_r
|
|
inst_evfsnmadd :: inst_evfsnmadd_r_r_r
|
|
emit_evfsnmadd :: emit_evfsnmadd_r_r_r
|
|
inst_evfsnmsub :: inst_evfsnmsub_r_r_r
|
|
emit_evfsnmsub :: emit_evfsnmsub_r_r_r
|
|
inst_efsmadd :: inst_efsmadd_r_r_r
|
|
emit_efsmadd :: emit_efsmadd_r_r_r
|
|
inst_efsmsub :: inst_efsmsub_r_r_r
|
|
emit_efsmsub :: emit_efsmsub_r_r_r
|
|
inst_efsnmadd :: inst_efsnmadd_r_r_r
|
|
emit_efsnmadd :: emit_efsnmadd_r_r_r
|
|
inst_efsnmsub :: inst_efsnmsub_r_r_r
|
|
emit_efsnmsub :: emit_efsnmsub_r_r_r
|
|
inst_efdmadd :: inst_efdmadd_r_r_r
|
|
emit_efdmadd :: emit_efdmadd_r_r_r
|
|
inst_efdmsub :: inst_efdmsub_r_r_r
|
|
emit_efdmsub :: emit_efdmsub_r_r_r
|
|
inst_efdnmadd :: inst_efdnmadd_r_r_r
|
|
emit_efdnmadd :: emit_efdnmadd_r_r_r
|
|
inst_efdnmsub :: inst_efdnmsub_r_r_r
|
|
emit_efdnmsub :: emit_efdnmsub_r_r_r
|
|
inst_evfssqrt :: inst_evfssqrt_r_r
|
|
emit_evfssqrt :: emit_evfssqrt_r_r
|
|
inst_evfsmax :: inst_evfsmax_r_r_r
|
|
emit_evfsmax :: emit_evfsmax_r_r_r
|
|
inst_evfsmin :: inst_evfsmin_r_r_r
|
|
emit_evfsmin :: emit_evfsmin_r_r_r
|
|
inst_evfscfh :: inst_evfscfh_r_r
|
|
emit_evfscfh :: emit_evfscfh_r_r
|
|
inst_evfscth :: inst_evfscth_r_r
|
|
emit_evfscth :: emit_evfscth_r_r
|
|
inst_evfsaddsub :: inst_evfsaddsub_r_r_r
|
|
emit_evfsaddsub :: emit_evfsaddsub_r_r_r
|
|
inst_evfssubadd :: inst_evfssubadd_r_r_r
|
|
emit_evfssubadd :: emit_evfssubadd_r_r_r
|
|
inst_evfssum :: inst_evfssum_r_r_r
|
|
emit_evfssum :: emit_evfssum_r_r_r
|
|
inst_evfsdiff :: inst_evfsdiff_r_r_r
|
|
emit_evfsdiff :: emit_evfsdiff_r_r_r
|
|
inst_evfssumdiff :: inst_evfssumdiff_r_r_r
|
|
emit_evfssumdiff :: emit_evfssumdiff_r_r_r
|
|
inst_evfsdiffsum :: inst_evfsdiffsum_r_r_r
|
|
emit_evfsdiffsum :: emit_evfsdiffsum_r_r_r
|
|
inst_evfsaddx :: inst_evfsaddx_r_r_r
|
|
emit_evfsaddx :: emit_evfsaddx_r_r_r
|
|
inst_evfssubx :: inst_evfssubx_r_r_r
|
|
emit_evfssubx :: emit_evfssubx_r_r_r
|
|
inst_evfsaddsubx :: inst_evfsaddsubx_r_r_r
|
|
emit_evfsaddsubx :: emit_evfsaddsubx_r_r_r
|
|
inst_evfssubaddx :: inst_evfssubaddx_r_r_r
|
|
emit_evfssubaddx :: emit_evfssubaddx_r_r_r
|
|
inst_evfsmulx :: inst_evfsmulx_r_r_r
|
|
emit_evfsmulx :: emit_evfsmulx_r_r_r
|
|
inst_evfsmule :: inst_evfsmule_r_r_r
|
|
emit_evfsmule :: emit_evfsmule_r_r_r
|
|
inst_evfsmulo :: inst_evfsmulo_r_r_r
|
|
emit_evfsmulo :: emit_evfsmulo_r_r_r
|
|
inst_efssqrt :: inst_efssqrt_r_r
|
|
emit_efssqrt :: emit_efssqrt_r_r
|
|
inst_efsmax :: inst_efsmax_r_r_r
|
|
emit_efsmax :: emit_efsmax_r_r_r
|
|
inst_efsmin :: inst_efsmin_r_r_r
|
|
emit_efsmin :: emit_efsmin_r_r_r
|
|
inst_efscfh :: inst_efscfh_r_r
|
|
emit_efscfh :: emit_efscfh_r_r
|
|
inst_efscth :: inst_efscth_r_r
|
|
emit_efscth :: emit_efscth_r_r
|
|
inst_efdsqrt :: inst_efdsqrt_r_r
|
|
emit_efdsqrt :: emit_efdsqrt_r_r
|
|
inst_efdmax :: inst_efdmax_r_r_r
|
|
emit_efdmax :: emit_efdmax_r_r_r
|
|
inst_efdmin :: inst_efdmin_r_r_r
|
|
emit_efdmin :: emit_efdmin_r_r_r
|
|
inst_efdcfh :: inst_efdcfh_r_r
|
|
emit_efdcfh :: emit_efdcfh_r_r
|
|
inst_efdcth :: inst_efdcth_r_r
|
|
emit_efdcth :: emit_efdcth_r_r
|
|
inst_evsubw :: inst_evsubw_r_r_r
|
|
emit_evsubw :: emit_evsubw_r_r_r
|
|
inst_evsubiw :: inst_evsubiw_r_r_r
|
|
emit_evsubiw :: emit_evsubiw_r_r_r
|
|
inst_evneg :: inst_evneg_r_r_r
|
|
emit_evneg :: emit_evneg_r_r_r
|
|
inst_evrndw :: inst_evrndw_r_r_r
|
|
emit_evrndw :: emit_evrndw_r_r_r
|
|
inst_evmr :: inst_evmr_r_r_r
|
|
emit_evmr :: emit_evmr_r_r_r
|
|
inst_evnot :: inst_evnot_r_r_r
|
|
emit_evnot :: emit_evnot_r_r_r
|
|
inst_evsadd :: inst_evsadd_r_r_r
|
|
emit_evsadd :: emit_evsadd_r_r_r
|
|
inst_evssub :: inst_evssub_r_r_r
|
|
emit_evssub :: emit_evssub_r_r_r
|
|
inst_evsabs :: inst_evsabs_r_r_r
|
|
emit_evsabs :: emit_evsabs_r_r_r
|
|
inst_evsnabs :: inst_evsnabs_r_r_r
|
|
emit_evsnabs :: emit_evsnabs_r_r_r
|
|
inst_evsneg :: inst_evsneg_r_r_r
|
|
emit_evsneg :: emit_evsneg_r_r_r
|
|
inst_evsmul :: inst_evsmul_r_r_r
|
|
emit_evsmul :: emit_evsmul_r_r_r
|
|
inst_evsdiv :: inst_evsdiv_r_r_r
|
|
emit_evsdiv :: emit_evsdiv_r_r_r
|
|
inst_evscmpgt :: inst_evscmpgt_r_r_r
|
|
emit_evscmpgt :: emit_evscmpgt_r_r_r
|
|
inst_evsgmplt :: inst_evsgmplt_r_r_r
|
|
emit_evsgmplt :: emit_evsgmplt_r_r_r
|
|
inst_evsgmpeq :: inst_evsgmpeq_r_r_r
|
|
emit_evsgmpeq :: emit_evsgmpeq_r_r_r
|
|
inst_evscfui :: inst_evscfui_r_r_r
|
|
emit_evscfui :: emit_evscfui_r_r_r
|
|
inst_evscfsi :: inst_evscfsi_r_r_r
|
|
emit_evscfsi :: emit_evscfsi_r_r_r
|
|
inst_evscfuf :: inst_evscfuf_r_r_r
|
|
emit_evscfuf :: emit_evscfuf_r_r_r
|
|
inst_evscfsf :: inst_evscfsf_r_r_r
|
|
emit_evscfsf :: emit_evscfsf_r_r_r
|
|
inst_evsctui :: inst_evsctui_r_r_r
|
|
emit_evsctui :: emit_evsctui_r_r_r
|
|
inst_evsctsi :: inst_evsctsi_r_r_r
|
|
emit_evsctsi :: emit_evsctsi_r_r_r
|
|
inst_evsctuf :: inst_evsctuf_r_r_r
|
|
emit_evsctuf :: emit_evsctuf_r_r_r
|
|
inst_evsctsf :: inst_evsctsf_r_r_r
|
|
emit_evsctsf :: emit_evsctsf_r_r_r
|
|
inst_evsctuiz :: inst_evsctuiz_r_r_r
|
|
emit_evsctuiz :: emit_evsctuiz_r_r_r
|
|
inst_evsctsiz :: inst_evsctsiz_r_r_r
|
|
emit_evsctsiz :: emit_evsctsiz_r_r_r
|
|
inst_evststgt :: inst_evststgt_r_r_r
|
|
emit_evststgt :: emit_evststgt_r_r_r
|
|
inst_evststlt :: inst_evststlt_r_r_r
|
|
emit_evststlt :: emit_evststlt_r_r_r
|
|
inst_evststeq :: inst_evststeq_r_r_r
|
|
emit_evststeq :: emit_evststeq_r_r_r
|
|
inst_evmwlssf :: inst_evmwlssf_r_r_r
|
|
emit_evmwlssf :: emit_evmwlssf_r_r_r
|
|
inst_evmwlsmf :: inst_evmwlsmf_r_r_r
|
|
emit_evmwlsmf :: emit_evmwlsmf_r_r_r
|
|
inst_evmwlssfa :: inst_evmwlssfa_r_r_r
|
|
emit_evmwlssfa :: emit_evmwlssfa_r_r_r
|
|
inst_evmwlsmfa :: inst_evmwlsmfa_r_r_r
|
|
emit_evmwlsmfa :: emit_evmwlsmfa_r_r_r
|
|
inst_evaddusiaaw :: inst_evaddusiaaw_r_r_r
|
|
emit_evaddusiaaw :: emit_evaddusiaaw_r_r_r
|
|
inst_evaddssiaaw :: inst_evaddssiaaw_r_r_r
|
|
emit_evaddssiaaw :: emit_evaddssiaaw_r_r_r
|
|
inst_evsubfusiaaw :: inst_evsubfusiaaw_r_r_r
|
|
emit_evsubfusiaaw :: emit_evsubfusiaaw_r_r_r
|
|
inst_evsubfssiaaw :: inst_evsubfssiaaw_r_r_r
|
|
emit_evsubfssiaaw :: emit_evsubfssiaaw_r_r_r
|
|
inst_evaddumiaaw :: inst_evaddumiaaw_r_r_r
|
|
emit_evaddumiaaw :: emit_evaddumiaaw_r_r_r
|
|
inst_evaddsmiaaw :: inst_evaddsmiaaw_r_r_r
|
|
emit_evaddsmiaaw :: emit_evaddsmiaaw_r_r_r
|
|
inst_evsubfumiaaw :: inst_evsubfumiaaw_r_r_r
|
|
emit_evsubfumiaaw :: emit_evsubfumiaaw_r_r_r
|
|
inst_evsubfsmiaaw :: inst_evsubfsmiaaw_r_r_r
|
|
emit_evsubfsmiaaw :: emit_evsubfsmiaaw_r_r_r
|
|
inst_evmwlssfaaw :: inst_evmwlssfaaw_r_r_r
|
|
emit_evmwlssfaaw :: emit_evmwlssfaaw_r_r_r
|
|
inst_evmwhusiaa :: inst_evmwhusiaa_r_r_r
|
|
emit_evmwhusiaa :: emit_evmwhusiaa_r_r_r
|
|
inst_evmwhssmaa :: inst_evmwhssmaa_r_r_r
|
|
emit_evmwhssmaa :: emit_evmwhssmaa_r_r_r
|
|
inst_evmwhssfaa :: inst_evmwhssfaa_r_r_r
|
|
emit_evmwhssfaa :: emit_evmwhssfaa_r_r_r
|
|
inst_evmwlsmfaaw :: inst_evmwlsmfaaw_r_r_r
|
|
emit_evmwlsmfaaw :: emit_evmwlsmfaaw_r_r_r
|
|
inst_evmwhumiaa :: inst_evmwhumiaa_r_r_r
|
|
emit_evmwhumiaa :: emit_evmwhumiaa_r_r_r
|
|
inst_evmwhsmiaa :: inst_evmwhsmiaa_r_r_r
|
|
emit_evmwhsmiaa :: emit_evmwhsmiaa_r_r_r
|
|
inst_evmwhsmfaa :: inst_evmwhsmfaa_r_r_r
|
|
emit_evmwhsmfaa :: emit_evmwhsmfaa_r_r_r
|
|
inst_evmwhgumiaa :: inst_evmwhgumiaa_r_r_r
|
|
emit_evmwhgumiaa :: emit_evmwhgumiaa_r_r_r
|
|
inst_evmwhgsmiaa :: inst_evmwhgsmiaa_r_r_r
|
|
emit_evmwhgsmiaa :: emit_evmwhgsmiaa_r_r_r
|
|
inst_evmwhgssfaa :: inst_evmwhgssfaa_r_r_r
|
|
emit_evmwhgssfaa :: emit_evmwhgssfaa_r_r_r
|
|
inst_evmwhgsmfaa :: inst_evmwhgsmfaa_r_r_r
|
|
emit_evmwhgsmfaa :: emit_evmwhgsmfaa_r_r_r
|
|
inst_evmwlssfanw :: inst_evmwlssfanw_r_r_r
|
|
emit_evmwlssfanw :: emit_evmwlssfanw_r_r_r
|
|
inst_evmwhusian :: inst_evmwhusian_r_r_r
|
|
emit_evmwhusian :: emit_evmwhusian_r_r_r
|
|
inst_evmwhssian :: inst_evmwhssian_r_r_r
|
|
emit_evmwhssian :: emit_evmwhssian_r_r_r
|
|
inst_evmwhssfan :: inst_evmwhssfan_r_r_r
|
|
emit_evmwhssfan :: emit_evmwhssfan_r_r_r
|
|
inst_evmwlsmfanw :: inst_evmwlsmfanw_r_r_r
|
|
emit_evmwlsmfanw :: emit_evmwlsmfanw_r_r_r
|
|
inst_evmwhumian :: inst_evmwhumian_r_r_r
|
|
emit_evmwhumian :: emit_evmwhumian_r_r_r
|
|
inst_evmwhsmian :: inst_evmwhsmian_r_r_r
|
|
emit_evmwhsmian :: emit_evmwhsmian_r_r_r
|
|
inst_evmwhsmfan :: inst_evmwhsmfan_r_r_r
|
|
emit_evmwhsmfan :: emit_evmwhsmfan_r_r_r
|
|
inst_evmwhgumian :: inst_evmwhgumian_r_r_r
|
|
emit_evmwhgumian :: emit_evmwhgumian_r_r_r
|
|
inst_evmwhgsmian :: inst_evmwhgsmian_r_r_r
|
|
emit_evmwhgsmian :: emit_evmwhgsmian_r_r_r
|
|
inst_evmwhgssfan :: inst_evmwhgssfan_r_r_r
|
|
emit_evmwhgssfan :: emit_evmwhgssfan_r_r_r
|
|
inst_evmwhgsmfan :: inst_evmwhgsmfan_r_r_r
|
|
emit_evmwhgsmfan :: emit_evmwhgsmfan_r_r_r
|
|
inst_evdotpwcssi :: inst_evdotpwcssi_r_r_r
|
|
emit_evdotpwcssi :: emit_evdotpwcssi_r_r_r
|
|
inst_evdotpwcsmi :: inst_evdotpwcsmi_r_r_r
|
|
emit_evdotpwcsmi :: emit_evdotpwcsmi_r_r_r
|
|
inst_evdotpwcssfr :: inst_evdotpwcssfr_r_r_r
|
|
emit_evdotpwcssfr :: emit_evdotpwcssfr_r_r_r
|
|
inst_evdotpwcssf :: inst_evdotpwcssf_r_r_r
|
|
emit_evdotpwcssf :: emit_evdotpwcssf_r_r_r
|
|
inst_evdotpwgasmf :: inst_evdotpwgasmf_r_r_r
|
|
emit_evdotpwgasmf :: emit_evdotpwgasmf_r_r_r
|
|
inst_evdotpwxgasmf :: inst_evdotpwxgasmf_r_r_r
|
|
emit_evdotpwxgasmf :: emit_evdotpwxgasmf_r_r_r
|
|
inst_evdotpwgasmfr :: inst_evdotpwgasmfr_r_r_r
|
|
emit_evdotpwgasmfr :: emit_evdotpwgasmfr_r_r_r
|
|
inst_evdotpwxgasmfr :: inst_evdotpwxgasmfr_r_r_r
|
|
emit_evdotpwxgasmfr :: emit_evdotpwxgasmfr_r_r_r
|
|
inst_evdotpwgssmf :: inst_evdotpwgssmf_r_r_r
|
|
emit_evdotpwgssmf :: emit_evdotpwgssmf_r_r_r
|
|
inst_evdotpwxgssmf :: inst_evdotpwxgssmf_r_r_r
|
|
emit_evdotpwxgssmf :: emit_evdotpwxgssmf_r_r_r
|
|
inst_evdotpwgssmfr :: inst_evdotpwgssmfr_r_r_r
|
|
emit_evdotpwgssmfr :: emit_evdotpwgssmfr_r_r_r
|
|
inst_evdotpwxgssmfr :: inst_evdotpwxgssmfr_r_r_r
|
|
emit_evdotpwxgssmfr :: emit_evdotpwxgssmfr_r_r_r
|
|
inst_evdotpwcssiaaw3 :: inst_evdotpwcssiaaw3_r_r_r
|
|
emit_evdotpwcssiaaw3 :: emit_evdotpwcssiaaw3_r_r_r
|
|
inst_evdotpwcsmiaaw3 :: inst_evdotpwcsmiaaw3_r_r_r
|
|
emit_evdotpwcsmiaaw3 :: emit_evdotpwcsmiaaw3_r_r_r
|
|
inst_evdotpwcssfraaw3 :: inst_evdotpwcssfraaw3_r_r_r
|
|
emit_evdotpwcssfraaw3 :: emit_evdotpwcssfraaw3_r_r_r
|
|
inst_evdotpwcssfaaw3 :: inst_evdotpwcssfaaw3_r_r_r
|
|
emit_evdotpwcssfaaw3 :: emit_evdotpwcssfaaw3_r_r_r
|
|
inst_evdotpwgasmfaa3 :: inst_evdotpwgasmfaa3_r_r_r
|
|
emit_evdotpwgasmfaa3 :: emit_evdotpwgasmfaa3_r_r_r
|
|
inst_evdotpwxgasmfaa3 :: inst_evdotpwxgasmfaa3_r_r_r
|
|
emit_evdotpwxgasmfaa3 :: emit_evdotpwxgasmfaa3_r_r_r
|
|
inst_evdotpwgasmfraa3 :: inst_evdotpwgasmfraa3_r_r_r
|
|
emit_evdotpwgasmfraa3 :: emit_evdotpwgasmfraa3_r_r_r
|
|
inst_evdotpwxgasmfraa3 :: inst_evdotpwxgasmfraa3_r_r_r
|
|
emit_evdotpwxgasmfraa3 :: emit_evdotpwxgasmfraa3_r_r_r
|
|
inst_evdotpwgssmfaa3 :: inst_evdotpwgssmfaa3_r_r_r
|
|
emit_evdotpwgssmfaa3 :: emit_evdotpwgssmfaa3_r_r_r
|
|
inst_evdotpwxgssmfaa3 :: inst_evdotpwxgssmfaa3_r_r_r
|
|
emit_evdotpwxgssmfaa3 :: emit_evdotpwxgssmfaa3_r_r_r
|
|
inst_evdotpwgssmfraa3 :: inst_evdotpwgssmfraa3_r_r_r
|
|
emit_evdotpwgssmfraa3 :: emit_evdotpwgssmfraa3_r_r_r
|
|
inst_evdotpwxgssmfraa3 :: inst_evdotpwxgssmfraa3_r_r_r
|
|
emit_evdotpwxgssmfraa3 :: emit_evdotpwxgssmfraa3_r_r_r
|
|
inst_evdotpwcssia :: inst_evdotpwcssia_r_r_r
|
|
emit_evdotpwcssia :: emit_evdotpwcssia_r_r_r
|
|
inst_evdotpwcsmia :: inst_evdotpwcsmia_r_r_r
|
|
emit_evdotpwcsmia :: emit_evdotpwcsmia_r_r_r
|
|
inst_evdotpwcssfra :: inst_evdotpwcssfra_r_r_r
|
|
emit_evdotpwcssfra :: emit_evdotpwcssfra_r_r_r
|
|
inst_evdotpwcssfa :: inst_evdotpwcssfa_r_r_r
|
|
emit_evdotpwcssfa :: emit_evdotpwcssfa_r_r_r
|
|
inst_evdotpwgasmfa :: inst_evdotpwgasmfa_r_r_r
|
|
emit_evdotpwgasmfa :: emit_evdotpwgasmfa_r_r_r
|
|
inst_evdotpwxgasmfa :: inst_evdotpwxgasmfa_r_r_r
|
|
emit_evdotpwxgasmfa :: emit_evdotpwxgasmfa_r_r_r
|
|
inst_evdotpwgasmfra :: inst_evdotpwgasmfra_r_r_r
|
|
emit_evdotpwgasmfra :: emit_evdotpwgasmfra_r_r_r
|
|
inst_evdotpwxgasmfra :: inst_evdotpwxgasmfra_r_r_r
|
|
emit_evdotpwxgasmfra :: emit_evdotpwxgasmfra_r_r_r
|
|
inst_evdotpwgssmfa :: inst_evdotpwgssmfa_r_r_r
|
|
emit_evdotpwgssmfa :: emit_evdotpwgssmfa_r_r_r
|
|
inst_evdotpwxgssmfa :: inst_evdotpwxgssmfa_r_r_r
|
|
emit_evdotpwxgssmfa :: emit_evdotpwxgssmfa_r_r_r
|
|
inst_evdotpwgssmfra :: inst_evdotpwgssmfra_r_r_r
|
|
emit_evdotpwgssmfra :: emit_evdotpwgssmfra_r_r_r
|
|
inst_evdotpwxgssmfra :: inst_evdotpwxgssmfra_r_r_r
|
|
emit_evdotpwxgssmfra :: emit_evdotpwxgssmfra_r_r_r
|
|
inst_evdotpwcssiaaw :: inst_evdotpwcssiaaw_r_r_r
|
|
emit_evdotpwcssiaaw :: emit_evdotpwcssiaaw_r_r_r
|
|
inst_evdotpwcsmiaaw :: inst_evdotpwcsmiaaw_r_r_r
|
|
emit_evdotpwcsmiaaw :: emit_evdotpwcsmiaaw_r_r_r
|
|
inst_evdotpwcssfraaw :: inst_evdotpwcssfraaw_r_r_r
|
|
emit_evdotpwcssfraaw :: emit_evdotpwcssfraaw_r_r_r
|
|
inst_evdotpwcssfaaw :: inst_evdotpwcssfaaw_r_r_r
|
|
emit_evdotpwcssfaaw :: emit_evdotpwcssfaaw_r_r_r
|
|
inst_evdotpwgasmfaa :: inst_evdotpwgasmfaa_r_r_r
|
|
emit_evdotpwgasmfaa :: emit_evdotpwgasmfaa_r_r_r
|
|
inst_evdotpwxgasmfaa :: inst_evdotpwxgasmfaa_r_r_r
|
|
emit_evdotpwxgasmfaa :: emit_evdotpwxgasmfaa_r_r_r
|
|
inst_evdotpwgasmfraa :: inst_evdotpwgasmfraa_r_r_r
|
|
emit_evdotpwgasmfraa :: emit_evdotpwgasmfraa_r_r_r
|
|
inst_evdotpwxgasmfraa :: inst_evdotpwxgasmfraa_r_r_r
|
|
emit_evdotpwxgasmfraa :: emit_evdotpwxgasmfraa_r_r_r
|
|
inst_evdotpwgssmfaa :: inst_evdotpwgssmfaa_r_r_r
|
|
emit_evdotpwgssmfaa :: emit_evdotpwgssmfaa_r_r_r
|
|
inst_evdotpwxgssmfaa :: inst_evdotpwxgssmfaa_r_r_r
|
|
emit_evdotpwxgssmfaa :: emit_evdotpwxgssmfaa_r_r_r
|
|
inst_evdotpwgssmfraa :: inst_evdotpwgssmfraa_r_r_r
|
|
emit_evdotpwgssmfraa :: emit_evdotpwgssmfraa_r_r_r
|
|
inst_evdotpwxgssmfraa :: inst_evdotpwxgssmfraa_r_r_r
|
|
emit_evdotpwxgssmfraa :: emit_evdotpwxgssmfraa_r_r_r
|
|
inst_evdotphihcssi :: inst_evdotphihcssi_r_r_r
|
|
emit_evdotphihcssi :: emit_evdotphihcssi_r_r_r
|
|
inst_evdotplohcssi :: inst_evdotplohcssi_r_r_r
|
|
emit_evdotplohcssi :: emit_evdotplohcssi_r_r_r
|
|
inst_evdotphihcssf :: inst_evdotphihcssf_r_r_r
|
|
emit_evdotphihcssf :: emit_evdotphihcssf_r_r_r
|
|
inst_evdotplohcssf :: inst_evdotplohcssf_r_r_r
|
|
emit_evdotplohcssf :: emit_evdotplohcssf_r_r_r
|
|
inst_evdotphihcsmi :: inst_evdotphihcsmi_r_r_r
|
|
emit_evdotphihcsmi :: emit_evdotphihcsmi_r_r_r
|
|
inst_evdotplohcsmi :: inst_evdotplohcsmi_r_r_r
|
|
emit_evdotplohcsmi :: emit_evdotplohcsmi_r_r_r
|
|
inst_evdotphihcssfr :: inst_evdotphihcssfr_r_r_r
|
|
emit_evdotphihcssfr :: emit_evdotphihcssfr_r_r_r
|
|
inst_evdotplohcssfr :: inst_evdotplohcssfr_r_r_r
|
|
emit_evdotplohcssfr :: emit_evdotplohcssfr_r_r_r
|
|
inst_evdotphihcssiaaw3 :: inst_evdotphihcssiaaw3_r_r_r
|
|
emit_evdotphihcssiaaw3 :: emit_evdotphihcssiaaw3_r_r_r
|
|
inst_evdotplohcssiaaw3 :: inst_evdotplohcssiaaw3_r_r_r
|
|
emit_evdotplohcssiaaw3 :: emit_evdotplohcssiaaw3_r_r_r
|
|
inst_evdotphihcssfaaw3 :: inst_evdotphihcssfaaw3_r_r_r
|
|
emit_evdotphihcssfaaw3 :: emit_evdotphihcssfaaw3_r_r_r
|
|
inst_evdotplohcssfaaw3 :: inst_evdotplohcssfaaw3_r_r_r
|
|
emit_evdotplohcssfaaw3 :: emit_evdotplohcssfaaw3_r_r_r
|
|
inst_evdotphihcsmiaaw3 :: inst_evdotphihcsmiaaw3_r_r_r
|
|
emit_evdotphihcsmiaaw3 :: emit_evdotphihcsmiaaw3_r_r_r
|
|
inst_evdotplohcsmiaaw3 :: inst_evdotplohcsmiaaw3_r_r_r
|
|
emit_evdotplohcsmiaaw3 :: emit_evdotplohcsmiaaw3_r_r_r
|
|
inst_evdotphihcssfraaw3 :: inst_evdotphihcssfraaw3_r_r_r
|
|
emit_evdotphihcssfraaw3 :: emit_evdotphihcssfraaw3_r_r_r
|
|
inst_evdotplohcssfraaw3 :: inst_evdotplohcssfraaw3_r_r_r
|
|
emit_evdotplohcssfraaw3 :: emit_evdotplohcssfraaw3_r_r_r
|
|
inst_evdotphihcssia :: inst_evdotphihcssia_r_r_r
|
|
emit_evdotphihcssia :: emit_evdotphihcssia_r_r_r
|
|
inst_evdotplohcssia :: inst_evdotplohcssia_r_r_r
|
|
emit_evdotplohcssia :: emit_evdotplohcssia_r_r_r
|
|
inst_evdotphihcssfa :: inst_evdotphihcssfa_r_r_r
|
|
emit_evdotphihcssfa :: emit_evdotphihcssfa_r_r_r
|
|
inst_evdotplohcssfa :: inst_evdotplohcssfa_r_r_r
|
|
emit_evdotplohcssfa :: emit_evdotplohcssfa_r_r_r
|
|
inst_evdotphihcsmia :: inst_evdotphihcsmia_r_r_r
|
|
emit_evdotphihcsmia :: emit_evdotphihcsmia_r_r_r
|
|
inst_evdotplohcsmia :: inst_evdotplohcsmia_r_r_r
|
|
emit_evdotplohcsmia :: emit_evdotplohcsmia_r_r_r
|
|
inst_evdotphihcssfra :: inst_evdotphihcssfra_r_r_r
|
|
emit_evdotphihcssfra :: emit_evdotphihcssfra_r_r_r
|
|
inst_evdotplohcssfra :: inst_evdotplohcssfra_r_r_r
|
|
emit_evdotplohcssfra :: emit_evdotplohcssfra_r_r_r
|
|
inst_evdotphihcssiaaw :: inst_evdotphihcssiaaw_r_r_r
|
|
emit_evdotphihcssiaaw :: emit_evdotphihcssiaaw_r_r_r
|
|
inst_evdotplohcssiaaw :: inst_evdotplohcssiaaw_r_r_r
|
|
emit_evdotplohcssiaaw :: emit_evdotplohcssiaaw_r_r_r
|
|
inst_evdotphihcssfaaw :: inst_evdotphihcssfaaw_r_r_r
|
|
emit_evdotphihcssfaaw :: emit_evdotphihcssfaaw_r_r_r
|
|
inst_evdotplohcssfaaw :: inst_evdotplohcssfaaw_r_r_r
|
|
emit_evdotplohcssfaaw :: emit_evdotplohcssfaaw_r_r_r
|
|
inst_evdotphihcsmiaaw :: inst_evdotphihcsmiaaw_r_r_r
|
|
emit_evdotphihcsmiaaw :: emit_evdotphihcsmiaaw_r_r_r
|
|
inst_evdotplohcsmiaaw :: inst_evdotplohcsmiaaw_r_r_r
|
|
emit_evdotplohcsmiaaw :: emit_evdotplohcsmiaaw_r_r_r
|
|
inst_evdotphihcssfraaw :: inst_evdotphihcssfraaw_r_r_r
|
|
emit_evdotphihcssfraaw :: emit_evdotphihcssfraaw_r_r_r
|
|
inst_evdotplohcssfraaw :: inst_evdotplohcssfraaw_r_r_r
|
|
emit_evdotplohcssfraaw :: emit_evdotplohcssfraaw_r_r_r
|
|
inst_evdotphausi :: inst_evdotphausi_r_r_r
|
|
emit_evdotphausi :: emit_evdotphausi_r_r_r
|
|
inst_evdotphassi :: inst_evdotphassi_r_r_r
|
|
emit_evdotphassi :: emit_evdotphassi_r_r_r
|
|
inst_evdotphasusi :: inst_evdotphasusi_r_r_r
|
|
emit_evdotphasusi :: emit_evdotphasusi_r_r_r
|
|
inst_evdotphassf :: inst_evdotphassf_r_r_r
|
|
emit_evdotphassf :: emit_evdotphassf_r_r_r
|
|
inst_evdotphsssf :: inst_evdotphsssf_r_r_r
|
|
emit_evdotphsssf :: emit_evdotphsssf_r_r_r
|
|
inst_evdotphaumi :: inst_evdotphaumi_r_r_r
|
|
emit_evdotphaumi :: emit_evdotphaumi_r_r_r
|
|
inst_evdotphasmi :: inst_evdotphasmi_r_r_r
|
|
emit_evdotphasmi :: emit_evdotphasmi_r_r_r
|
|
inst_evdotphasumi :: inst_evdotphasumi_r_r_r
|
|
emit_evdotphasumi :: emit_evdotphasumi_r_r_r
|
|
inst_evdotphassfr :: inst_evdotphassfr_r_r_r
|
|
emit_evdotphassfr :: emit_evdotphassfr_r_r_r
|
|
inst_evdotphssmi :: inst_evdotphssmi_r_r_r
|
|
emit_evdotphssmi :: emit_evdotphssmi_r_r_r
|
|
inst_evdotphsssi :: inst_evdotphsssi_r_r_r
|
|
emit_evdotphsssi :: emit_evdotphsssi_r_r_r
|
|
inst_evdotphsssfr :: inst_evdotphsssfr_r_r_r
|
|
emit_evdotphsssfr :: emit_evdotphsssfr_r_r_r
|
|
inst_evdotphausiaaw3 :: inst_evdotphausiaaw3_r_r_r
|
|
emit_evdotphausiaaw3 :: emit_evdotphausiaaw3_r_r_r
|
|
inst_evdotphassiaaw3 :: inst_evdotphassiaaw3_r_r_r
|
|
emit_evdotphassiaaw3 :: emit_evdotphassiaaw3_r_r_r
|
|
inst_evdotphasusiaaw3 :: inst_evdotphasusiaaw3_r_r_r
|
|
emit_evdotphasusiaaw3 :: emit_evdotphasusiaaw3_r_r_r
|
|
inst_evdotphassfaaw3 :: inst_evdotphassfaaw3_r_r_r
|
|
emit_evdotphassfaaw3 :: emit_evdotphassfaaw3_r_r_r
|
|
inst_evdotphsssiaaw3 :: inst_evdotphsssiaaw3_r_r_r
|
|
emit_evdotphsssiaaw3 :: emit_evdotphsssiaaw3_r_r_r
|
|
inst_evdotphsssfaaw3 :: inst_evdotphsssfaaw3_r_r_r
|
|
emit_evdotphsssfaaw3 :: emit_evdotphsssfaaw3_r_r_r
|
|
inst_evdotphaumiaaw3 :: inst_evdotphaumiaaw3_r_r_r
|
|
emit_evdotphaumiaaw3 :: emit_evdotphaumiaaw3_r_r_r
|
|
inst_evdotphasmiaaw3 :: inst_evdotphasmiaaw3_r_r_r
|
|
emit_evdotphasmiaaw3 :: emit_evdotphasmiaaw3_r_r_r
|
|
inst_evdotphasumiaaw3 :: inst_evdotphasumiaaw3_r_r_r
|
|
emit_evdotphasumiaaw3 :: emit_evdotphasumiaaw3_r_r_r
|
|
inst_evdotphassfraaw3 :: inst_evdotphassfraaw3_r_r_r
|
|
emit_evdotphassfraaw3 :: emit_evdotphassfraaw3_r_r_r
|
|
inst_evdotphssmiaaw3 :: inst_evdotphssmiaaw3_r_r_r
|
|
emit_evdotphssmiaaw3 :: emit_evdotphssmiaaw3_r_r_r
|
|
inst_evdotphsssfraaw3 :: inst_evdotphsssfraaw3_r_r_r
|
|
emit_evdotphsssfraaw3 :: emit_evdotphsssfraaw3_r_r_r
|
|
inst_evdotphausia :: inst_evdotphausia_r_r_r
|
|
emit_evdotphausia :: emit_evdotphausia_r_r_r
|
|
inst_evdotphassia :: inst_evdotphassia_r_r_r
|
|
emit_evdotphassia :: emit_evdotphassia_r_r_r
|
|
inst_evdotphasusia :: inst_evdotphasusia_r_r_r
|
|
emit_evdotphasusia :: emit_evdotphasusia_r_r_r
|
|
inst_evdotphassfa :: inst_evdotphassfa_r_r_r
|
|
emit_evdotphassfa :: emit_evdotphassfa_r_r_r
|
|
inst_evdotphsssfa :: inst_evdotphsssfa_r_r_r
|
|
emit_evdotphsssfa :: emit_evdotphsssfa_r_r_r
|
|
inst_evdotphaumia :: inst_evdotphaumia_r_r_r
|
|
emit_evdotphaumia :: emit_evdotphaumia_r_r_r
|
|
inst_evdotphasmia :: inst_evdotphasmia_r_r_r
|
|
emit_evdotphasmia :: emit_evdotphasmia_r_r_r
|
|
inst_evdotphasumia :: inst_evdotphasumia_r_r_r
|
|
emit_evdotphasumia :: emit_evdotphasumia_r_r_r
|
|
inst_evdotphassfra :: inst_evdotphassfra_r_r_r
|
|
emit_evdotphassfra :: emit_evdotphassfra_r_r_r
|
|
inst_evdotphssmia :: inst_evdotphssmia_r_r_r
|
|
emit_evdotphssmia :: emit_evdotphssmia_r_r_r
|
|
inst_evdotphsssia :: inst_evdotphsssia_r_r_r
|
|
emit_evdotphsssia :: emit_evdotphsssia_r_r_r
|
|
inst_evdotphsssfra :: inst_evdotphsssfra_r_r_r
|
|
emit_evdotphsssfra :: emit_evdotphsssfra_r_r_r
|
|
inst_evdotphausiaaw :: inst_evdotphausiaaw_r_r_r
|
|
emit_evdotphausiaaw :: emit_evdotphausiaaw_r_r_r
|
|
inst_evdotphassiaaw :: inst_evdotphassiaaw_r_r_r
|
|
emit_evdotphassiaaw :: emit_evdotphassiaaw_r_r_r
|
|
inst_evdotphasusiaaw :: inst_evdotphasusiaaw_r_r_r
|
|
emit_evdotphasusiaaw :: emit_evdotphasusiaaw_r_r_r
|
|
inst_evdotphassfaaw :: inst_evdotphassfaaw_r_r_r
|
|
emit_evdotphassfaaw :: emit_evdotphassfaaw_r_r_r
|
|
inst_evdotphsssiaaw :: inst_evdotphsssiaaw_r_r_r
|
|
emit_evdotphsssiaaw :: emit_evdotphsssiaaw_r_r_r
|
|
inst_evdotphsssfaaw :: inst_evdotphsssfaaw_r_r_r
|
|
emit_evdotphsssfaaw :: emit_evdotphsssfaaw_r_r_r
|
|
inst_evdotphaumiaaw :: inst_evdotphaumiaaw_r_r_r
|
|
emit_evdotphaumiaaw :: emit_evdotphaumiaaw_r_r_r
|
|
inst_evdotphasmiaaw :: inst_evdotphasmiaaw_r_r_r
|
|
emit_evdotphasmiaaw :: emit_evdotphasmiaaw_r_r_r
|
|
inst_evdotphasumiaaw :: inst_evdotphasumiaaw_r_r_r
|
|
emit_evdotphasumiaaw :: emit_evdotphasumiaaw_r_r_r
|
|
inst_evdotphassfraaw :: inst_evdotphassfraaw_r_r_r
|
|
emit_evdotphassfraaw :: emit_evdotphassfraaw_r_r_r
|
|
inst_evdotphssmiaaw :: inst_evdotphssmiaaw_r_r_r
|
|
emit_evdotphssmiaaw :: emit_evdotphssmiaaw_r_r_r
|
|
inst_evdotphsssfraaw :: inst_evdotphsssfraaw_r_r_r
|
|
emit_evdotphsssfraaw :: emit_evdotphsssfraaw_r_r_r
|
|
inst_evdotp4hgaumi :: inst_evdotp4hgaumi_r_r_r
|
|
emit_evdotp4hgaumi :: emit_evdotp4hgaumi_r_r_r
|
|
inst_evdotp4hgasmi :: inst_evdotp4hgasmi_r_r_r
|
|
emit_evdotp4hgasmi :: emit_evdotp4hgasmi_r_r_r
|
|
inst_evdotp4hgasumi :: inst_evdotp4hgasumi_r_r_r
|
|
emit_evdotp4hgasumi :: emit_evdotp4hgasumi_r_r_r
|
|
inst_evdotp4hgasmf :: inst_evdotp4hgasmf_r_r_r
|
|
emit_evdotp4hgasmf :: emit_evdotp4hgasmf_r_r_r
|
|
inst_evdotp4hgssmi :: inst_evdotp4hgssmi_r_r_r
|
|
emit_evdotp4hgssmi :: emit_evdotp4hgssmi_r_r_r
|
|
inst_evdotp4hgssmf :: inst_evdotp4hgssmf_r_r_r
|
|
emit_evdotp4hgssmf :: emit_evdotp4hgssmf_r_r_r
|
|
inst_evdotp4hxgasmi :: inst_evdotp4hxgasmi_r_r_r
|
|
emit_evdotp4hxgasmi :: emit_evdotp4hxgasmi_r_r_r
|
|
inst_evdotp4hxgasmf :: inst_evdotp4hxgasmf_r_r_r
|
|
emit_evdotp4hxgasmf :: emit_evdotp4hxgasmf_r_r_r
|
|
inst_evdotpbaumi :: inst_evdotpbaumi_r_r_r
|
|
emit_evdotpbaumi :: emit_evdotpbaumi_r_r_r
|
|
inst_evdotpbasmi :: inst_evdotpbasmi_r_r_r
|
|
emit_evdotpbasmi :: emit_evdotpbasmi_r_r_r
|
|
inst_evdotpbasumi :: inst_evdotpbasumi_r_r_r
|
|
emit_evdotpbasumi :: emit_evdotpbasumi_r_r_r
|
|
inst_evdotp4hxgssmi :: inst_evdotp4hxgssmi_r_r_r
|
|
emit_evdotp4hxgssmi :: emit_evdotp4hxgssmi_r_r_r
|
|
inst_evdotp4hxgssmf :: inst_evdotp4hxgssmf_r_r_r
|
|
emit_evdotp4hxgssmf :: emit_evdotp4hxgssmf_r_r_r
|
|
inst_evdotp4hgaumiaa3 :: inst_evdotp4hgaumiaa3_r_r_r
|
|
emit_evdotp4hgaumiaa3 :: emit_evdotp4hgaumiaa3_r_r_r
|
|
inst_evdotp4hgasmiaa3 :: inst_evdotp4hgasmiaa3_r_r_r
|
|
emit_evdotp4hgasmiaa3 :: emit_evdotp4hgasmiaa3_r_r_r
|
|
inst_evdotp4hgasumiaa3 :: inst_evdotp4hgasumiaa3_r_r_r
|
|
emit_evdotp4hgasumiaa3 :: emit_evdotp4hgasumiaa3_r_r_r
|
|
inst_evdotp4hgasmfaa3 :: inst_evdotp4hgasmfaa3_r_r_r
|
|
emit_evdotp4hgasmfaa3 :: emit_evdotp4hgasmfaa3_r_r_r
|
|
inst_evdotp4hgssmiaa3 :: inst_evdotp4hgssmiaa3_r_r_r
|
|
emit_evdotp4hgssmiaa3 :: emit_evdotp4hgssmiaa3_r_r_r
|
|
inst_evdotp4hgssmfaa3 :: inst_evdotp4hgssmfaa3_r_r_r
|
|
emit_evdotp4hgssmfaa3 :: emit_evdotp4hgssmfaa3_r_r_r
|
|
inst_evdotp4hxgasmiaa3 :: inst_evdotp4hxgasmiaa3_r_r_r
|
|
emit_evdotp4hxgasmiaa3 :: emit_evdotp4hxgasmiaa3_r_r_r
|
|
inst_evdotp4hxgasmfaa3 :: inst_evdotp4hxgasmfaa3_r_r_r
|
|
emit_evdotp4hxgasmfaa3 :: emit_evdotp4hxgasmfaa3_r_r_r
|
|
inst_evdotpbaumiaaw3 :: inst_evdotpbaumiaaw3_r_r_r
|
|
emit_evdotpbaumiaaw3 :: emit_evdotpbaumiaaw3_r_r_r
|
|
inst_evdotpbasmiaaw3 :: inst_evdotpbasmiaaw3_r_r_r
|
|
emit_evdotpbasmiaaw3 :: emit_evdotpbasmiaaw3_r_r_r
|
|
inst_evdotpbasumiaaw3 :: inst_evdotpbasumiaaw3_r_r_r
|
|
emit_evdotpbasumiaaw3 :: emit_evdotpbasumiaaw3_r_r_r
|
|
inst_evdotp4hxgssmiaa3 :: inst_evdotp4hxgssmiaa3_r_r_r
|
|
emit_evdotp4hxgssmiaa3 :: emit_evdotp4hxgssmiaa3_r_r_r
|
|
inst_evdotp4hxgssmfaa3 :: inst_evdotp4hxgssmfaa3_r_r_r
|
|
emit_evdotp4hxgssmfaa3 :: emit_evdotp4hxgssmfaa3_r_r_r
|
|
inst_evdotp4hgaumia :: inst_evdotp4hgaumia_r_r_r
|
|
emit_evdotp4hgaumia :: emit_evdotp4hgaumia_r_r_r
|
|
inst_evdotp4hgasmia :: inst_evdotp4hgasmia_r_r_r
|
|
emit_evdotp4hgasmia :: emit_evdotp4hgasmia_r_r_r
|
|
inst_evdotp4hgasumia :: inst_evdotp4hgasumia_r_r_r
|
|
emit_evdotp4hgasumia :: emit_evdotp4hgasumia_r_r_r
|
|
inst_evdotp4hgasmfa :: inst_evdotp4hgasmfa_r_r_r
|
|
emit_evdotp4hgasmfa :: emit_evdotp4hgasmfa_r_r_r
|
|
inst_evdotp4hgssmia :: inst_evdotp4hgssmia_r_r_r
|
|
emit_evdotp4hgssmia :: emit_evdotp4hgssmia_r_r_r
|
|
inst_evdotp4hgssmfa :: inst_evdotp4hgssmfa_r_r_r
|
|
emit_evdotp4hgssmfa :: emit_evdotp4hgssmfa_r_r_r
|
|
inst_evdotp4hxgasmia :: inst_evdotp4hxgasmia_r_r_r
|
|
emit_evdotp4hxgasmia :: emit_evdotp4hxgasmia_r_r_r
|
|
inst_evdotp4hxgasmfa :: inst_evdotp4hxgasmfa_r_r_r
|
|
emit_evdotp4hxgasmfa :: emit_evdotp4hxgasmfa_r_r_r
|
|
inst_evdotpbaumia :: inst_evdotpbaumia_r_r_r
|
|
emit_evdotpbaumia :: emit_evdotpbaumia_r_r_r
|
|
inst_evdotpbasmia :: inst_evdotpbasmia_r_r_r
|
|
emit_evdotpbasmia :: emit_evdotpbasmia_r_r_r
|
|
inst_evdotpbasumia :: inst_evdotpbasumia_r_r_r
|
|
emit_evdotpbasumia :: emit_evdotpbasumia_r_r_r
|
|
inst_evdotp4hxgssmia :: inst_evdotp4hxgssmia_r_r_r
|
|
emit_evdotp4hxgssmia :: emit_evdotp4hxgssmia_r_r_r
|
|
inst_evdotp4hxgssmfa :: inst_evdotp4hxgssmfa_r_r_r
|
|
emit_evdotp4hxgssmfa :: emit_evdotp4hxgssmfa_r_r_r
|
|
inst_evdotp4hgaumiaa :: inst_evdotp4hgaumiaa_r_r_r
|
|
emit_evdotp4hgaumiaa :: emit_evdotp4hgaumiaa_r_r_r
|
|
inst_evdotp4hgasmiaa :: inst_evdotp4hgasmiaa_r_r_r
|
|
emit_evdotp4hgasmiaa :: emit_evdotp4hgasmiaa_r_r_r
|
|
inst_evdotp4hgasumiaa :: inst_evdotp4hgasumiaa_r_r_r
|
|
emit_evdotp4hgasumiaa :: emit_evdotp4hgasumiaa_r_r_r
|
|
inst_evdotp4hgasmfaa :: inst_evdotp4hgasmfaa_r_r_r
|
|
emit_evdotp4hgasmfaa :: emit_evdotp4hgasmfaa_r_r_r
|
|
inst_evdotp4hgssmiaa :: inst_evdotp4hgssmiaa_r_r_r
|
|
emit_evdotp4hgssmiaa :: emit_evdotp4hgssmiaa_r_r_r
|
|
inst_evdotp4hgssmfaa :: inst_evdotp4hgssmfaa_r_r_r
|
|
emit_evdotp4hgssmfaa :: emit_evdotp4hgssmfaa_r_r_r
|
|
inst_evdotp4hxgasmiaa :: inst_evdotp4hxgasmiaa_r_r_r
|
|
emit_evdotp4hxgasmiaa :: emit_evdotp4hxgasmiaa_r_r_r
|
|
inst_evdotp4hxgasmfaa :: inst_evdotp4hxgasmfaa_r_r_r
|
|
emit_evdotp4hxgasmfaa :: emit_evdotp4hxgasmfaa_r_r_r
|
|
inst_evdotpbaumiaaw :: inst_evdotpbaumiaaw_r_r_r
|
|
emit_evdotpbaumiaaw :: emit_evdotpbaumiaaw_r_r_r
|
|
inst_evdotpbasmiaaw :: inst_evdotpbasmiaaw_r_r_r
|
|
emit_evdotpbasmiaaw :: emit_evdotpbasmiaaw_r_r_r
|
|
inst_evdotpbasumiaaw :: inst_evdotpbasumiaaw_r_r_r
|
|
emit_evdotpbasumiaaw :: emit_evdotpbasumiaaw_r_r_r
|
|
inst_evdotp4hxgssmiaa :: inst_evdotp4hxgssmiaa_r_r_r
|
|
emit_evdotp4hxgssmiaa :: emit_evdotp4hxgssmiaa_r_r_r
|
|
inst_evdotp4hxgssmfaa :: inst_evdotp4hxgssmfaa_r_r_r
|
|
emit_evdotp4hxgssmfaa :: emit_evdotp4hxgssmfaa_r_r_r
|
|
inst_evdotpwausi :: inst_evdotpwausi_r_r_r
|
|
emit_evdotpwausi :: emit_evdotpwausi_r_r_r
|
|
inst_evdotpwassi :: inst_evdotpwassi_r_r_r
|
|
emit_evdotpwassi :: emit_evdotpwassi_r_r_r
|
|
inst_evdotpwasusi :: inst_evdotpwasusi_r_r_r
|
|
emit_evdotpwasusi :: emit_evdotpwasusi_r_r_r
|
|
inst_evdotpwaumi :: inst_evdotpwaumi_r_r_r
|
|
emit_evdotpwaumi :: emit_evdotpwaumi_r_r_r
|
|
inst_evdotpwasmi :: inst_evdotpwasmi_r_r_r
|
|
emit_evdotpwasmi :: emit_evdotpwasmi_r_r_r
|
|
inst_evdotpwasumi :: inst_evdotpwasumi_r_r_r
|
|
emit_evdotpwasumi :: emit_evdotpwasumi_r_r_r
|
|
inst_evdotpwssmi :: inst_evdotpwssmi_r_r_r
|
|
emit_evdotpwssmi :: emit_evdotpwssmi_r_r_r
|
|
inst_evdotpwsssi :: inst_evdotpwsssi_r_r_r
|
|
emit_evdotpwsssi :: emit_evdotpwsssi_r_r_r
|
|
inst_evdotpwausiaa3 :: inst_evdotpwausiaa3_r_r_r
|
|
emit_evdotpwausiaa3 :: emit_evdotpwausiaa3_r_r_r
|
|
inst_evdotpwassiaa3 :: inst_evdotpwassiaa3_r_r_r
|
|
emit_evdotpwassiaa3 :: emit_evdotpwassiaa3_r_r_r
|
|
inst_evdotpwasusiaa3 :: inst_evdotpwasusiaa3_r_r_r
|
|
emit_evdotpwasusiaa3 :: emit_evdotpwasusiaa3_r_r_r
|
|
inst_evdotpwsssiaa3 :: inst_evdotpwsssiaa3_r_r_r
|
|
emit_evdotpwsssiaa3 :: emit_evdotpwsssiaa3_r_r_r
|
|
inst_evdotpwaumiaa3 :: inst_evdotpwaumiaa3_r_r_r
|
|
emit_evdotpwaumiaa3 :: emit_evdotpwaumiaa3_r_r_r
|
|
inst_evdotpwasmiaa3 :: inst_evdotpwasmiaa3_r_r_r
|
|
emit_evdotpwasmiaa3 :: emit_evdotpwasmiaa3_r_r_r
|
|
inst_evdotpwasumiaa3 :: inst_evdotpwasumiaa3_r_r_r
|
|
emit_evdotpwasumiaa3 :: emit_evdotpwasumiaa3_r_r_r
|
|
inst_evdotpwssmiaa3 :: inst_evdotpwssmiaa3_r_r_r
|
|
emit_evdotpwssmiaa3 :: emit_evdotpwssmiaa3_r_r_r
|
|
inst_evdotpwausia :: inst_evdotpwausia_r_r_r
|
|
emit_evdotpwausia :: emit_evdotpwausia_r_r_r
|
|
inst_evdotpwassia :: inst_evdotpwassia_r_r_r
|
|
emit_evdotpwassia :: emit_evdotpwassia_r_r_r
|
|
inst_evdotpwasusia :: inst_evdotpwasusia_r_r_r
|
|
emit_evdotpwasusia :: emit_evdotpwasusia_r_r_r
|
|
inst_evdotpwaumia :: inst_evdotpwaumia_r_r_r
|
|
emit_evdotpwaumia :: emit_evdotpwaumia_r_r_r
|
|
inst_evdotpwasmia :: inst_evdotpwasmia_r_r_r
|
|
emit_evdotpwasmia :: emit_evdotpwasmia_r_r_r
|
|
inst_evdotpwasumia :: inst_evdotpwasumia_r_r_r
|
|
emit_evdotpwasumia :: emit_evdotpwasumia_r_r_r
|
|
inst_evdotpwssmia :: inst_evdotpwssmia_r_r_r
|
|
emit_evdotpwssmia :: emit_evdotpwssmia_r_r_r
|
|
inst_evdotpwsssia :: inst_evdotpwsssia_r_r_r
|
|
emit_evdotpwsssia :: emit_evdotpwsssia_r_r_r
|
|
inst_evdotpwausiaa :: inst_evdotpwausiaa_r_r_r
|
|
emit_evdotpwausiaa :: emit_evdotpwausiaa_r_r_r
|
|
inst_evdotpwassiaa :: inst_evdotpwassiaa_r_r_r
|
|
emit_evdotpwassiaa :: emit_evdotpwassiaa_r_r_r
|
|
inst_evdotpwasusiaa :: inst_evdotpwasusiaa_r_r_r
|
|
emit_evdotpwasusiaa :: emit_evdotpwasusiaa_r_r_r
|
|
inst_evdotpwsssiaa :: inst_evdotpwsssiaa_r_r_r
|
|
emit_evdotpwsssiaa :: emit_evdotpwsssiaa_r_r_r
|
|
inst_evdotpwaumiaa :: inst_evdotpwaumiaa_r_r_r
|
|
emit_evdotpwaumiaa :: emit_evdotpwaumiaa_r_r_r
|
|
inst_evdotpwasmiaa :: inst_evdotpwasmiaa_r_r_r
|
|
emit_evdotpwasmiaa :: emit_evdotpwasmiaa_r_r_r
|
|
inst_evdotpwasumiaa :: inst_evdotpwasumiaa_r_r_r
|
|
emit_evdotpwasumiaa :: emit_evdotpwasumiaa_r_r_r
|
|
inst_evdotpwssmiaa :: inst_evdotpwssmiaa_r_r_r
|
|
emit_evdotpwssmiaa :: emit_evdotpwssmiaa_r_r_r
|
|
inst_evaddib :: inst_evaddib_r_r_r
|
|
emit_evaddib :: emit_evaddib_r_r_r
|
|
inst_evaddih :: inst_evaddih_r_r_r
|
|
emit_evaddih :: emit_evaddih_r_r_r
|
|
inst_evsubifh :: inst_evsubifh_r_r_r
|
|
emit_evsubifh :: emit_evsubifh_r_r_r
|
|
inst_evsubifb :: inst_evsubifb_r_r_r
|
|
emit_evsubifb :: emit_evsubifb_r_r_r
|
|
inst_evabsb :: inst_evabsb_r_r_r
|
|
emit_evabsb :: emit_evabsb_r_r_r
|
|
inst_evabsh :: inst_evabsh_r_r_r
|
|
emit_evabsh :: emit_evabsh_r_r_r
|
|
inst_evabsd :: inst_evabsd_r_r_r
|
|
emit_evabsd :: emit_evabsd_r_r_r
|
|
inst_evabss :: inst_evabss_r_r_r
|
|
emit_evabss :: emit_evabss_r_r_r
|
|
inst_evabsbs :: inst_evabsbs_r_r_r
|
|
emit_evabsbs :: emit_evabsbs_r_r_r
|
|
inst_evabshs :: inst_evabshs_r_r_r
|
|
emit_evabshs :: emit_evabshs_r_r_r
|
|
inst_evabsds :: inst_evabsds_r_r_r
|
|
emit_evabsds :: emit_evabsds_r_r_r
|
|
inst_evnegwo :: inst_evnegwo_r_r_r
|
|
emit_evnegwo :: emit_evnegwo_r_r_r
|
|
inst_evnegb :: inst_evnegb_r_r_r
|
|
emit_evnegb :: emit_evnegb_r_r_r
|
|
inst_evnegbo :: inst_evnegbo_r_r_r
|
|
emit_evnegbo :: emit_evnegbo_r_r_r
|
|
inst_evnegh :: inst_evnegh_r_r_r
|
|
emit_evnegh :: emit_evnegh_r_r_r
|
|
inst_evnegho :: inst_evnegho_r_r_r
|
|
emit_evnegho :: emit_evnegho_r_r_r
|
|
inst_evnegd :: inst_evnegd_r_r_r
|
|
emit_evnegd :: emit_evnegd_r_r_r
|
|
inst_evnegs :: inst_evnegs_r_r_r
|
|
emit_evnegs :: emit_evnegs_r_r_r
|
|
inst_evnegwos :: inst_evnegwos_r_r_r
|
|
emit_evnegwos :: emit_evnegwos_r_r_r
|
|
inst_evnegbs :: inst_evnegbs_r_r_r
|
|
emit_evnegbs :: emit_evnegbs_r_r_r
|
|
inst_evnegbos :: inst_evnegbos_r_r_r
|
|
emit_evnegbos :: emit_evnegbos_r_r_r
|
|
inst_evneghs :: inst_evneghs_r_r_r
|
|
emit_evneghs :: emit_evneghs_r_r_r
|
|
inst_evneghos :: inst_evneghos_r_r_r
|
|
emit_evneghos :: emit_evneghos_r_r_r
|
|
inst_evnegds :: inst_evnegds_r_r_r
|
|
emit_evnegds :: emit_evnegds_r_r_r
|
|
inst_evextzb :: inst_evextzb_r_r_r
|
|
emit_evextzb :: emit_evextzb_r_r_r
|
|
inst_evextsbh :: inst_evextsbh_r_r_r
|
|
emit_evextsbh :: emit_evextsbh_r_r_r
|
|
inst_evextsw :: inst_evextsw_r_r_r
|
|
emit_evextsw :: emit_evextsw_r_r_r
|
|
inst_evrndwh :: inst_evrndwh_r_r_r
|
|
emit_evrndwh :: emit_evrndwh_r_r_r
|
|
inst_evrndhb :: inst_evrndhb_r_r_r
|
|
emit_evrndhb :: emit_evrndhb_r_r_r
|
|
inst_evrnddw :: inst_evrnddw_r_r_r
|
|
emit_evrnddw :: emit_evrnddw_r_r_r
|
|
inst_evrndwhus :: inst_evrndwhus_r_r_r
|
|
emit_evrndwhus :: emit_evrndwhus_r_r_r
|
|
inst_evrndwhss :: inst_evrndwhss_r_r_r
|
|
emit_evrndwhss :: emit_evrndwhss_r_r_r
|
|
inst_evrndhbus :: inst_evrndhbus_r_r_r
|
|
emit_evrndhbus :: emit_evrndhbus_r_r_r
|
|
inst_evrndhbss :: inst_evrndhbss_r_r_r
|
|
emit_evrndhbss :: emit_evrndhbss_r_r_r
|
|
inst_evrnddwus :: inst_evrnddwus_r_r_r
|
|
emit_evrnddwus :: emit_evrnddwus_r_r_r
|
|
inst_evrnddwss :: inst_evrnddwss_r_r_r
|
|
emit_evrnddwss :: emit_evrnddwss_r_r_r
|
|
inst_evrndwnh :: inst_evrndwnh_r_r_r
|
|
emit_evrndwnh :: emit_evrndwnh_r_r_r
|
|
inst_evrndhnb :: inst_evrndhnb_r_r_r
|
|
emit_evrndhnb :: emit_evrndhnb_r_r_r
|
|
inst_evrnddnw :: inst_evrnddnw_r_r_r
|
|
emit_evrnddnw :: emit_evrnddnw_r_r_r
|
|
inst_evrndwnhus :: inst_evrndwnhus_r_r_r
|
|
emit_evrndwnhus :: emit_evrndwnhus_r_r_r
|
|
inst_evrndwnhss :: inst_evrndwnhss_r_r_r
|
|
emit_evrndwnhss :: emit_evrndwnhss_r_r_r
|
|
inst_evrndhnbus :: inst_evrndhnbus_r_r_r
|
|
emit_evrndhnbus :: emit_evrndhnbus_r_r_r
|
|
inst_evrndhnbss :: inst_evrndhnbss_r_r_r
|
|
emit_evrndhnbss :: emit_evrndhnbss_r_r_r
|
|
inst_evrnddnwus :: inst_evrnddnwus_r_r_r
|
|
emit_evrnddnwus :: emit_evrnddnwus_r_r_r
|
|
inst_evrnddnwss :: inst_evrnddnwss_r_r_r
|
|
emit_evrnddnwss :: emit_evrnddnwss_r_r_r
|
|
inst_evcntlzh :: inst_evcntlzh_r_r_r
|
|
emit_evcntlzh :: emit_evcntlzh_r_r_r
|
|
inst_evcntlsh :: inst_evcntlsh_r_r_r
|
|
emit_evcntlsh :: emit_evcntlsh_r_r_r
|
|
inst_evpopcntb :: inst_evpopcntb_r_r_r
|
|
emit_evpopcntb :: emit_evpopcntb_r_r_r
|
|
inst_circinc :: inst_circinc_r_r_r
|
|
emit_circinc :: emit_circinc_r_r_r
|
|
inst_evunpkhibui :: inst_evunpkhibui_r_r_r
|
|
emit_evunpkhibui :: emit_evunpkhibui_r_r_r
|
|
inst_evunpkhibsi :: inst_evunpkhibsi_r_r_r
|
|
emit_evunpkhibsi :: emit_evunpkhibsi_r_r_r
|
|
inst_evunpkhihui :: inst_evunpkhihui_r_r_r
|
|
emit_evunpkhihui :: emit_evunpkhihui_r_r_r
|
|
inst_evunpkhihsi :: inst_evunpkhihsi_r_r_r
|
|
emit_evunpkhihsi :: emit_evunpkhihsi_r_r_r
|
|
inst_evunpklobui :: inst_evunpklobui_r_r_r
|
|
emit_evunpklobui :: emit_evunpklobui_r_r_r
|
|
inst_evunpklobsi :: inst_evunpklobsi_r_r_r
|
|
emit_evunpklobsi :: emit_evunpklobsi_r_r_r
|
|
inst_evunpklohui :: inst_evunpklohui_r_r_r
|
|
emit_evunpklohui :: emit_evunpklohui_r_r_r
|
|
inst_evunpklohsi :: inst_evunpklohsi_r_r_r
|
|
emit_evunpklohsi :: emit_evunpklohsi_r_r_r
|
|
inst_evunpklohf :: inst_evunpklohf_r_r_r
|
|
emit_evunpklohf :: emit_evunpklohf_r_r_r
|
|
inst_evunpkhihf :: inst_evunpkhihf_r_r_r
|
|
emit_evunpkhihf :: emit_evunpkhihf_r_r_r
|
|
inst_evunpklowgsf :: inst_evunpklowgsf_r_r_r
|
|
emit_evunpklowgsf :: emit_evunpklowgsf_r_r_r
|
|
inst_evunpkhiwgsf :: inst_evunpkhiwgsf_r_r_r
|
|
emit_evunpkhiwgsf :: emit_evunpkhiwgsf_r_r_r
|
|
inst_evsatsduw :: inst_evsatsduw_r_r_r
|
|
emit_evsatsduw :: emit_evsatsduw_r_r_r
|
|
inst_evsatsdsw :: inst_evsatsdsw_r_r_r
|
|
emit_evsatsdsw :: emit_evsatsdsw_r_r_r
|
|
inst_evsatshub :: inst_evsatshub_r_r_r
|
|
emit_evsatshub :: emit_evsatshub_r_r_r
|
|
inst_evsatshsb :: inst_evsatshsb_r_r_r
|
|
emit_evsatshsb :: emit_evsatshsb_r_r_r
|
|
inst_evsatuwuh :: inst_evsatuwuh_r_r_r
|
|
emit_evsatuwuh :: emit_evsatuwuh_r_r_r
|
|
inst_evsatswsh :: inst_evsatswsh_r_r_r
|
|
emit_evsatswsh :: emit_evsatswsh_r_r_r
|
|
inst_evsatswuh :: inst_evsatswuh_r_r_r
|
|
emit_evsatswuh :: emit_evsatswuh_r_r_r
|
|
inst_evsatuhub :: inst_evsatuhub_r_r_r
|
|
emit_evsatuhub :: emit_evsatuhub_r_r_r
|
|
inst_evsatuduw :: inst_evsatuduw_r_r_r
|
|
emit_evsatuduw :: emit_evsatuduw_r_r_r
|
|
inst_evsatuwsw :: inst_evsatuwsw_r_r_r
|
|
emit_evsatuwsw :: emit_evsatuwsw_r_r_r
|
|
inst_evsatshuh :: inst_evsatshuh_r_r_r
|
|
emit_evsatshuh :: emit_evsatshuh_r_r_r
|
|
inst_evsatuhsh :: inst_evsatuhsh_r_r_r
|
|
emit_evsatuhsh :: emit_evsatuhsh_r_r_r
|
|
inst_evsatswuw :: inst_evsatswuw_r_r_r
|
|
emit_evsatswuw :: emit_evsatswuw_r_r_r
|
|
inst_evsatswgsdf :: inst_evsatswgsdf_r_r_r
|
|
emit_evsatswgsdf :: emit_evsatswgsdf_r_r_r
|
|
inst_evsatsbub :: inst_evsatsbub_r_r_r
|
|
emit_evsatsbub :: emit_evsatsbub_r_r_r
|
|
inst_evsatubsb :: inst_evsatubsb_r_r_r
|
|
emit_evsatubsb :: emit_evsatubsb_r_r_r
|
|
inst_evmaxhpuw :: inst_evmaxhpuw_r_r_r
|
|
emit_evmaxhpuw :: emit_evmaxhpuw_r_r_r
|
|
inst_evmaxhpsw :: inst_evmaxhpsw_r_r_r
|
|
emit_evmaxhpsw :: emit_evmaxhpsw_r_r_r
|
|
inst_evmaxbpuh :: inst_evmaxbpuh_r_r_r
|
|
emit_evmaxbpuh :: emit_evmaxbpuh_r_r_r
|
|
inst_evmaxbpsh :: inst_evmaxbpsh_r_r_r
|
|
emit_evmaxbpsh :: emit_evmaxbpsh_r_r_r
|
|
inst_evmaxwpud :: inst_evmaxwpud_r_r_r
|
|
emit_evmaxwpud :: emit_evmaxwpud_r_r_r
|
|
inst_evmaxwpsd :: inst_evmaxwpsd_r_r_r
|
|
emit_evmaxwpsd :: emit_evmaxwpsd_r_r_r
|
|
inst_evminhpuw :: inst_evminhpuw_r_r_r
|
|
emit_evminhpuw :: emit_evminhpuw_r_r_r
|
|
inst_evminhpsw :: inst_evminhpsw_r_r_r
|
|
emit_evminhpsw :: emit_evminhpsw_r_r_r
|
|
inst_evminbpuh :: inst_evminbpuh_r_r_r
|
|
emit_evminbpuh :: emit_evminbpuh_r_r_r
|
|
inst_evminbpsh :: inst_evminbpsh_r_r_r
|
|
emit_evminbpsh :: emit_evminbpsh_r_r_r
|
|
inst_evminwpud :: inst_evminwpud_r_r_r
|
|
emit_evminwpud :: emit_evminwpud_r_r_r
|
|
inst_evminwpsd :: inst_evminwpsd_r_r_r
|
|
emit_evminwpsd :: emit_evminwpsd_r_r_r
|
|
inst_evmaxmagws :: inst_evmaxmagws_r_r_r
|
|
emit_evmaxmagws :: emit_evmaxmagws_r_r_r
|
|
inst_evsl :: inst_evsl_r_r_r
|
|
emit_evsl :: emit_evsl_r_r_r
|
|
inst_evsli :: inst_evsli_r_r_r
|
|
emit_evsli :: emit_evsli_r_r_r
|
|
inst_evsplatie :: inst_evsplatie_r_r_r
|
|
emit_evsplatie :: emit_evsplatie_r_r_r
|
|
inst_evsplatib :: inst_evsplatib_r_r_r
|
|
emit_evsplatib :: emit_evsplatib_r_r_r
|
|
inst_evsplatibe :: inst_evsplatibe_r_r_r
|
|
emit_evsplatibe :: emit_evsplatibe_r_r_r
|
|
inst_evsplatih :: inst_evsplatih_r_r_r
|
|
emit_evsplatih :: emit_evsplatih_r_r_r
|
|
inst_evsplatihe :: inst_evsplatihe_r_r_r
|
|
emit_evsplatihe :: emit_evsplatihe_r_r_r
|
|
inst_evsplatid :: inst_evsplatid_r_r_r
|
|
emit_evsplatid :: emit_evsplatid_r_r_r
|
|
inst_evsplatia :: inst_evsplatia_r_r_r
|
|
emit_evsplatia :: emit_evsplatia_r_r_r
|
|
inst_evsplatiea :: inst_evsplatiea_r_r_r
|
|
emit_evsplatiea :: emit_evsplatiea_r_r_r
|
|
inst_evsplatiba :: inst_evsplatiba_r_r_r
|
|
emit_evsplatiba :: emit_evsplatiba_r_r_r
|
|
inst_evsplatibea :: inst_evsplatibea_r_r_r
|
|
emit_evsplatibea :: emit_evsplatibea_r_r_r
|
|
inst_evsplatiha :: inst_evsplatiha_r_r_r
|
|
emit_evsplatiha :: emit_evsplatiha_r_r_r
|
|
inst_evsplatihea :: inst_evsplatihea_r_r_r
|
|
emit_evsplatihea :: emit_evsplatihea_r_r_r
|
|
inst_evsplatida :: inst_evsplatida_r_r_r
|
|
emit_evsplatida :: emit_evsplatida_r_r_r
|
|
inst_evsplatfio :: inst_evsplatfio_r_r_r
|
|
emit_evsplatfio :: emit_evsplatfio_r_r_r
|
|
inst_evsplatfib :: inst_evsplatfib_r_r_r
|
|
emit_evsplatfib :: emit_evsplatfib_r_r_r
|
|
inst_evsplatfibo :: inst_evsplatfibo_r_r_r
|
|
emit_evsplatfibo :: emit_evsplatfibo_r_r_r
|
|
inst_evsplatfih :: inst_evsplatfih_r_r_r
|
|
emit_evsplatfih :: emit_evsplatfih_r_r_r
|
|
inst_evsplatfiho :: inst_evsplatfiho_r_r_r
|
|
emit_evsplatfiho :: emit_evsplatfiho_r_r_r
|
|
inst_evsplatfid :: inst_evsplatfid_r_r_r
|
|
emit_evsplatfid :: emit_evsplatfid_r_r_r
|
|
inst_evsplatfia :: inst_evsplatfia_r_r_r
|
|
emit_evsplatfia :: emit_evsplatfia_r_r_r
|
|
inst_evsplatfioa :: inst_evsplatfioa_r_r_r
|
|
emit_evsplatfioa :: emit_evsplatfioa_r_r_r
|
|
inst_evsplatfiba :: inst_evsplatfiba_r_r_r
|
|
emit_evsplatfiba :: emit_evsplatfiba_r_r_r
|
|
inst_evsplatfiboa :: inst_evsplatfiboa_r_r_r
|
|
emit_evsplatfiboa :: emit_evsplatfiboa_r_r_r
|
|
inst_evsplatfiha :: inst_evsplatfiha_r_r_r
|
|
emit_evsplatfiha :: emit_evsplatfiha_r_r_r
|
|
inst_evsplatfihoa :: inst_evsplatfihoa_r_r_r
|
|
emit_evsplatfihoa :: emit_evsplatfihoa_r_r_r
|
|
inst_evsplatfida :: inst_evsplatfida_r_r_r
|
|
emit_evsplatfida :: emit_evsplatfida_r_r_r
|
|
inst_evcmpgtdu :: inst_evcmpgtdu_r_r_r
|
|
emit_evcmpgtdu :: emit_evcmpgtdu_r_r_r
|
|
inst_evcmpgtds :: inst_evcmpgtds_r_r_r
|
|
emit_evcmpgtds :: emit_evcmpgtds_r_r_r
|
|
inst_evcmpltdu :: inst_evcmpltdu_r_r_r
|
|
emit_evcmpltdu :: emit_evcmpltdu_r_r_r
|
|
inst_evcmpltds :: inst_evcmpltds_r_r_r
|
|
emit_evcmpltds :: emit_evcmpltds_r_r_r
|
|
inst_evcmpeqd :: inst_evcmpeqd_r_r_r
|
|
emit_evcmpeqd :: emit_evcmpeqd_r_r_r
|
|
inst_evswapbhilo :: inst_evswapbhilo_r_r_r
|
|
emit_evswapbhilo :: emit_evswapbhilo_r_r_r
|
|
inst_evswapblohi :: inst_evswapblohi_r_r_r
|
|
emit_evswapblohi :: emit_evswapblohi_r_r_r
|
|
inst_evswaphhilo :: inst_evswaphhilo_r_r_r
|
|
emit_evswaphhilo :: emit_evswaphhilo_r_r_r
|
|
inst_evswaphlohi :: inst_evswaphlohi_r_r_r
|
|
emit_evswaphlohi :: emit_evswaphlohi_r_r_r
|
|
inst_evswaphe :: inst_evswaphe_r_r_r
|
|
emit_evswaphe :: emit_evswaphe_r_r_r
|
|
inst_evswaphhi :: inst_evswaphhi_r_r_r
|
|
emit_evswaphhi :: emit_evswaphhi_r_r_r
|
|
inst_evswaphlo :: inst_evswaphlo_r_r_r
|
|
emit_evswaphlo :: emit_evswaphlo_r_r_r
|
|
inst_evswapho :: inst_evswapho_r_r_r
|
|
emit_evswapho :: emit_evswapho_r_r_r
|
|
inst_evinsb :: inst_evinsb_r_r_r
|
|
emit_evinsb :: emit_evinsb_r_r_r
|
|
inst_evxtrb :: inst_evxtrb_r_r_r
|
|
emit_evxtrb :: emit_evxtrb_r_r_r
|
|
inst_evsplath :: inst_evsplath_r_r_r
|
|
emit_evsplath :: emit_evsplath_r_r_r
|
|
inst_evsplatb :: inst_evsplatb_r_r_r
|
|
emit_evsplatb :: emit_evsplatb_r_r_r
|
|
inst_evinsh :: inst_evinsh_r_r_r
|
|
emit_evinsh :: emit_evinsh_r_r_r
|
|
inst_evclrbe :: inst_evclrbe_r_r_r
|
|
emit_evclrbe :: emit_evclrbe_r_r_r
|
|
inst_evclrbo :: inst_evclrbo_r_r_r
|
|
emit_evclrbo :: emit_evclrbo_r_r_r
|
|
inst_evclrh :: inst_evclrh_r_r_r
|
|
emit_evclrh :: emit_evclrh_r_r_r
|
|
inst_evxtrh :: inst_evxtrh_r_r_r
|
|
emit_evxtrh :: emit_evxtrh_r_r_r
|
|
inst_evselbitm0 :: inst_evselbitm0_r_r_r
|
|
emit_evselbitm0 :: emit_evselbitm0_r_r_r
|
|
inst_evselbitm1 :: inst_evselbitm1_r_r_r
|
|
emit_evselbitm1 :: emit_evselbitm1_r_r_r
|
|
inst_evselbit :: inst_evselbit_r_r_r
|
|
emit_evselbit :: emit_evselbit_r_r_r
|
|
inst_evperm :: inst_evperm_r_r_r
|
|
emit_evperm :: emit_evperm_r_r_r
|
|
inst_evperm2 :: inst_evperm2_r_r_r
|
|
emit_evperm2 :: emit_evperm2_r_r_r
|
|
inst_evperm3 :: inst_evperm3_r_r_r
|
|
emit_evperm3 :: emit_evperm3_r_r_r
|
|
inst_evxtrd :: inst_evxtrd_r_r_r
|
|
emit_evxtrd :: emit_evxtrd_r_r_r
|
|
inst_evsrbu :: inst_evsrbu_r_r_r
|
|
emit_evsrbu :: emit_evsrbu_r_r_r
|
|
inst_evsrbs :: inst_evsrbs_r_r_r
|
|
emit_evsrbs :: emit_evsrbs_r_r_r
|
|
inst_evsrbiu :: inst_evsrbiu_r_r_r
|
|
emit_evsrbiu :: emit_evsrbiu_r_r_r
|
|
inst_evsrbis :: inst_evsrbis_r_r_r
|
|
emit_evsrbis :: emit_evsrbis_r_r_r
|
|
inst_evslb :: inst_evslb_r_r_r
|
|
emit_evslb :: emit_evslb_r_r_r
|
|
inst_evrlb :: inst_evrlb_r_r_r
|
|
emit_evrlb :: emit_evrlb_r_r_r
|
|
inst_evslbi :: inst_evslbi_r_r_r
|
|
emit_evslbi :: emit_evslbi_r_r_r
|
|
inst_evrlbi :: inst_evrlbi_r_r_r
|
|
emit_evrlbi :: emit_evrlbi_r_r_r
|
|
inst_evsrhu :: inst_evsrhu_r_r_r
|
|
emit_evsrhu :: emit_evsrhu_r_r_r
|
|
inst_evsrhs :: inst_evsrhs_r_r_r
|
|
emit_evsrhs :: emit_evsrhs_r_r_r
|
|
inst_evsrhiu :: inst_evsrhiu_r_r_r
|
|
emit_evsrhiu :: emit_evsrhiu_r_r_r
|
|
inst_evsrhis :: inst_evsrhis_r_r_r
|
|
emit_evsrhis :: emit_evsrhis_r_r_r
|
|
inst_evslh :: inst_evslh_r_r_r
|
|
emit_evslh :: emit_evslh_r_r_r
|
|
inst_evrlh :: inst_evrlh_r_r_r
|
|
emit_evrlh :: emit_evrlh_r_r_r
|
|
inst_evslhi :: inst_evslhi_r_r_r
|
|
emit_evslhi :: emit_evslhi_r_r_r
|
|
inst_evrlhi :: inst_evrlhi_r_r_r
|
|
emit_evrlhi :: emit_evrlhi_r_r_r
|
|
inst_evsru :: inst_evsru_r_r_r
|
|
emit_evsru :: emit_evsru_r_r_r
|
|
inst_evsrs :: inst_evsrs_r_r_r
|
|
emit_evsrs :: emit_evsrs_r_r_r
|
|
inst_evsriu :: inst_evsriu_r_r_r
|
|
emit_evsriu :: emit_evsriu_r_r_r
|
|
inst_evsris :: inst_evsris_r_r_r
|
|
emit_evsris :: emit_evsris_r_r_r
|
|
inst_evlvsl :: inst_evlvsl_r_r_r
|
|
emit_evlvsl :: emit_evlvsl_r_r_r
|
|
inst_evlvsr :: inst_evlvsr_r_r_r
|
|
emit_evlvsr :: emit_evlvsr_r_r_r
|
|
inst_evsroiu :: inst_evsroiu_r_r_r
|
|
emit_evsroiu :: emit_evsroiu_r_r_r
|
|
inst_evsrois :: inst_evsrois_r_r_r
|
|
emit_evsrois :: emit_evsrois_r_r_r
|
|
inst_evsloi :: inst_evsloi_r_r_r
|
|
emit_evsloi :: emit_evsloi_r_r_r
|
|
inst_evldbx :: inst_evldbx_r_r_r
|
|
emit_evldbx :: emit_evldbx_r_r_r
|
|
inst_evldb :: inst_evldb_r_r_r
|
|
emit_evldb :: emit_evldb_r_r_r
|
|
inst_evlhhsplathx :: inst_evlhhsplathx_r_r_r
|
|
emit_evlhhsplathx :: emit_evlhhsplathx_r_r_r
|
|
inst_evlhhsplath :: inst_evlhhsplath_r_r_r
|
|
emit_evlhhsplath :: emit_evlhhsplath_r_r_r
|
|
inst_evlwbsplatwx :: inst_evlwbsplatwx_r_r_r
|
|
emit_evlwbsplatwx :: emit_evlwbsplatwx_r_r_r
|
|
inst_evlwbsplatw :: inst_evlwbsplatw_r_r_r
|
|
emit_evlwbsplatw :: emit_evlwbsplatw_r_r_r
|
|
inst_evlwhsplatwx :: inst_evlwhsplatwx_r_r_r
|
|
emit_evlwhsplatwx :: emit_evlwhsplatwx_r_r_r
|
|
inst_evlwhsplatw :: inst_evlwhsplatw_r_r_r
|
|
emit_evlwhsplatw :: emit_evlwhsplatw_r_r_r
|
|
inst_evlbbsplatbx :: inst_evlbbsplatbx_r_r_r
|
|
emit_evlbbsplatbx :: emit_evlbbsplatbx_r_r_r
|
|
inst_evlbbsplatb :: inst_evlbbsplatb_r_r_r
|
|
emit_evlbbsplatb :: emit_evlbbsplatb_r_r_r
|
|
inst_evstdbx :: inst_evstdbx_r_r_r
|
|
emit_evstdbx :: emit_evstdbx_r_r_r
|
|
inst_evstdb :: inst_evstdb_r_r_r
|
|
emit_evstdb :: emit_evstdb_r_r_r
|
|
inst_evlwbex :: inst_evlwbex_r_r_r
|
|
emit_evlwbex :: emit_evlwbex_r_r_r
|
|
inst_evlwbe :: inst_evlwbe_r_r_r
|
|
emit_evlwbe :: emit_evlwbe_r_r_r
|
|
inst_evlwboux :: inst_evlwboux_r_r_r
|
|
emit_evlwboux :: emit_evlwboux_r_r_r
|
|
inst_evlwbou :: inst_evlwbou_r_r_r
|
|
emit_evlwbou :: emit_evlwbou_r_r_r
|
|
inst_evlwbosx :: inst_evlwbosx_r_r_r
|
|
emit_evlwbosx :: emit_evlwbosx_r_r_r
|
|
inst_evlwbos :: inst_evlwbos_r_r_r
|
|
emit_evlwbos :: emit_evlwbos_r_r_r
|
|
inst_evstwbex :: inst_evstwbex_r_r_r
|
|
emit_evstwbex :: emit_evstwbex_r_r_r
|
|
inst_evstwbe :: inst_evstwbe_r_r_r
|
|
emit_evstwbe :: emit_evstwbe_r_r_r
|
|
inst_evstwbox :: inst_evstwbox_r_r_r
|
|
emit_evstwbox :: emit_evstwbox_r_r_r
|
|
inst_evstwbo :: inst_evstwbo_r_r_r
|
|
emit_evstwbo :: emit_evstwbo_r_r_r
|
|
inst_evstwbx :: inst_evstwbx_r_r_r
|
|
emit_evstwbx :: emit_evstwbx_r_r_r
|
|
inst_evstwb :: inst_evstwb_r_r_r
|
|
emit_evstwb :: emit_evstwb_r_r_r
|
|
inst_evsthbx :: inst_evsthbx_r_r_r
|
|
emit_evsthbx :: emit_evsthbx_r_r_r
|
|
inst_evsthb :: inst_evsthb_r_r_r
|
|
emit_evsthb :: emit_evsthb_r_r_r
|
|
inst_evlddmx :: inst_evlddmx_r_r_r
|
|
emit_evlddmx :: emit_evlddmx_r_r_r
|
|
inst_evlddu :: inst_evlddu_r_r_r
|
|
emit_evlddu :: emit_evlddu_r_r_r
|
|
inst_evldwmx :: inst_evldwmx_r_r_r
|
|
emit_evldwmx :: emit_evldwmx_r_r_r
|
|
inst_evldwu :: inst_evldwu_r_r_r
|
|
emit_evldwu :: emit_evldwu_r_r_r
|
|
inst_evldhmx :: inst_evldhmx_r_r_r
|
|
emit_evldhmx :: emit_evldhmx_r_r_r
|
|
inst_evldhu :: inst_evldhu_r_r_r
|
|
emit_evldhu :: emit_evldhu_r_r_r
|
|
inst_evldbmx :: inst_evldbmx_r_r_r
|
|
emit_evldbmx :: emit_evldbmx_r_r_r
|
|
inst_evldbu :: inst_evldbu_r_r_r
|
|
emit_evldbu :: emit_evldbu_r_r_r
|
|
inst_evlhhesplatmx :: inst_evlhhesplatmx_r_r_r
|
|
emit_evlhhesplatmx :: emit_evlhhesplatmx_r_r_r
|
|
inst_evlhhesplatu :: inst_evlhhesplatu_r_r_r
|
|
emit_evlhhesplatu :: emit_evlhhesplatu_r_r_r
|
|
inst_evlhhsplathmx :: inst_evlhhsplathmx_r_r_r
|
|
emit_evlhhsplathmx :: emit_evlhhsplathmx_r_r_r
|
|
inst_evlhhsplathu :: inst_evlhhsplathu_r_r_r
|
|
emit_evlhhsplathu :: emit_evlhhsplathu_r_r_r
|
|
inst_evlhhousplatmx :: inst_evlhhousplatmx_r_r_r
|
|
emit_evlhhousplatmx :: emit_evlhhousplatmx_r_r_r
|
|
inst_evlhhousplatu :: inst_evlhhousplatu_r_r_r
|
|
emit_evlhhousplatu :: emit_evlhhousplatu_r_r_r
|
|
inst_evlhhossplatmx :: inst_evlhhossplatmx_r_r_r
|
|
emit_evlhhossplatmx :: emit_evlhhossplatmx_r_r_r
|
|
inst_evlhhossplatu :: inst_evlhhossplatu_r_r_r
|
|
emit_evlhhossplatu :: emit_evlhhossplatu_r_r_r
|
|
inst_evlwhemx :: inst_evlwhemx_r_r_r
|
|
emit_evlwhemx :: emit_evlwhemx_r_r_r
|
|
inst_evlwheu :: inst_evlwheu_r_r_r
|
|
emit_evlwheu :: emit_evlwheu_r_r_r
|
|
inst_evlwbsplatwmx :: inst_evlwbsplatwmx_r_r_r
|
|
emit_evlwbsplatwmx :: emit_evlwbsplatwmx_r_r_r
|
|
inst_evlwbsplatwu :: inst_evlwbsplatwu_r_r_r
|
|
emit_evlwbsplatwu :: emit_evlwbsplatwu_r_r_r
|
|
inst_evlwhoumx :: inst_evlwhoumx_r_r_r
|
|
emit_evlwhoumx :: emit_evlwhoumx_r_r_r
|
|
inst_evlwhouu :: inst_evlwhouu_r_r_r
|
|
emit_evlwhouu :: emit_evlwhouu_r_r_r
|
|
inst_evlwhosmx :: inst_evlwhosmx_r_r_r
|
|
emit_evlwhosmx :: emit_evlwhosmx_r_r_r
|
|
inst_evlwhosu :: inst_evlwhosu_r_r_r
|
|
emit_evlwhosu :: emit_evlwhosu_r_r_r
|
|
inst_evlwwsplatmx :: inst_evlwwsplatmx_r_r_r
|
|
emit_evlwwsplatmx :: emit_evlwwsplatmx_r_r_r
|
|
inst_evlwwsplatu :: inst_evlwwsplatu_r_r_r
|
|
emit_evlwwsplatu :: emit_evlwwsplatu_r_r_r
|
|
inst_evlwhsplatwmx :: inst_evlwhsplatwmx_r_r_r
|
|
emit_evlwhsplatwmx :: emit_evlwhsplatwmx_r_r_r
|
|
inst_evlwhsplatwu :: inst_evlwhsplatwu_r_r_r
|
|
emit_evlwhsplatwu :: emit_evlwhsplatwu_r_r_r
|
|
inst_evlwhsplatmx :: inst_evlwhsplatmx_r_r_r
|
|
emit_evlwhsplatmx :: emit_evlwhsplatmx_r_r_r
|
|
inst_evlwhsplatu :: inst_evlwhsplatu_r_r_r
|
|
emit_evlwhsplatu :: emit_evlwhsplatu_r_r_r
|
|
inst_evlbbsplatbmx :: inst_evlbbsplatbmx_r_r_r
|
|
emit_evlbbsplatbmx :: emit_evlbbsplatbmx_r_r_r
|
|
inst_evlbbsplatbu :: inst_evlbbsplatbu_r_r_r
|
|
emit_evlbbsplatbu :: emit_evlbbsplatbu_r_r_r
|
|
inst_evstddmx :: inst_evstddmx_r_r_r
|
|
emit_evstddmx :: emit_evstddmx_r_r_r
|
|
inst_evstddu :: inst_evstddu_r_r_r
|
|
emit_evstddu :: emit_evstddu_r_r_r
|
|
inst_evstdwmx :: inst_evstdwmx_r_r_r
|
|
emit_evstdwmx :: emit_evstdwmx_r_r_r
|
|
inst_evstdwu :: inst_evstdwu_r_r_r
|
|
emit_evstdwu :: emit_evstdwu_r_r_r
|
|
inst_evstdhmx :: inst_evstdhmx_r_r_r
|
|
emit_evstdhmx :: emit_evstdhmx_r_r_r
|
|
inst_evstdhu :: inst_evstdhu_r_r_r
|
|
emit_evstdhu :: emit_evstdhu_r_r_r
|
|
inst_evstdbmx :: inst_evstdbmx_r_r_r
|
|
emit_evstdbmx :: emit_evstdbmx_r_r_r
|
|
inst_evstdbu :: inst_evstdbu_r_r_r
|
|
emit_evstdbu :: emit_evstdbu_r_r_r
|
|
inst_evlwbemx :: inst_evlwbemx_r_r_r
|
|
emit_evlwbemx :: emit_evlwbemx_r_r_r
|
|
inst_evlwbeu :: inst_evlwbeu_r_r_r
|
|
emit_evlwbeu :: emit_evlwbeu_r_r_r
|
|
inst_evlwboumx :: inst_evlwboumx_r_r_r
|
|
emit_evlwboumx :: emit_evlwboumx_r_r_r
|
|
inst_evlwbouu :: inst_evlwbouu_r_r_r
|
|
emit_evlwbouu :: emit_evlwbouu_r_r_r
|
|
inst_evlwbosmx :: inst_evlwbosmx_r_r_r
|
|
emit_evlwbosmx :: emit_evlwbosmx_r_r_r
|
|
inst_evlwbosu :: inst_evlwbosu_r_r_r
|
|
emit_evlwbosu :: emit_evlwbosu_r_r_r
|
|
inst_evstwhemx :: inst_evstwhemx_r_r_r
|
|
emit_evstwhemx :: emit_evstwhemx_r_r_r
|
|
inst_evstwheu :: inst_evstwheu_r_r_r
|
|
emit_evstwheu :: emit_evstwheu_r_r_r
|
|
inst_evstwbemx :: inst_evstwbemx_r_r_r
|
|
emit_evstwbemx :: emit_evstwbemx_r_r_r
|
|
inst_evstwbeu :: inst_evstwbeu_r_r_r
|
|
emit_evstwbeu :: emit_evstwbeu_r_r_r
|
|
inst_evstwhomx :: inst_evstwhomx_r_r_r
|
|
emit_evstwhomx :: emit_evstwhomx_r_r_r
|
|
inst_evstwhou :: inst_evstwhou_r_r_r
|
|
emit_evstwhou :: emit_evstwhou_r_r_r
|
|
inst_evstwbomx :: inst_evstwbomx_r_r_r
|
|
emit_evstwbomx :: emit_evstwbomx_r_r_r
|
|
inst_evstwbou :: inst_evstwbou_r_r_r
|
|
emit_evstwbou :: emit_evstwbou_r_r_r
|
|
inst_evstwwemx :: inst_evstwwemx_r_r_r
|
|
emit_evstwwemx :: emit_evstwwemx_r_r_r
|
|
inst_evstwweu :: inst_evstwweu_r_r_r
|
|
emit_evstwweu :: emit_evstwweu_r_r_r
|
|
inst_evstwbmx :: inst_evstwbmx_r_r_r
|
|
emit_evstwbmx :: emit_evstwbmx_r_r_r
|
|
inst_evstwbu :: inst_evstwbu_r_r_r
|
|
emit_evstwbu :: emit_evstwbu_r_r_r
|
|
inst_evstwwomx :: inst_evstwwomx_r_r_r
|
|
emit_evstwwomx :: emit_evstwwomx_r_r_r
|
|
inst_evstwwou :: inst_evstwwou_r_r_r
|
|
emit_evstwwou :: emit_evstwwou_r_r_r
|
|
inst_evsthbmx :: inst_evsthbmx_r_r_r
|
|
emit_evsthbmx :: emit_evsthbmx_r_r_r
|
|
inst_evsthbu :: inst_evsthbu_r_r_r
|
|
emit_evsthbu :: emit_evsthbu_r_r_r
|
|
inst_evmhusi :: inst_evmhusi_r_r_r
|
|
emit_evmhusi :: emit_evmhusi_r_r_r
|
|
inst_evmhssi :: inst_evmhssi_r_r_r
|
|
emit_evmhssi :: emit_evmhssi_r_r_r
|
|
inst_evmhsusi :: inst_evmhsusi_r_r_r
|
|
emit_evmhsusi :: emit_evmhsusi_r_r_r
|
|
inst_evmhssf :: inst_evmhssf_r_r_r
|
|
emit_evmhssf :: emit_evmhssf_r_r_r
|
|
inst_evmhumi :: inst_evmhumi_r_r_r
|
|
emit_evmhumi :: emit_evmhumi_r_r_r
|
|
inst_evmhssfr :: inst_evmhssfr_r_r_r
|
|
emit_evmhssfr :: emit_evmhssfr_r_r_r
|
|
inst_evmhesumi :: inst_evmhesumi_r_r_r
|
|
emit_evmhesumi :: emit_evmhesumi_r_r_r
|
|
inst_evmhosumi :: inst_evmhosumi_r_r_r
|
|
emit_evmhosumi :: emit_evmhosumi_r_r_r
|
|
inst_evmbeumi :: inst_evmbeumi_r_r_r
|
|
emit_evmbeumi :: emit_evmbeumi_r_r_r
|
|
inst_evmbesmi :: inst_evmbesmi_r_r_r
|
|
emit_evmbesmi :: emit_evmbesmi_r_r_r
|
|
inst_evmbesumi :: inst_evmbesumi_r_r_r
|
|
emit_evmbesumi :: emit_evmbesumi_r_r_r
|
|
inst_evmboumi :: inst_evmboumi_r_r_r
|
|
emit_evmboumi :: emit_evmboumi_r_r_r
|
|
inst_evmbosmi :: inst_evmbosmi_r_r_r
|
|
emit_evmbosmi :: emit_evmbosmi_r_r_r
|
|
inst_evmbosumi :: inst_evmbosumi_r_r_r
|
|
emit_evmbosumi :: emit_evmbosumi_r_r_r
|
|
inst_evmhesumia :: inst_evmhesumia_r_r_r
|
|
emit_evmhesumia :: emit_evmhesumia_r_r_r
|
|
inst_evmhosumia :: inst_evmhosumia_r_r_r
|
|
emit_evmhosumia :: emit_evmhosumia_r_r_r
|
|
inst_evmbeumia :: inst_evmbeumia_r_r_r
|
|
emit_evmbeumia :: emit_evmbeumia_r_r_r
|
|
inst_evmbesmia :: inst_evmbesmia_r_r_r
|
|
emit_evmbesmia :: emit_evmbesmia_r_r_r
|
|
inst_evmbesumia :: inst_evmbesumia_r_r_r
|
|
emit_evmbesumia :: emit_evmbesumia_r_r_r
|
|
inst_evmboumia :: inst_evmboumia_r_r_r
|
|
emit_evmboumia :: emit_evmboumia_r_r_r
|
|
inst_evmbosmia :: inst_evmbosmia_r_r_r
|
|
emit_evmbosmia :: emit_evmbosmia_r_r_r
|
|
inst_evmbosumia :: inst_evmbosumia_r_r_r
|
|
emit_evmbosumia :: emit_evmbosumia_r_r_r
|
|
inst_evmwusiw :: inst_evmwusiw_r_r_r
|
|
emit_evmwusiw :: emit_evmwusiw_r_r_r
|
|
inst_evmwssiw :: inst_evmwssiw_r_r_r
|
|
emit_evmwssiw :: emit_evmwssiw_r_r_r
|
|
inst_evmwhssfr :: inst_evmwhssfr_r_r_r
|
|
emit_evmwhssfr :: emit_evmwhssfr_r_r_r
|
|
inst_evmwehgsmfr :: inst_evmwehgsmfr_r_r_r
|
|
emit_evmwehgsmfr :: emit_evmwehgsmfr_r_r_r
|
|
inst_evmwehgsmf :: inst_evmwehgsmf_r_r_r
|
|
emit_evmwehgsmf :: emit_evmwehgsmf_r_r_r
|
|
inst_evmwohgsmfr :: inst_evmwohgsmfr_r_r_r
|
|
emit_evmwohgsmfr :: emit_evmwohgsmfr_r_r_r
|
|
inst_evmwohgsmf :: inst_evmwohgsmf_r_r_r
|
|
emit_evmwohgsmf :: emit_evmwohgsmf_r_r_r
|
|
inst_evmwhssfra :: inst_evmwhssfra_r_r_r
|
|
emit_evmwhssfra :: emit_evmwhssfra_r_r_r
|
|
inst_evmwehgsmfra :: inst_evmwehgsmfra_r_r_r
|
|
emit_evmwehgsmfra :: emit_evmwehgsmfra_r_r_r
|
|
inst_evmwehgsmfa :: inst_evmwehgsmfa_r_r_r
|
|
emit_evmwehgsmfa :: emit_evmwehgsmfa_r_r_r
|
|
inst_evmwohgsmfra :: inst_evmwohgsmfra_r_r_r
|
|
emit_evmwohgsmfra :: emit_evmwohgsmfra_r_r_r
|
|
inst_evmwohgsmfa :: inst_evmwohgsmfa_r_r_r
|
|
emit_evmwohgsmfa :: emit_evmwohgsmfa_r_r_r
|
|
inst_evaddusiaa :: inst_evaddusiaa_r_r_r
|
|
emit_evaddusiaa :: emit_evaddusiaa_r_r_r
|
|
inst_evaddssiaa :: inst_evaddssiaa_r_r_r
|
|
emit_evaddssiaa :: emit_evaddssiaa_r_r_r
|
|
inst_evsubfusiaa :: inst_evsubfusiaa_r_r_r
|
|
emit_evsubfusiaa :: emit_evsubfusiaa_r_r_r
|
|
inst_evsubfssiaa :: inst_evsubfssiaa_r_r_r
|
|
emit_evsubfssiaa :: emit_evsubfssiaa_r_r_r
|
|
inst_evaddsmiaa :: inst_evaddsmiaa_r_r_r
|
|
emit_evaddsmiaa :: emit_evaddsmiaa_r_r_r
|
|
inst_evsubfsmiaa :: inst_evsubfsmiaa_r_r_r
|
|
emit_evsubfsmiaa :: emit_evsubfsmiaa_r_r_r
|
|
inst_evaddh :: inst_evaddh_r_r_r
|
|
emit_evaddh :: emit_evaddh_r_r_r
|
|
inst_evaddhss :: inst_evaddhss_r_r_r
|
|
emit_evaddhss :: emit_evaddhss_r_r_r
|
|
inst_evsubfh :: inst_evsubfh_r_r_r
|
|
emit_evsubfh :: emit_evsubfh_r_r_r
|
|
inst_evsubfhss :: inst_evsubfhss_r_r_r
|
|
emit_evsubfhss :: emit_evsubfhss_r_r_r
|
|
inst_evaddhx :: inst_evaddhx_r_r_r
|
|
emit_evaddhx :: emit_evaddhx_r_r_r
|
|
inst_evaddhxss :: inst_evaddhxss_r_r_r
|
|
emit_evaddhxss :: emit_evaddhxss_r_r_r
|
|
inst_evsubfhx :: inst_evsubfhx_r_r_r
|
|
emit_evsubfhx :: emit_evsubfhx_r_r_r
|
|
inst_evsubfhxss :: inst_evsubfhxss_r_r_r
|
|
emit_evsubfhxss :: emit_evsubfhxss_r_r_r
|
|
inst_evaddd :: inst_evaddd_r_r_r
|
|
emit_evaddd :: emit_evaddd_r_r_r
|
|
inst_evadddss :: inst_evadddss_r_r_r
|
|
emit_evadddss :: emit_evadddss_r_r_r
|
|
inst_evsubfd :: inst_evsubfd_r_r_r
|
|
emit_evsubfd :: emit_evsubfd_r_r_r
|
|
inst_evsubfdss :: inst_evsubfdss_r_r_r
|
|
emit_evsubfdss :: emit_evsubfdss_r_r_r
|
|
inst_evaddb :: inst_evaddb_r_r_r
|
|
emit_evaddb :: emit_evaddb_r_r_r
|
|
inst_evaddbss :: inst_evaddbss_r_r_r
|
|
emit_evaddbss :: emit_evaddbss_r_r_r
|
|
inst_evsubfb :: inst_evsubfb_r_r_r
|
|
emit_evsubfb :: emit_evsubfb_r_r_r
|
|
inst_evsubfbss :: inst_evsubfbss_r_r_r
|
|
emit_evsubfbss :: emit_evsubfbss_r_r_r
|
|
inst_evaddsubfh :: inst_evaddsubfh_r_r_r
|
|
emit_evaddsubfh :: emit_evaddsubfh_r_r_r
|
|
inst_evaddsubfhss :: inst_evaddsubfhss_r_r_r
|
|
emit_evaddsubfhss :: emit_evaddsubfhss_r_r_r
|
|
inst_evsubfaddh :: inst_evsubfaddh_r_r_r
|
|
emit_evsubfaddh :: emit_evsubfaddh_r_r_r
|
|
inst_evsubfaddhss :: inst_evsubfaddhss_r_r_r
|
|
emit_evsubfaddhss :: emit_evsubfaddhss_r_r_r
|
|
inst_evaddsubfhx :: inst_evaddsubfhx_r_r_r
|
|
emit_evaddsubfhx :: emit_evaddsubfhx_r_r_r
|
|
inst_evaddsubfhxss :: inst_evaddsubfhxss_r_r_r
|
|
emit_evaddsubfhxss :: emit_evaddsubfhxss_r_r_r
|
|
inst_evsubfaddhx :: inst_evsubfaddhx_r_r_r
|
|
emit_evsubfaddhx :: emit_evsubfaddhx_r_r_r
|
|
inst_evsubfaddhxss :: inst_evsubfaddhxss_r_r_r
|
|
emit_evsubfaddhxss :: emit_evsubfaddhxss_r_r_r
|
|
inst_evadddus :: inst_evadddus_r_r_r
|
|
emit_evadddus :: emit_evadddus_r_r_r
|
|
inst_evaddbus :: inst_evaddbus_r_r_r
|
|
emit_evaddbus :: emit_evaddbus_r_r_r
|
|
inst_evsubfdus :: inst_evsubfdus_r_r_r
|
|
emit_evsubfdus :: emit_evsubfdus_r_r_r
|
|
inst_evsubfbus :: inst_evsubfbus_r_r_r
|
|
emit_evsubfbus :: emit_evsubfbus_r_r_r
|
|
inst_evaddwus :: inst_evaddwus_r_r_r
|
|
emit_evaddwus :: emit_evaddwus_r_r_r
|
|
inst_evaddwxus :: inst_evaddwxus_r_r_r
|
|
emit_evaddwxus :: emit_evaddwxus_r_r_r
|
|
inst_evsubfwus :: inst_evsubfwus_r_r_r
|
|
emit_evsubfwus :: emit_evsubfwus_r_r_r
|
|
inst_evsubfwxus :: inst_evsubfwxus_r_r_r
|
|
emit_evsubfwxus :: emit_evsubfwxus_r_r_r
|
|
inst_evadd2subf2h :: inst_evadd2subf2h_r_r_r
|
|
emit_evadd2subf2h :: emit_evadd2subf2h_r_r_r
|
|
inst_evadd2subf2hss :: inst_evadd2subf2hss_r_r_r
|
|
emit_evadd2subf2hss :: emit_evadd2subf2hss_r_r_r
|
|
inst_evsubf2add2h :: inst_evsubf2add2h_r_r_r
|
|
emit_evsubf2add2h :: emit_evsubf2add2h_r_r_r
|
|
inst_evsubf2add2hss :: inst_evsubf2add2hss_r_r_r
|
|
emit_evsubf2add2hss :: emit_evsubf2add2hss_r_r_r
|
|
inst_evaddhus :: inst_evaddhus_r_r_r
|
|
emit_evaddhus :: emit_evaddhus_r_r_r
|
|
inst_evaddhxus :: inst_evaddhxus_r_r_r
|
|
emit_evaddhxus :: emit_evaddhxus_r_r_r
|
|
inst_evsubfhus :: inst_evsubfhus_r_r_r
|
|
emit_evsubfhus :: emit_evsubfhus_r_r_r
|
|
inst_evsubfhxus :: inst_evsubfhxus_r_r_r
|
|
emit_evsubfhxus :: emit_evsubfhxus_r_r_r
|
|
inst_evaddwss :: inst_evaddwss_r_r_r
|
|
emit_evaddwss :: emit_evaddwss_r_r_r
|
|
inst_evsubfwss :: inst_evsubfwss_r_r_r
|
|
emit_evsubfwss :: emit_evsubfwss_r_r_r
|
|
inst_evaddwx :: inst_evaddwx_r_r_r
|
|
emit_evaddwx :: emit_evaddwx_r_r_r
|
|
inst_evaddwxss :: inst_evaddwxss_r_r_r
|
|
emit_evaddwxss :: emit_evaddwxss_r_r_r
|
|
inst_evsubfwx :: inst_evsubfwx_r_r_r
|
|
emit_evsubfwx :: emit_evsubfwx_r_r_r
|
|
inst_evsubfwxss :: inst_evsubfwxss_r_r_r
|
|
emit_evsubfwxss :: emit_evsubfwxss_r_r_r
|
|
inst_evaddsubfw :: inst_evaddsubfw_r_r_r
|
|
emit_evaddsubfw :: emit_evaddsubfw_r_r_r
|
|
inst_evaddsubfwss :: inst_evaddsubfwss_r_r_r
|
|
emit_evaddsubfwss :: emit_evaddsubfwss_r_r_r
|
|
inst_evsubfaddw :: inst_evsubfaddw_r_r_r
|
|
emit_evsubfaddw :: emit_evsubfaddw_r_r_r
|
|
inst_evsubfaddwss :: inst_evsubfaddwss_r_r_r
|
|
emit_evsubfaddwss :: emit_evsubfaddwss_r_r_r
|
|
inst_evaddsubfwx :: inst_evaddsubfwx_r_r_r
|
|
emit_evaddsubfwx :: emit_evaddsubfwx_r_r_r
|
|
inst_evaddsubfwxss :: inst_evaddsubfwxss_r_r_r
|
|
emit_evaddsubfwxss :: emit_evaddsubfwxss_r_r_r
|
|
inst_evsubfaddwx :: inst_evsubfaddwx_r_r_r
|
|
emit_evsubfaddwx :: emit_evsubfaddwx_r_r_r
|
|
inst_evsubfaddwxss :: inst_evsubfaddwxss_r_r_r
|
|
emit_evsubfaddwxss :: emit_evsubfaddwxss_r_r_r
|
|
inst_evmar :: inst_evmar_r_r_r
|
|
emit_evmar :: emit_evmar_r_r_r
|
|
inst_evsumwu :: inst_evsumwu_r_r_r
|
|
emit_evsumwu :: emit_evsumwu_r_r_r
|
|
inst_evsumws :: inst_evsumws_r_r_r
|
|
emit_evsumws :: emit_evsumws_r_r_r
|
|
inst_evsum4bu :: inst_evsum4bu_r_r_r
|
|
emit_evsum4bu :: emit_evsum4bu_r_r_r
|
|
inst_evsum4bs :: inst_evsum4bs_r_r_r
|
|
emit_evsum4bs :: emit_evsum4bs_r_r_r
|
|
inst_evsum2hu :: inst_evsum2hu_r_r_r
|
|
emit_evsum2hu :: emit_evsum2hu_r_r_r
|
|
inst_evsum2hs :: inst_evsum2hs_r_r_r
|
|
emit_evsum2hs :: emit_evsum2hs_r_r_r
|
|
inst_evdiff2his :: inst_evdiff2his_r_r_r
|
|
emit_evdiff2his :: emit_evdiff2his_r_r_r
|
|
inst_evsum2his :: inst_evsum2his_r_r_r
|
|
emit_evsum2his :: emit_evsum2his_r_r_r
|
|
inst_evsumwua :: inst_evsumwua_r_r_r
|
|
emit_evsumwua :: emit_evsumwua_r_r_r
|
|
inst_evsumwsa :: inst_evsumwsa_r_r_r
|
|
emit_evsumwsa :: emit_evsumwsa_r_r_r
|
|
inst_evsum4bua :: inst_evsum4bua_r_r_r
|
|
emit_evsum4bua :: emit_evsum4bua_r_r_r
|
|
inst_evsum4bsa :: inst_evsum4bsa_r_r_r
|
|
emit_evsum4bsa :: emit_evsum4bsa_r_r_r
|
|
inst_evsum2hua :: inst_evsum2hua_r_r_r
|
|
emit_evsum2hua :: emit_evsum2hua_r_r_r
|
|
inst_evsum2hsa :: inst_evsum2hsa_r_r_r
|
|
emit_evsum2hsa :: emit_evsum2hsa_r_r_r
|
|
inst_evdiff2hisa :: inst_evdiff2hisa_r_r_r
|
|
emit_evdiff2hisa :: emit_evdiff2hisa_r_r_r
|
|
inst_evsum2hisa :: inst_evsum2hisa_r_r_r
|
|
emit_evsum2hisa :: emit_evsum2hisa_r_r_r
|
|
inst_evsumwuaa :: inst_evsumwuaa_r_r_r
|
|
emit_evsumwuaa :: emit_evsumwuaa_r_r_r
|
|
inst_evsumwsaa :: inst_evsumwsaa_r_r_r
|
|
emit_evsumwsaa :: emit_evsumwsaa_r_r_r
|
|
inst_evsum4buaaw :: inst_evsum4buaaw_r_r_r
|
|
emit_evsum4buaaw :: emit_evsum4buaaw_r_r_r
|
|
inst_evsum4bsaaw :: inst_evsum4bsaaw_r_r_r
|
|
emit_evsum4bsaaw :: emit_evsum4bsaaw_r_r_r
|
|
inst_evsum2huaaw :: inst_evsum2huaaw_r_r_r
|
|
emit_evsum2huaaw :: emit_evsum2huaaw_r_r_r
|
|
inst_evsum2hsaaw :: inst_evsum2hsaaw_r_r_r
|
|
emit_evsum2hsaaw :: emit_evsum2hsaaw_r_r_r
|
|
inst_evdiff2hisaaw :: inst_evdiff2hisaaw_r_r_r
|
|
emit_evdiff2hisaaw :: emit_evdiff2hisaaw_r_r_r
|
|
inst_evsum2hisaaw :: inst_evsum2hisaaw_r_r_r
|
|
emit_evsum2hisaaw :: emit_evsum2hisaaw_r_r_r
|
|
inst_evdivwsf :: inst_evdivwsf_r_r_r
|
|
emit_evdivwsf :: emit_evdivwsf_r_r_r
|
|
inst_evdivwuf :: inst_evdivwuf_r_r_r
|
|
emit_evdivwuf :: emit_evdivwuf_r_r_r
|
|
inst_evdivs :: inst_evdivs_r_r_r
|
|
emit_evdivs :: emit_evdivs_r_r_r
|
|
inst_evdivu :: inst_evdivu_r_r_r
|
|
emit_evdivu :: emit_evdivu_r_r_r
|
|
inst_evaddwegsi :: inst_evaddwegsi_r_r_r
|
|
emit_evaddwegsi :: emit_evaddwegsi_r_r_r
|
|
inst_evaddwegsf :: inst_evaddwegsf_r_r_r
|
|
emit_evaddwegsf :: emit_evaddwegsf_r_r_r
|
|
inst_evsubfwegsi :: inst_evsubfwegsi_r_r_r
|
|
emit_evsubfwegsi :: emit_evsubfwegsi_r_r_r
|
|
inst_evsubfwegsf :: inst_evsubfwegsf_r_r_r
|
|
emit_evsubfwegsf :: emit_evsubfwegsf_r_r_r
|
|
inst_evaddwogsi :: inst_evaddwogsi_r_r_r
|
|
emit_evaddwogsi :: emit_evaddwogsi_r_r_r
|
|
inst_evaddwogsf :: inst_evaddwogsf_r_r_r
|
|
emit_evaddwogsf :: emit_evaddwogsf_r_r_r
|
|
inst_evsubfwogsi :: inst_evsubfwogsi_r_r_r
|
|
emit_evsubfwogsi :: emit_evsubfwogsi_r_r_r
|
|
inst_evsubfwogsf :: inst_evsubfwogsf_r_r_r
|
|
emit_evsubfwogsf :: emit_evsubfwogsf_r_r_r
|
|
inst_evaddhhiuw :: inst_evaddhhiuw_r_r_r
|
|
emit_evaddhhiuw :: emit_evaddhhiuw_r_r_r
|
|
inst_evaddhhisw :: inst_evaddhhisw_r_r_r
|
|
emit_evaddhhisw :: emit_evaddhhisw_r_r_r
|
|
inst_evsubfhhiuw :: inst_evsubfhhiuw_r_r_r
|
|
emit_evsubfhhiuw :: emit_evsubfhhiuw_r_r_r
|
|
inst_evsubfhhisw :: inst_evsubfhhisw_r_r_r
|
|
emit_evsubfhhisw :: emit_evsubfhhisw_r_r_r
|
|
inst_evaddhlouw :: inst_evaddhlouw_r_r_r
|
|
emit_evaddhlouw :: emit_evaddhlouw_r_r_r
|
|
inst_evaddhlosw :: inst_evaddhlosw_r_r_r
|
|
emit_evaddhlosw :: emit_evaddhlosw_r_r_r
|
|
inst_evsubfhlouw :: inst_evsubfhlouw_r_r_r
|
|
emit_evsubfhlouw :: emit_evsubfhlouw_r_r_r
|
|
inst_evsubfhlosw :: inst_evsubfhlosw_r_r_r
|
|
emit_evsubfhlosw :: emit_evsubfhlosw_r_r_r
|
|
inst_evmhesusiaaw :: inst_evmhesusiaaw_r_r_r
|
|
emit_evmhesusiaaw :: emit_evmhesusiaaw_r_r_r
|
|
inst_evmhosusiaaw :: inst_evmhosusiaaw_r_r_r
|
|
emit_evmhosusiaaw :: emit_evmhosusiaaw_r_r_r
|
|
inst_evmhesumiaaw :: inst_evmhesumiaaw_r_r_r
|
|
emit_evmhesumiaaw :: emit_evmhesumiaaw_r_r_r
|
|
inst_evmhosumiaaw :: inst_evmhosumiaaw_r_r_r
|
|
emit_evmhosumiaaw :: emit_evmhosumiaaw_r_r_r
|
|
inst_evmbeusiaah :: inst_evmbeusiaah_r_r_r
|
|
emit_evmbeusiaah :: emit_evmbeusiaah_r_r_r
|
|
inst_evmbessiaah :: inst_evmbessiaah_r_r_r
|
|
emit_evmbessiaah :: emit_evmbessiaah_r_r_r
|
|
inst_evmbesusiaah :: inst_evmbesusiaah_r_r_r
|
|
emit_evmbesusiaah :: emit_evmbesusiaah_r_r_r
|
|
inst_evmbousiaah :: inst_evmbousiaah_r_r_r
|
|
emit_evmbousiaah :: emit_evmbousiaah_r_r_r
|
|
inst_evmbossiaah :: inst_evmbossiaah_r_r_r
|
|
emit_evmbossiaah :: emit_evmbossiaah_r_r_r
|
|
inst_evmbosusiaah :: inst_evmbosusiaah_r_r_r
|
|
emit_evmbosusiaah :: emit_evmbosusiaah_r_r_r
|
|
inst_evmbeumiaah :: inst_evmbeumiaah_r_r_r
|
|
emit_evmbeumiaah :: emit_evmbeumiaah_r_r_r
|
|
inst_evmbesmiaah :: inst_evmbesmiaah_r_r_r
|
|
emit_evmbesmiaah :: emit_evmbesmiaah_r_r_r
|
|
inst_evmbesumiaah :: inst_evmbesumiaah_r_r_r
|
|
emit_evmbesumiaah :: emit_evmbesumiaah_r_r_r
|
|
inst_evmboumiaah :: inst_evmboumiaah_r_r_r
|
|
emit_evmboumiaah :: emit_evmboumiaah_r_r_r
|
|
inst_evmbosmiaah :: inst_evmbosmiaah_r_r_r
|
|
emit_evmbosmiaah :: emit_evmbosmiaah_r_r_r
|
|
inst_evmbosumiaah :: inst_evmbosumiaah_r_r_r
|
|
emit_evmbosumiaah :: emit_evmbosumiaah_r_r_r
|
|
inst_evmwlusiaaw3 :: inst_evmwlusiaaw3_r_r_r
|
|
emit_evmwlusiaaw3 :: emit_evmwlusiaaw3_r_r_r
|
|
inst_evmwlssiaaw3 :: inst_evmwlssiaaw3_r_r_r
|
|
emit_evmwlssiaaw3 :: emit_evmwlssiaaw3_r_r_r
|
|
inst_evmwhssfraaw3 :: inst_evmwhssfraaw3_r_r_r
|
|
emit_evmwhssfraaw3 :: emit_evmwhssfraaw3_r_r_r
|
|
inst_evmwhssfaaw3 :: inst_evmwhssfaaw3_r_r_r
|
|
emit_evmwhssfaaw3 :: emit_evmwhssfaaw3_r_r_r
|
|
inst_evmwhssfraaw :: inst_evmwhssfraaw_r_r_r
|
|
emit_evmwhssfraaw :: emit_evmwhssfraaw_r_r_r
|
|
inst_evmwhssfaaw :: inst_evmwhssfaaw_r_r_r
|
|
emit_evmwhssfaaw :: emit_evmwhssfaaw_r_r_r
|
|
inst_evmwlumiaaw3 :: inst_evmwlumiaaw3_r_r_r
|
|
emit_evmwlumiaaw3 :: emit_evmwlumiaaw3_r_r_r
|
|
inst_evmwlsmiaaw3 :: inst_evmwlsmiaaw3_r_r_r
|
|
emit_evmwlsmiaaw3 :: emit_evmwlsmiaaw3_r_r_r
|
|
inst_evmwusiaa :: inst_evmwusiaa_r_r_r
|
|
emit_evmwusiaa :: emit_evmwusiaa_r_r_r
|
|
inst_evmwssiaa :: inst_evmwssiaa_r_r_r
|
|
emit_evmwssiaa :: emit_evmwssiaa_r_r_r
|
|
inst_evmwehgsmfraa :: inst_evmwehgsmfraa_r_r_r
|
|
emit_evmwehgsmfraa :: emit_evmwehgsmfraa_r_r_r
|
|
inst_evmwehgsmfaa :: inst_evmwehgsmfaa_r_r_r
|
|
emit_evmwehgsmfaa :: emit_evmwehgsmfaa_r_r_r
|
|
inst_evmwohgsmfraa :: inst_evmwohgsmfraa_r_r_r
|
|
emit_evmwohgsmfraa :: emit_evmwohgsmfraa_r_r_r
|
|
inst_evmwohgsmfaa :: inst_evmwohgsmfaa_r_r_r
|
|
emit_evmwohgsmfaa :: emit_evmwohgsmfaa_r_r_r
|
|
inst_evmhesusianw :: inst_evmhesusianw_r_r_r
|
|
emit_evmhesusianw :: emit_evmhesusianw_r_r_r
|
|
inst_evmhosusianw :: inst_evmhosusianw_r_r_r
|
|
emit_evmhosusianw :: emit_evmhosusianw_r_r_r
|
|
inst_evmhesumianw :: inst_evmhesumianw_r_r_r
|
|
emit_evmhesumianw :: emit_evmhesumianw_r_r_r
|
|
inst_evmhosumianw :: inst_evmhosumianw_r_r_r
|
|
emit_evmhosumianw :: emit_evmhosumianw_r_r_r
|
|
inst_evmbeusianh :: inst_evmbeusianh_r_r_r
|
|
emit_evmbeusianh :: emit_evmbeusianh_r_r_r
|
|
inst_evmbessianh :: inst_evmbessianh_r_r_r
|
|
emit_evmbessianh :: emit_evmbessianh_r_r_r
|
|
inst_evmbesusianh :: inst_evmbesusianh_r_r_r
|
|
emit_evmbesusianh :: emit_evmbesusianh_r_r_r
|
|
inst_evmbousianh :: inst_evmbousianh_r_r_r
|
|
emit_evmbousianh :: emit_evmbousianh_r_r_r
|
|
inst_evmbossianh :: inst_evmbossianh_r_r_r
|
|
emit_evmbossianh :: emit_evmbossianh_r_r_r
|
|
inst_evmbosusianh :: inst_evmbosusianh_r_r_r
|
|
emit_evmbosusianh :: emit_evmbosusianh_r_r_r
|
|
inst_evmbeumianh :: inst_evmbeumianh_r_r_r
|
|
emit_evmbeumianh :: emit_evmbeumianh_r_r_r
|
|
inst_evmbesmianh :: inst_evmbesmianh_r_r_r
|
|
emit_evmbesmianh :: emit_evmbesmianh_r_r_r
|
|
inst_evmbesumianh :: inst_evmbesumianh_r_r_r
|
|
emit_evmbesumianh :: emit_evmbesumianh_r_r_r
|
|
inst_evmboumianh :: inst_evmboumianh_r_r_r
|
|
emit_evmboumianh :: emit_evmboumianh_r_r_r
|
|
inst_evmbosmianh :: inst_evmbosmianh_r_r_r
|
|
emit_evmbosmianh :: emit_evmbosmianh_r_r_r
|
|
inst_evmbosumianh :: inst_evmbosumianh_r_r_r
|
|
emit_evmbosumianh :: emit_evmbosumianh_r_r_r
|
|
inst_evmwlusianw3 :: inst_evmwlusianw3_r_r_r
|
|
emit_evmwlusianw3 :: emit_evmwlusianw3_r_r_r
|
|
inst_evmwlssianw3 :: inst_evmwlssianw3_r_r_r
|
|
emit_evmwlssianw3 :: emit_evmwlssianw3_r_r_r
|
|
inst_evmwhssfranw3 :: inst_evmwhssfranw3_r_r_r
|
|
emit_evmwhssfranw3 :: emit_evmwhssfranw3_r_r_r
|
|
inst_evmwhssfanw3 :: inst_evmwhssfanw3_r_r_r
|
|
emit_evmwhssfanw3 :: emit_evmwhssfanw3_r_r_r
|
|
inst_evmwhssfranw :: inst_evmwhssfranw_r_r_r
|
|
emit_evmwhssfranw :: emit_evmwhssfranw_r_r_r
|
|
inst_evmwhssfanw :: inst_evmwhssfanw_r_r_r
|
|
emit_evmwhssfanw :: emit_evmwhssfanw_r_r_r
|
|
inst_evmwlumianw3 :: inst_evmwlumianw3_r_r_r
|
|
emit_evmwlumianw3 :: emit_evmwlumianw3_r_r_r
|
|
inst_evmwlsmianw3 :: inst_evmwlsmianw3_r_r_r
|
|
emit_evmwlsmianw3 :: emit_evmwlsmianw3_r_r_r
|
|
inst_evmwusian :: inst_evmwusian_r_r_r
|
|
emit_evmwusian :: emit_evmwusian_r_r_r
|
|
inst_evmwssian :: inst_evmwssian_r_r_r
|
|
emit_evmwssian :: emit_evmwssian_r_r_r
|
|
inst_evmwehgsmfran :: inst_evmwehgsmfran_r_r_r
|
|
emit_evmwehgsmfran :: emit_evmwehgsmfran_r_r_r
|
|
inst_evmwehgsmfan :: inst_evmwehgsmfan_r_r_r
|
|
emit_evmwehgsmfan :: emit_evmwehgsmfan_r_r_r
|
|
inst_evmwohgsmfran :: inst_evmwohgsmfran_r_r_r
|
|
emit_evmwohgsmfran :: emit_evmwohgsmfran_r_r_r
|
|
inst_evmwohgsmfan :: inst_evmwohgsmfan_r_r_r
|
|
emit_evmwohgsmfan :: emit_evmwohgsmfan_r_r_r
|
|
inst_evseteqb :: inst_evseteqb_r_r_r
|
|
emit_evseteqb :: emit_evseteqb_r_r_r
|
|
inst_evseteqh :: inst_evseteqh_r_r_r
|
|
emit_evseteqh :: emit_evseteqh_r_r_r
|
|
inst_evseteqw :: inst_evseteqw_r_r_r
|
|
emit_evseteqw :: emit_evseteqw_r_r_r
|
|
inst_evsetgthu :: inst_evsetgthu_r_r_r
|
|
emit_evsetgthu :: emit_evsetgthu_r_r_r
|
|
inst_evsetgths :: inst_evsetgths_r_r_r
|
|
emit_evsetgths :: emit_evsetgths_r_r_r
|
|
inst_evsetgtwu :: inst_evsetgtwu_r_r_r
|
|
emit_evsetgtwu :: emit_evsetgtwu_r_r_r
|
|
inst_evsetgtws :: inst_evsetgtws_r_r_r
|
|
emit_evsetgtws :: emit_evsetgtws_r_r_r
|
|
inst_evsetgtbu :: inst_evsetgtbu_r_r_r
|
|
emit_evsetgtbu :: emit_evsetgtbu_r_r_r
|
|
inst_evsetgtbs :: inst_evsetgtbs_r_r_r
|
|
emit_evsetgtbs :: emit_evsetgtbs_r_r_r
|
|
inst_evsetltbu :: inst_evsetltbu_r_r_r
|
|
emit_evsetltbu :: emit_evsetltbu_r_r_r
|
|
inst_evsetltbs :: inst_evsetltbs_r_r_r
|
|
emit_evsetltbs :: emit_evsetltbs_r_r_r
|
|
inst_evsetlthu :: inst_evsetlthu_r_r_r
|
|
emit_evsetlthu :: emit_evsetlthu_r_r_r
|
|
inst_evsetlths :: inst_evsetlths_r_r_r
|
|
emit_evsetlths :: emit_evsetlths_r_r_r
|
|
inst_evsetltwu :: inst_evsetltwu_r_r_r
|
|
emit_evsetltwu :: emit_evsetltwu_r_r_r
|
|
inst_evsetltws :: inst_evsetltws_r_r_r
|
|
emit_evsetltws :: emit_evsetltws_r_r_r
|
|
inst_evsaduw :: inst_evsaduw_r_r_r
|
|
emit_evsaduw :: emit_evsaduw_r_r_r
|
|
inst_evsadsw :: inst_evsadsw_r_r_r
|
|
emit_evsadsw :: emit_evsadsw_r_r_r
|
|
inst_evsad4ub :: inst_evsad4ub_r_r_r
|
|
emit_evsad4ub :: emit_evsad4ub_r_r_r
|
|
inst_evsad4sb :: inst_evsad4sb_r_r_r
|
|
emit_evsad4sb :: emit_evsad4sb_r_r_r
|
|
inst_evsad2uh :: inst_evsad2uh_r_r_r
|
|
emit_evsad2uh :: emit_evsad2uh_r_r_r
|
|
inst_evsad2sh :: inst_evsad2sh_r_r_r
|
|
emit_evsad2sh :: emit_evsad2sh_r_r_r
|
|
inst_evsaduwa :: inst_evsaduwa_r_r_r
|
|
emit_evsaduwa :: emit_evsaduwa_r_r_r
|
|
inst_evsadswa :: inst_evsadswa_r_r_r
|
|
emit_evsadswa :: emit_evsadswa_r_r_r
|
|
inst_evsad4uba :: inst_evsad4uba_r_r_r
|
|
emit_evsad4uba :: emit_evsad4uba_r_r_r
|
|
inst_evsad4sba :: inst_evsad4sba_r_r_r
|
|
emit_evsad4sba :: emit_evsad4sba_r_r_r
|
|
inst_evsad2uha :: inst_evsad2uha_r_r_r
|
|
emit_evsad2uha :: emit_evsad2uha_r_r_r
|
|
inst_evsad2sha :: inst_evsad2sha_r_r_r
|
|
emit_evsad2sha :: emit_evsad2sha_r_r_r
|
|
inst_evabsdifuw :: inst_evabsdifuw_r_r_r
|
|
emit_evabsdifuw :: emit_evabsdifuw_r_r_r
|
|
inst_evabsdifsw :: inst_evabsdifsw_r_r_r
|
|
emit_evabsdifsw :: emit_evabsdifsw_r_r_r
|
|
inst_evabsdifub :: inst_evabsdifub_r_r_r
|
|
emit_evabsdifub :: emit_evabsdifub_r_r_r
|
|
inst_evabsdifsb :: inst_evabsdifsb_r_r_r
|
|
emit_evabsdifsb :: emit_evabsdifsb_r_r_r
|
|
inst_evabsdifuh :: inst_evabsdifuh_r_r_r
|
|
emit_evabsdifuh :: emit_evabsdifuh_r_r_r
|
|
inst_evabsdifsh :: inst_evabsdifsh_r_r_r
|
|
emit_evabsdifsh :: emit_evabsdifsh_r_r_r
|
|
inst_evsaduwaa :: inst_evsaduwaa_r_r_r
|
|
emit_evsaduwaa :: emit_evsaduwaa_r_r_r
|
|
inst_evsadswaa :: inst_evsadswaa_r_r_r
|
|
emit_evsadswaa :: emit_evsadswaa_r_r_r
|
|
inst_evsad4ubaaw :: inst_evsad4ubaaw_r_r_r
|
|
emit_evsad4ubaaw :: emit_evsad4ubaaw_r_r_r
|
|
inst_evsad4sbaaw :: inst_evsad4sbaaw_r_r_r
|
|
emit_evsad4sbaaw :: emit_evsad4sbaaw_r_r_r
|
|
inst_evsad2uhaaw :: inst_evsad2uhaaw_r_r_r
|
|
emit_evsad2uhaaw :: emit_evsad2uhaaw_r_r_r
|
|
inst_evsad2shaaw :: inst_evsad2shaaw_r_r_r
|
|
emit_evsad2shaaw :: emit_evsad2shaaw_r_r_r
|
|
inst_evpkshubs :: inst_evpkshubs_r_r_r
|
|
emit_evpkshubs :: emit_evpkshubs_r_r_r
|
|
inst_evpkshsbs :: inst_evpkshsbs_r_r_r
|
|
emit_evpkshsbs :: emit_evpkshsbs_r_r_r
|
|
inst_evpkswuhs :: inst_evpkswuhs_r_r_r
|
|
emit_evpkswuhs :: emit_evpkswuhs_r_r_r
|
|
inst_evpkswshs :: inst_evpkswshs_r_r_r
|
|
emit_evpkswshs :: emit_evpkswshs_r_r_r
|
|
inst_evpkuhubs :: inst_evpkuhubs_r_r_r
|
|
emit_evpkuhubs :: emit_evpkuhubs_r_r_r
|
|
inst_evpkuwuhs :: inst_evpkuwuhs_r_r_r
|
|
emit_evpkuwuhs :: emit_evpkuwuhs_r_r_r
|
|
inst_evpkswshilvs :: inst_evpkswshilvs_r_r_r
|
|
emit_evpkswshilvs :: emit_evpkswshilvs_r_r_r
|
|
inst_evpkswgshefrs :: inst_evpkswgshefrs_r_r_r
|
|
emit_evpkswgshefrs :: emit_evpkswgshefrs_r_r_r
|
|
inst_evpkswshfrs :: inst_evpkswshfrs_r_r_r
|
|
emit_evpkswshfrs :: emit_evpkswshfrs_r_r_r
|
|
inst_evpkswshilvfrs :: inst_evpkswshilvfrs_r_r_r
|
|
emit_evpkswshilvfrs :: emit_evpkswshilvfrs_r_r_r
|
|
inst_evpksdswfrs :: inst_evpksdswfrs_r_r_r
|
|
emit_evpksdswfrs :: emit_evpksdswfrs_r_r_r
|
|
inst_evpksdshefrs :: inst_evpksdshefrs_r_r_r
|
|
emit_evpksdshefrs :: emit_evpksdshefrs_r_r_r
|
|
inst_evpkuduws :: inst_evpkuduws_r_r_r
|
|
emit_evpkuduws :: emit_evpkuduws_r_r_r
|
|
inst_evpksdsws :: inst_evpksdsws_r_r_r
|
|
emit_evpksdsws :: emit_evpksdsws_r_r_r
|
|
inst_evpkswgswfrs :: inst_evpkswgswfrs_r_r_r
|
|
emit_evpkswgswfrs :: emit_evpkswgswfrs_r_r_r
|
|
inst_evilveh :: inst_evilveh_r_r_r
|
|
emit_evilveh :: emit_evilveh_r_r_r
|
|
inst_evilveoh :: inst_evilveoh_r_r_r
|
|
emit_evilveoh :: emit_evilveoh_r_r_r
|
|
inst_evilvhih :: inst_evilvhih_r_r_r
|
|
emit_evilvhih :: emit_evilvhih_r_r_r
|
|
inst_evilvhiloh :: inst_evilvhiloh_r_r_r
|
|
emit_evilvhiloh :: emit_evilvhiloh_r_r_r
|
|
inst_evilvloh :: inst_evilvloh_r_r_r
|
|
emit_evilvloh :: emit_evilvloh_r_r_r
|
|
inst_evilvlohih :: inst_evilvlohih_r_r_r
|
|
emit_evilvlohih :: emit_evilvlohih_r_r_r
|
|
inst_evilvoeh :: inst_evilvoeh_r_r_r
|
|
emit_evilvoeh :: emit_evilvoeh_r_r_r
|
|
inst_evilvoh :: inst_evilvoh_r_r_r
|
|
emit_evilvoh :: emit_evilvoh_r_r_r
|
|
inst_evdlveb :: inst_evdlveb_r_r_r
|
|
emit_evdlveb :: emit_evdlveb_r_r_r
|
|
inst_evdlveh :: inst_evdlveh_r_r_r
|
|
emit_evdlveh :: emit_evdlveh_r_r_r
|
|
inst_evdlveob :: inst_evdlveob_r_r_r
|
|
emit_evdlveob :: emit_evdlveob_r_r_r
|
|
inst_evdlveoh :: inst_evdlveoh_r_r_r
|
|
emit_evdlveoh :: emit_evdlveoh_r_r_r
|
|
inst_evdlvob :: inst_evdlvob_r_r_r
|
|
emit_evdlvob :: emit_evdlvob_r_r_r
|
|
inst_evdlvoh :: inst_evdlvoh_r_r_r
|
|
emit_evdlvoh :: emit_evdlvoh_r_r_r
|
|
inst_evdlvoeb :: inst_evdlvoeb_r_r_r
|
|
emit_evdlvoeb :: emit_evdlvoeb_r_r_r
|
|
inst_evdlvoeh :: inst_evdlvoeh_r_r_r
|
|
emit_evdlvoeh :: emit_evdlvoeh_r_r_r
|
|
inst_evmaxbu :: inst_evmaxbu_r_r_r
|
|
emit_evmaxbu :: emit_evmaxbu_r_r_r
|
|
inst_evmaxbs :: inst_evmaxbs_r_r_r
|
|
emit_evmaxbs :: emit_evmaxbs_r_r_r
|
|
inst_evmaxhu :: inst_evmaxhu_r_r_r
|
|
emit_evmaxhu :: emit_evmaxhu_r_r_r
|
|
inst_evmaxhs :: inst_evmaxhs_r_r_r
|
|
emit_evmaxhs :: emit_evmaxhs_r_r_r
|
|
inst_evmaxwu :: inst_evmaxwu_r_r_r
|
|
emit_evmaxwu :: emit_evmaxwu_r_r_r
|
|
inst_evmaxws :: inst_evmaxws_r_r_r
|
|
emit_evmaxws :: emit_evmaxws_r_r_r
|
|
inst_evmaxdu :: inst_evmaxdu_r_r_r
|
|
emit_evmaxdu :: emit_evmaxdu_r_r_r
|
|
inst_evmaxds :: inst_evmaxds_r_r_r
|
|
emit_evmaxds :: emit_evmaxds_r_r_r
|
|
inst_evminbu :: inst_evminbu_r_r_r
|
|
emit_evminbu :: emit_evminbu_r_r_r
|
|
inst_evminbs :: inst_evminbs_r_r_r
|
|
emit_evminbs :: emit_evminbs_r_r_r
|
|
inst_evminhu :: inst_evminhu_r_r_r
|
|
emit_evminhu :: emit_evminhu_r_r_r
|
|
inst_evminhs :: inst_evminhs_r_r_r
|
|
emit_evminhs :: emit_evminhs_r_r_r
|
|
inst_evminwu :: inst_evminwu_r_r_r
|
|
emit_evminwu :: emit_evminwu_r_r_r
|
|
inst_evminws :: inst_evminws_r_r_r
|
|
emit_evminws :: emit_evminws_r_r_r
|
|
inst_evmindu :: inst_evmindu_r_r_r
|
|
emit_evmindu :: emit_evmindu_r_r_r
|
|
inst_evminds :: inst_evminds_r_r_r
|
|
emit_evminds :: emit_evminds_r_r_r
|
|
inst_evavgwu :: inst_evavgwu_r_r_r
|
|
emit_evavgwu :: emit_evavgwu_r_r_r
|
|
inst_evavgws :: inst_evavgws_r_r_r
|
|
emit_evavgws :: emit_evavgws_r_r_r
|
|
inst_evavgbu :: inst_evavgbu_r_r_r
|
|
emit_evavgbu :: emit_evavgbu_r_r_r
|
|
inst_evavgbs :: inst_evavgbs_r_r_r
|
|
emit_evavgbs :: emit_evavgbs_r_r_r
|
|
inst_evavghu :: inst_evavghu_r_r_r
|
|
emit_evavghu :: emit_evavghu_r_r_r
|
|
inst_evavghs :: inst_evavghs_r_r_r
|
|
emit_evavghs :: emit_evavghs_r_r_r
|
|
inst_evavgdu :: inst_evavgdu_r_r_r
|
|
emit_evavgdu :: emit_evavgdu_r_r_r
|
|
inst_evavgds :: inst_evavgds_r_r_r
|
|
emit_evavgds :: emit_evavgds_r_r_r
|
|
inst_evavgwur :: inst_evavgwur_r_r_r
|
|
emit_evavgwur :: emit_evavgwur_r_r_r
|
|
inst_evavgwsr :: inst_evavgwsr_r_r_r
|
|
emit_evavgwsr :: emit_evavgwsr_r_r_r
|
|
inst_evavgbur :: inst_evavgbur_r_r_r
|
|
emit_evavgbur :: emit_evavgbur_r_r_r
|
|
inst_evavgbsr :: inst_evavgbsr_r_r_r
|
|
emit_evavgbsr :: emit_evavgbsr_r_r_r
|
|
inst_evavghur :: inst_evavghur_r_r_r
|
|
emit_evavghur :: emit_evavghur_r_r_r
|
|
inst_evavghsr :: inst_evavghsr_r_r_r
|
|
emit_evavghsr :: emit_evavghsr_r_r_r
|
|
inst_evavgdur :: inst_evavgdur_r_r_r
|
|
emit_evavgdur :: emit_evavgdur_r_r_r
|
|
inst_evavgdsr :: inst_evavgdsr_r_r_r
|
|
emit_evavgdsr :: emit_evavgdsr_r_r_r
|
|
inst_ps_div :: inst_ps_div_fr_fr_fr
|
|
emit_ps_div :: emit_ps_div_fr_fr_fr
|
|
inst_ps_div_dot :: inst_ps_div_dot_fr_fr_fr
|
|
emit_ps_div_dot :: emit_ps_div_dot_fr_fr_fr
|
|
inst_ps_sub :: inst_ps_sub_fr_fr_fr
|
|
emit_ps_sub :: emit_ps_sub_fr_fr_fr
|
|
inst_ps_sub_dot :: inst_ps_sub_dot_fr_fr_fr
|
|
emit_ps_sub_dot :: emit_ps_sub_dot_fr_fr_fr
|
|
inst_ps_add :: inst_ps_add_fr_fr_fr
|
|
emit_ps_add :: emit_ps_add_fr_fr_fr
|
|
inst_ps_add_dot :: inst_ps_add_dot_fr_fr_fr
|
|
emit_ps_add_dot :: emit_ps_add_dot_fr_fr_fr
|
|
inst_ps_sel :: inst_ps_sel_fr_fr_fr_fr
|
|
emit_ps_sel :: emit_ps_sel_fr_fr_fr_fr
|
|
inst_ps_sel_dot :: inst_ps_sel_dot_fr_fr_fr_fr
|
|
emit_ps_sel_dot :: emit_ps_sel_dot_fr_fr_fr_fr
|
|
inst_ps_res :: inst_ps_res_fr_fr
|
|
emit_ps_res :: emit_ps_res_fr_fr
|
|
inst_ps_res_dot :: inst_ps_res_dot_fr_fr
|
|
emit_ps_res_dot :: emit_ps_res_dot_fr_fr
|
|
inst_ps_mul :: inst_ps_mul_fr_fr_fr
|
|
emit_ps_mul :: emit_ps_mul_fr_fr_fr
|
|
inst_ps_mul_dot :: inst_ps_mul_dot_fr_fr_fr
|
|
emit_ps_mul_dot :: emit_ps_mul_dot_fr_fr_fr
|
|
inst_ps_rsqrte :: inst_ps_rsqrte_fr_fr
|
|
emit_ps_rsqrte :: emit_ps_rsqrte_fr_fr
|
|
inst_ps_rsqrte_dot :: inst_ps_rsqrte_dot_fr_fr
|
|
emit_ps_rsqrte_dot :: emit_ps_rsqrte_dot_fr_fr
|
|
inst_ps_msub :: inst_ps_msub_fr_fr_fr_fr
|
|
emit_ps_msub :: emit_ps_msub_fr_fr_fr_fr
|
|
inst_ps_msub_dot :: inst_ps_msub_dot_fr_fr_fr_fr
|
|
emit_ps_msub_dot :: emit_ps_msub_dot_fr_fr_fr_fr
|
|
inst_ps_madd :: inst_ps_madd_fr_fr_fr_fr
|
|
emit_ps_madd :: emit_ps_madd_fr_fr_fr_fr
|
|
inst_ps_madd_dot :: inst_ps_madd_dot_fr_fr_fr_fr
|
|
emit_ps_madd_dot :: emit_ps_madd_dot_fr_fr_fr_fr
|
|
inst_ps_nmsub :: inst_ps_nmsub_fr_fr_fr_fr
|
|
emit_ps_nmsub :: emit_ps_nmsub_fr_fr_fr_fr
|
|
inst_ps_nmsub_dot :: inst_ps_nmsub_dot_fr_fr_fr_fr
|
|
emit_ps_nmsub_dot :: emit_ps_nmsub_dot_fr_fr_fr_fr
|
|
inst_ps_nmadd :: inst_ps_nmadd_fr_fr_fr_fr
|
|
emit_ps_nmadd :: emit_ps_nmadd_fr_fr_fr_fr
|
|
inst_ps_nmadd_dot :: inst_ps_nmadd_dot_fr_fr_fr_fr
|
|
emit_ps_nmadd_dot :: emit_ps_nmadd_dot_fr_fr_fr_fr
|
|
inst_ps_sum0 :: inst_ps_sum0_fr_fr_fr_fr
|
|
emit_ps_sum0 :: emit_ps_sum0_fr_fr_fr_fr
|
|
inst_ps_sum0_dot :: inst_ps_sum0_dot_fr_fr_fr_fr
|
|
emit_ps_sum0_dot :: emit_ps_sum0_dot_fr_fr_fr_fr
|
|
inst_ps_sum1 :: inst_ps_sum1_fr_fr_fr_fr
|
|
emit_ps_sum1 :: emit_ps_sum1_fr_fr_fr_fr
|
|
inst_ps_sum1_dot :: inst_ps_sum1_dot_fr_fr_fr_fr
|
|
emit_ps_sum1_dot :: emit_ps_sum1_dot_fr_fr_fr_fr
|
|
inst_ps_muls0 :: inst_ps_muls0_fr_fr_fr
|
|
emit_ps_muls0 :: emit_ps_muls0_fr_fr_fr
|
|
inst_ps_muls0_dot :: inst_ps_muls0_dot_fr_fr_fr
|
|
emit_ps_muls0_dot :: emit_ps_muls0_dot_fr_fr_fr
|
|
inst_ps_muls1 :: inst_ps_muls1_fr_fr_fr
|
|
emit_ps_muls1 :: emit_ps_muls1_fr_fr_fr
|
|
inst_ps_muls1_dot :: inst_ps_muls1_dot_fr_fr_fr
|
|
emit_ps_muls1_dot :: emit_ps_muls1_dot_fr_fr_fr
|
|
inst_ps_madds0 :: inst_ps_madds0_fr_fr_fr_fr
|
|
emit_ps_madds0 :: emit_ps_madds0_fr_fr_fr_fr
|
|
inst_ps_madds0_dot :: inst_ps_madds0_dot_fr_fr_fr_fr
|
|
emit_ps_madds0_dot :: emit_ps_madds0_dot_fr_fr_fr_fr
|
|
inst_ps_madds1 :: inst_ps_madds1_fr_fr_fr_fr
|
|
emit_ps_madds1 :: emit_ps_madds1_fr_fr_fr_fr
|
|
inst_ps_madds1_dot :: inst_ps_madds1_dot_fr_fr_fr_fr
|
|
emit_ps_madds1_dot :: emit_ps_madds1_dot_fr_fr_fr_fr
|
|
inst_ps_neg :: inst_ps_neg_fr_fr
|
|
emit_ps_neg :: emit_ps_neg_fr_fr
|
|
inst_ps_neg_dot :: inst_ps_neg_dot_fr_fr
|
|
emit_ps_neg_dot :: emit_ps_neg_dot_fr_fr
|
|
inst_ps_mr :: inst_ps_mr_fr_fr
|
|
emit_ps_mr :: emit_ps_mr_fr_fr
|
|
inst_ps_mr_dot :: inst_ps_mr_dot_fr_fr
|
|
emit_ps_mr_dot :: emit_ps_mr_dot_fr_fr
|
|
inst_ps_nabs :: inst_ps_nabs_fr_fr
|
|
emit_ps_nabs :: emit_ps_nabs_fr_fr
|
|
inst_ps_nabs_dot :: inst_ps_nabs_dot_fr_fr
|
|
emit_ps_nabs_dot :: emit_ps_nabs_dot_fr_fr
|
|
inst_ps_abs :: inst_ps_abs_fr_fr
|
|
emit_ps_abs :: emit_ps_abs_fr_fr
|
|
inst_ps_abs_dot :: inst_ps_abs_dot_fr_fr
|
|
emit_ps_abs_dot :: emit_ps_abs_dot_fr_fr
|
|
inst_ps_cmpu0 :: inst_ps_cmpu0_crf_fr_fr
|
|
emit_ps_cmpu0 :: emit_ps_cmpu0_crf_fr_fr
|
|
inst_ps_cmpu1 :: inst_ps_cmpu1_crf_fr_fr
|
|
emit_ps_cmpu1 :: emit_ps_cmpu1_crf_fr_fr
|
|
inst_ps_cmpo0 :: inst_ps_cmpo0_crf_fr_fr
|
|
emit_ps_cmpo0 :: emit_ps_cmpo0_crf_fr_fr
|
|
inst_ps_cmpo1 :: inst_ps_cmpo1_crf_fr_fr
|
|
emit_ps_cmpo1 :: emit_ps_cmpo1_crf_fr_fr
|
|
inst_ps_merge00 :: inst_ps_merge00_fr_fr_fr
|
|
emit_ps_merge00 :: emit_ps_merge00_fr_fr_fr
|
|
inst_ps_merge00_dot :: inst_ps_merge00_dot_fr_fr_fr
|
|
emit_ps_merge00_dot :: emit_ps_merge00_dot_fr_fr_fr
|
|
inst_ps_merge01 :: inst_ps_merge01_fr_fr_fr
|
|
emit_ps_merge01 :: emit_ps_merge01_fr_fr_fr
|
|
inst_ps_merge01_dot :: inst_ps_merge01_dot_fr_fr_fr
|
|
emit_ps_merge01_dot :: emit_ps_merge01_dot_fr_fr_fr
|
|
inst_ps_merge10 :: inst_ps_merge10_fr_fr_fr
|
|
emit_ps_merge10 :: emit_ps_merge10_fr_fr_fr
|
|
inst_ps_merge10_dot :: inst_ps_merge10_dot_fr_fr_fr
|
|
emit_ps_merge10_dot :: emit_ps_merge10_dot_fr_fr_fr
|
|
inst_ps_merge11 :: inst_ps_merge11_fr_fr_fr
|
|
emit_ps_merge11 :: emit_ps_merge11_fr_fr_fr
|
|
inst_ps_merge11_dot :: inst_ps_merge11_dot_fr_fr_fr
|
|
emit_ps_merge11_dot :: emit_ps_merge11_dot_fr_fr_fr
|
|
inst_psq_lx :: inst_psq_lx_fr_mem
|
|
emit_psq_lx :: emit_psq_lx_fr_mem
|
|
inst_psq_lux :: inst_psq_lux_fr_mem
|
|
emit_psq_lux :: emit_psq_lux_fr_mem
|
|
inst_psq_stx :: inst_psq_stx_fr_mem
|
|
emit_psq_stx :: emit_psq_stx_fr_mem
|
|
inst_psq_stux :: inst_psq_stux_fr_mem
|
|
emit_psq_stux :: emit_psq_stux_fr_mem
|
|
inst_psq_l :: inst_psq_l_fr_mem
|
|
emit_psq_l :: emit_psq_l_fr_mem
|
|
inst_psq_lu :: inst_psq_lu_fr_mem
|
|
emit_psq_lu :: emit_psq_lu_fr_mem
|
|
inst_psq_st :: inst_psq_st_fr_mem
|
|
emit_psq_st :: emit_psq_st_fr_mem
|
|
inst_psq_stu :: inst_psq_stu_fr_mem
|
|
emit_psq_stu :: emit_psq_stu_fr_mem
|
|
inst_vaddfp128 :: inst_vaddfp128_vr128_vr128_vr128
|
|
emit_vaddfp128 :: emit_vaddfp128_vr128_vr128_vr128
|
|
inst_vsubfp128 :: inst_vsubfp128_vr128_vr128_vr128
|
|
emit_vsubfp128 :: emit_vsubfp128_vr128_vr128_vr128
|
|
inst_vmulfp128 :: inst_vmulfp128_vr128_vr128_vr128
|
|
emit_vmulfp128 :: emit_vmulfp128_vr128_vr128_vr128
|
|
inst_vmaddfp128 :: inst_vmaddfp128_vr128_vr128_vr128_vr128
|
|
emit_vmaddfp128 :: emit_vmaddfp128_vr128_vr128_vr128_vr128
|
|
inst_vmaddcfp128 :: inst_vmaddcfp128_vr128_vr128_vr128_vr128
|
|
emit_vmaddcfp128 :: emit_vmaddcfp128_vr128_vr128_vr128_vr128
|
|
inst_vnmsubfp128 :: inst_vnmsubfp128_vr128_vr128_vr128_vr128
|
|
emit_vnmsubfp128 :: emit_vnmsubfp128_vr128_vr128_vr128_vr128
|
|
inst_vmsum3fp128 :: inst_vmsum3fp128_vr128_vr128_vr128_vr128
|
|
emit_vmsum3fp128 :: emit_vmsum3fp128_vr128_vr128_vr128_vr128
|
|
inst_vmsum4fp128 :: inst_vmsum4fp128_vr128_vr128_vr128_vr128
|
|
emit_vmsum4fp128 :: emit_vmsum4fp128_vr128_vr128_vr128_vr128
|
|
inst_vmaxfp128 :: inst_vmaxfp128_vr128_vr128_vr128
|
|
emit_vmaxfp128 :: emit_vmaxfp128_vr128_vr128_vr128
|
|
inst_vminfp128 :: inst_vminfp128_vr128_vr128_vr128
|
|
emit_vminfp128 :: emit_vminfp128_vr128_vr128_vr128
|
|
inst_vrefp128 :: inst_vrefp128_vr128_vr128
|
|
emit_vrefp128 :: emit_vrefp128_vr128_vr128
|
|
inst_vrsqrtefp128 :: inst_vrsqrtefp128_vr128_vr128
|
|
emit_vrsqrtefp128 :: emit_vrsqrtefp128_vr128_vr128
|
|
inst_vexptefp128 :: inst_vexptefp128_vr128_vr128
|
|
emit_vexptefp128 :: emit_vexptefp128_vr128_vr128
|
|
inst_vlogefp128 :: inst_vlogefp128_vr128_vr128
|
|
emit_vlogefp128 :: emit_vlogefp128_vr128_vr128
|
|
inst_vand128 :: inst_vand128_vr128_vr128_vr128
|
|
emit_vand128 :: emit_vand128_vr128_vr128_vr128
|
|
inst_vandc128 :: inst_vandc128_vr128_vr128_vr128
|
|
emit_vandc128 :: emit_vandc128_vr128_vr128_vr128
|
|
inst_vor128 :: inst_vor128_vr128_vr128_vr128
|
|
emit_vor128 :: emit_vor128_vr128_vr128_vr128
|
|
inst_vxor128 :: inst_vxor128_vr128_vr128_vr128
|
|
emit_vxor128 :: emit_vxor128_vr128_vr128_vr128
|
|
inst_vnor128 :: inst_vnor128_vr128_vr128_vr128
|
|
emit_vnor128 :: emit_vnor128_vr128_vr128_vr128
|
|
inst_vsel128 :: inst_vsel128_vr128_vr128_vr128_vr128
|
|
emit_vsel128 :: emit_vsel128_vr128_vr128_vr128_vr128
|
|
inst_vcmpeqfp128 :: inst_vcmpeqfp128_vr128_vr128_vr128
|
|
emit_vcmpeqfp128 :: emit_vcmpeqfp128_vr128_vr128_vr128
|
|
inst_vcmpeqfp128_dot :: inst_vcmpeqfp128_dot_vr128_vr128_vr128
|
|
emit_vcmpeqfp128_dot :: emit_vcmpeqfp128_dot_vr128_vr128_vr128
|
|
inst_vcmpgefp128 :: inst_vcmpgefp128_vr128_vr128_vr128
|
|
emit_vcmpgefp128 :: emit_vcmpgefp128_vr128_vr128_vr128
|
|
inst_vcmpgefp128_dot :: inst_vcmpgefp128_dot_vr128_vr128_vr128
|
|
emit_vcmpgefp128_dot :: emit_vcmpgefp128_dot_vr128_vr128_vr128
|
|
inst_vcmpgtfp128 :: inst_vcmpgtfp128_vr128_vr128_vr128
|
|
emit_vcmpgtfp128 :: emit_vcmpgtfp128_vr128_vr128_vr128
|
|
inst_vcmpgtfp128_dot :: inst_vcmpgtfp128_dot_vr128_vr128_vr128
|
|
emit_vcmpgtfp128_dot :: emit_vcmpgtfp128_dot_vr128_vr128_vr128
|
|
inst_vcmpbfp128 :: inst_vcmpbfp128_vr128_vr128_vr128
|
|
emit_vcmpbfp128 :: emit_vcmpbfp128_vr128_vr128_vr128
|
|
inst_vcmpbfp128_dot :: inst_vcmpbfp128_dot_vr128_vr128_vr128
|
|
emit_vcmpbfp128_dot :: emit_vcmpbfp128_dot_vr128_vr128_vr128
|
|
inst_vcmpequw128 :: inst_vcmpequw128_vr128_vr128_vr128
|
|
emit_vcmpequw128 :: emit_vcmpequw128_vr128_vr128_vr128
|
|
inst_vcmpequw128_dot :: inst_vcmpequw128_dot_vr128_vr128_vr128
|
|
emit_vcmpequw128_dot :: emit_vcmpequw128_dot_vr128_vr128_vr128
|
|
inst_vrfim128 :: inst_vrfim128_vr128_vr128
|
|
emit_vrfim128 :: emit_vrfim128_vr128_vr128
|
|
inst_vrfin128 :: inst_vrfin128_vr128_vr128
|
|
emit_vrfin128 :: emit_vrfin128_vr128_vr128
|
|
inst_vrfip128 :: inst_vrfip128_vr128_vr128
|
|
emit_vrfip128 :: emit_vrfip128_vr128_vr128
|
|
inst_vrfiz128 :: inst_vrfiz128_vr128_vr128
|
|
emit_vrfiz128 :: emit_vrfiz128_vr128_vr128
|
|
inst_vcfpsxws128 :: inst_vcfpsxws128_vr128_vr128
|
|
emit_vcfpsxws128 :: emit_vcfpsxws128_vr128_vr128
|
|
inst_vcfpuxws128 :: inst_vcfpuxws128_vr128_vr128
|
|
emit_vcfpuxws128 :: emit_vcfpuxws128_vr128_vr128
|
|
inst_vcsxwfp128 :: inst_vcsxwfp128_vr128_vr128
|
|
emit_vcsxwfp128 :: emit_vcsxwfp128_vr128_vr128
|
|
inst_vcuxwfp128 :: inst_vcuxwfp128_vr128_vr128
|
|
emit_vcuxwfp128 :: emit_vcuxwfp128_vr128_vr128
|
|
inst_vspltw128 :: inst_vspltw128_vr128_vr128_imm
|
|
emit_vspltw128 :: emit_vspltw128_vr128_vr128_imm
|
|
inst_vspltisw128 :: inst_vspltisw128_vr128_imm
|
|
emit_vspltisw128 :: emit_vspltisw128_vr128_imm
|
|
inst_vmrghw128 :: inst_vmrghw128_vr128_vr128_vr128
|
|
emit_vmrghw128 :: emit_vmrghw128_vr128_vr128_vr128
|
|
inst_vmrglw128 :: inst_vmrglw128_vr128_vr128_vr128
|
|
emit_vmrglw128 :: emit_vmrglw128_vr128_vr128_vr128
|
|
inst_vpkd3d128 :: inst_vpkd3d128_vr128_vr128_imm_imm
|
|
emit_vpkd3d128 :: emit_vpkd3d128_vr128_vr128_imm_imm
|
|
inst_vupkd3d128 :: inst_vupkd3d128_vr128_vr128_imm
|
|
emit_vupkd3d128 :: emit_vupkd3d128_vr128_vr128_imm
|
|
inst_vperm128 :: inst_vperm128_vr128_vr128_vr128_vr128
|
|
emit_vperm128 :: emit_vperm128_vr128_vr128_vr128_vr128
|
|
inst_vpermwi128 :: inst_vpermwi128_vr128_vr128_imm
|
|
emit_vpermwi128 :: emit_vpermwi128_vr128_vr128_imm
|
|
inst_vrlimi128 :: inst_vrlimi128_vr128_vr128_imm_imm
|
|
emit_vrlimi128 :: emit_vrlimi128_vr128_vr128_imm_imm
|
|
inst_vsldoi128 :: inst_vsldoi128_vr128_vr128_vr128_imm
|
|
emit_vsldoi128 :: emit_vsldoi128_vr128_vr128_vr128_imm
|
|
inst_vrlw128 :: inst_vrlw128_vr128_vr128_vr128
|
|
emit_vrlw128 :: emit_vrlw128_vr128_vr128_vr128
|
|
inst_vslw128 :: inst_vslw128_vr128_vr128_vr128
|
|
emit_vslw128 :: emit_vslw128_vr128_vr128_vr128
|
|
inst_vsrw128 :: inst_vsrw128_vr128_vr128_vr128
|
|
emit_vsrw128 :: emit_vsrw128_vr128_vr128_vr128
|
|
inst_vsraw128 :: inst_vsraw128_vr128_vr128_vr128
|
|
emit_vsraw128 :: emit_vsraw128_vr128_vr128_vr128
|
|
inst_lvebx128 :: inst_lvebx128_vr128_r_r
|
|
emit_lvebx128 :: emit_lvebx128_vr128_r_r
|
|
inst_lvehx128 :: inst_lvehx128_vr128_r_r
|
|
emit_lvehx128 :: emit_lvehx128_vr128_r_r
|
|
inst_lvewx128 :: inst_lvewx128_vr128_r_r
|
|
emit_lvewx128 :: emit_lvewx128_vr128_r_r
|
|
inst_lvx128 :: inst_lvx128_vr128_r_r
|
|
emit_lvx128 :: emit_lvx128_vr128_r_r
|
|
inst_lvxl128 :: inst_lvxl128_vr128_r_r
|
|
emit_lvxl128 :: emit_lvxl128_vr128_r_r
|
|
inst_lvlx128 :: inst_lvlx128_vr128_r_r
|
|
emit_lvlx128 :: emit_lvlx128_vr128_r_r
|
|
inst_lvrx128 :: inst_lvrx128_vr128_r_r
|
|
emit_lvrx128 :: emit_lvrx128_vr128_r_r
|
|
inst_lvlxl128 :: inst_lvlxl128_vr128_r_r
|
|
emit_lvlxl128 :: emit_lvlxl128_vr128_r_r
|
|
inst_lvrxl128 :: inst_lvrxl128_vr128_r_r
|
|
emit_lvrxl128 :: emit_lvrxl128_vr128_r_r
|
|
inst_stvebx128 :: inst_stvebx128_vr128_r_r
|
|
emit_stvebx128 :: emit_stvebx128_vr128_r_r
|
|
inst_stvehx128 :: inst_stvehx128_vr128_r_r
|
|
emit_stvehx128 :: emit_stvehx128_vr128_r_r
|
|
inst_stvewx128 :: inst_stvewx128_vr128_r_r
|
|
emit_stvewx128 :: emit_stvewx128_vr128_r_r
|
|
inst_stvx128 :: inst_stvx128_vr128_r_r
|
|
emit_stvx128 :: emit_stvx128_vr128_r_r
|
|
inst_stvxl128 :: inst_stvxl128_vr128_r_r
|
|
emit_stvxl128 :: emit_stvxl128_vr128_r_r
|
|
inst_stvlx128 :: inst_stvlx128_vr128_r_r
|
|
emit_stvlx128 :: emit_stvlx128_vr128_r_r
|
|
inst_stvrx128 :: inst_stvrx128_vr128_r_r
|
|
emit_stvrx128 :: emit_stvrx128_vr128_r_r
|
|
inst_stvlxl128 :: inst_stvlxl128_vr128_r_r
|
|
emit_stvlxl128 :: emit_stvlxl128_vr128_r_r
|
|
inst_stvrxl128 :: inst_stvrxl128_vr128_r_r
|
|
emit_stvrxl128 :: emit_stvrxl128_vr128_r_r
|
|
inst_ti :: inst_ti_r_r_imm
|
|
emit_ti :: emit_ti_r_r_imm
|
|
inst_mulhhwu :: inst_mulhhwu_r_r_r
|
|
emit_mulhhwu :: emit_mulhhwu_r_r_r
|
|
inst_mulhhwu_dot :: inst_mulhhwu_dot_r_r_r
|
|
emit_mulhhwu_dot :: emit_mulhhwu_dot_r_r_r
|
|
inst_machhwu :: inst_machhwu_r_r_r
|
|
emit_machhwu :: emit_machhwu_r_r_r
|
|
inst_machhwu_dot :: inst_machhwu_dot_r_r_r
|
|
emit_machhwu_dot :: emit_machhwu_dot_r_r_r
|
|
inst_mulhhw :: inst_mulhhw_r_r_r
|
|
emit_mulhhw :: emit_mulhhw_r_r_r
|
|
inst_mulhhw_dot :: inst_mulhhw_dot_r_r_r
|
|
emit_mulhhw_dot :: emit_mulhhw_dot_r_r_r
|
|
inst_machhw :: inst_machhw_r_r_r
|
|
emit_machhw :: emit_machhw_r_r_r
|
|
inst_machhw_dot :: inst_machhw_dot_r_r_r
|
|
emit_machhw_dot :: emit_machhw_dot_r_r_r
|
|
inst_nmachhw :: inst_nmachhw_r_r_r
|
|
emit_nmachhw :: emit_nmachhw_r_r_r
|
|
inst_nmachhw_dot :: inst_nmachhw_dot_r_r_r
|
|
emit_nmachhw_dot :: emit_nmachhw_dot_r_r_r
|
|
inst_machhwsu :: inst_machhwsu_r_r_r
|
|
emit_machhwsu :: emit_machhwsu_r_r_r
|
|
inst_machhwsu_dot :: inst_machhwsu_dot_r_r_r
|
|
emit_machhwsu_dot :: emit_machhwsu_dot_r_r_r
|
|
inst_machhws :: inst_machhws_r_r_r
|
|
emit_machhws :: emit_machhws_r_r_r
|
|
inst_machhws_dot :: inst_machhws_dot_r_r_r
|
|
emit_machhws_dot :: emit_machhws_dot_r_r_r
|
|
inst_nmachhws :: inst_nmachhws_r_r_r
|
|
emit_nmachhws :: emit_nmachhws_r_r_r
|
|
inst_nmachhws_dot :: inst_nmachhws_dot_r_r_r
|
|
emit_nmachhws_dot :: emit_nmachhws_dot_r_r_r
|
|
inst_vadduqm :: inst_vadduqm_r_r_r
|
|
emit_vadduqm :: emit_vadduqm_r_r_r
|
|
inst_vcmpuq :: inst_vcmpuq_r_r_r
|
|
emit_vcmpuq :: emit_vcmpuq_r_r_r
|
|
inst_mulchwu :: inst_mulchwu_r_r_r
|
|
emit_mulchwu :: emit_mulchwu_r_r_r
|
|
inst_mulchwu_dot :: inst_mulchwu_dot_r_r_r
|
|
emit_mulchwu_dot :: emit_mulchwu_dot_r_r_r
|
|
inst_macchwu :: inst_macchwu_r_r_r
|
|
emit_macchwu :: emit_macchwu_r_r_r
|
|
inst_macchwu_dot :: inst_macchwu_dot_r_r_r
|
|
emit_macchwu_dot :: emit_macchwu_dot_r_r_r
|
|
inst_vcmpsq :: inst_vcmpsq_r_r_r
|
|
emit_vcmpsq :: emit_vcmpsq_r_r_r
|
|
inst_mulchw :: inst_mulchw_r_r_r
|
|
emit_mulchw :: emit_mulchw_r_r_r
|
|
inst_mulchw_dot :: inst_mulchw_dot_r_r_r
|
|
emit_mulchw_dot :: emit_mulchw_dot_r_r_r
|
|
inst_macchw :: inst_macchw_r_r_r
|
|
emit_macchw :: emit_macchw_r_r_r
|
|
inst_macchw_dot :: inst_macchw_dot_r_r_r
|
|
emit_macchw_dot :: emit_macchw_dot_r_r_r
|
|
inst_nmacchw :: inst_nmacchw_r_r_r
|
|
emit_nmacchw :: emit_nmacchw_r_r_r
|
|
inst_nmacchw_dot :: inst_nmacchw_dot_r_r_r
|
|
emit_nmacchw_dot :: emit_nmacchw_dot_r_r_r
|
|
inst_macchwsu :: inst_macchwsu_r_r_r
|
|
emit_macchwsu :: emit_macchwsu_r_r_r
|
|
inst_macchwsu_dot :: inst_macchwsu_dot_r_r_r
|
|
emit_macchwsu_dot :: emit_macchwsu_dot_r_r_r
|
|
inst_vcmpequq :: inst_vcmpequq_r_r_r
|
|
emit_vcmpequq :: emit_vcmpequq_r_r_r
|
|
inst_macchws :: inst_macchws_r_r_r
|
|
emit_macchws :: emit_macchws_r_r_r
|
|
inst_macchws_dot :: inst_macchws_dot_r_r_r
|
|
emit_macchws_dot :: emit_macchws_dot_r_r_r
|
|
inst_nmacchws :: inst_nmacchws_r_r_r
|
|
emit_nmacchws :: emit_nmacchws_r_r_r
|
|
inst_nmacchws_dot :: inst_nmacchws_dot_r_r_r
|
|
emit_nmacchws_dot :: emit_nmacchws_dot_r_r_r
|
|
inst_vcmpgtuq :: inst_vcmpgtuq_r_r_r
|
|
emit_vcmpgtuq :: emit_vcmpgtuq_r_r_r
|
|
inst_vcuxwfp :: inst_vcuxwfp_r_r_r
|
|
emit_vcuxwfp :: emit_vcuxwfp_r_r_r
|
|
inst_mullhwu :: inst_mullhwu_r_r_r
|
|
emit_mullhwu :: emit_mullhwu_r_r_r
|
|
inst_mullhwu_dot :: inst_mullhwu_dot_r_r_r
|
|
emit_mullhwu_dot :: emit_mullhwu_dot_r_r_r
|
|
inst_maclhwu :: inst_maclhwu_r_r_r
|
|
emit_maclhwu :: emit_maclhwu_r_r_r
|
|
inst_maclhwu_dot :: inst_maclhwu_dot_r_r_r
|
|
emit_maclhwu_dot :: emit_maclhwu_dot_r_r_r
|
|
inst_vcsxwfp :: inst_vcsxwfp_r_r_r
|
|
emit_vcsxwfp :: emit_vcsxwfp_r_r_r
|
|
inst_mullhw :: inst_mullhw_r_r_r
|
|
emit_mullhw :: emit_mullhw_r_r_r
|
|
inst_mullhw_dot :: inst_mullhw_dot_r_r_r
|
|
emit_mullhw_dot :: emit_mullhw_dot_r_r_r
|
|
inst_maclhw :: inst_maclhw_r_r_r
|
|
emit_maclhw :: emit_maclhw_r_r_r
|
|
inst_maclhw_dot :: inst_maclhw_dot_r_r_r
|
|
emit_maclhw_dot :: emit_maclhw_dot_r_r_r
|
|
inst_nmaclhw :: inst_nmaclhw_r_r_r
|
|
emit_nmaclhw :: emit_nmaclhw_r_r_r
|
|
inst_nmaclhw_dot :: inst_nmaclhw_dot_r_r_r
|
|
emit_nmaclhw_dot :: emit_nmaclhw_dot_r_r_r
|
|
inst_vcmpgtsq :: inst_vcmpgtsq_r_r_r
|
|
emit_vcmpgtsq :: emit_vcmpgtsq_r_r_r
|
|
inst_vcfpuxws :: inst_vcfpuxws_r_r_r
|
|
emit_vcfpuxws :: emit_vcfpuxws_r_r_r
|
|
inst_maclhwsu :: inst_maclhwsu_r_r_r
|
|
emit_maclhwsu :: emit_maclhwsu_r_r_r
|
|
inst_maclhwsu_dot :: inst_maclhwsu_dot_r_r_r
|
|
emit_maclhwsu_dot :: emit_maclhwsu_dot_r_r_r
|
|
inst_vcfpsxws :: inst_vcfpsxws_r_r_r
|
|
emit_vcfpsxws :: emit_vcfpsxws_r_r_r
|
|
inst_maclhws :: inst_maclhws_r_r_r
|
|
emit_maclhws :: emit_maclhws_r_r_r
|
|
inst_maclhws_dot :: inst_maclhws_dot_r_r_r
|
|
emit_maclhws_dot :: emit_maclhws_dot_r_r_r
|
|
inst_nmaclhws :: inst_nmaclhws_r_r_r
|
|
emit_nmaclhws :: emit_nmaclhws_r_r_r
|
|
inst_nmaclhws_dot :: inst_nmaclhws_dot_r_r_r
|
|
emit_nmaclhws_dot :: emit_nmaclhws_dot_r_r_r
|
|
inst_machhwuo :: inst_machhwuo_r_r_r
|
|
emit_machhwuo :: emit_machhwuo_r_r_r
|
|
inst_machhwuo_dot :: inst_machhwuo_dot_r_r_r
|
|
emit_machhwuo_dot :: emit_machhwuo_dot_r_r_r
|
|
inst_machhwo :: inst_machhwo_r_r_r
|
|
emit_machhwo :: emit_machhwo_r_r_r
|
|
inst_machhwo_dot :: inst_machhwo_dot_r_r_r
|
|
emit_machhwo_dot :: emit_machhwo_dot_r_r_r
|
|
inst_nmachhwo :: inst_nmachhwo_r_r_r
|
|
emit_nmachhwo :: emit_nmachhwo_r_r_r
|
|
inst_nmachhwo_dot :: inst_nmachhwo_dot_r_r_r
|
|
emit_nmachhwo_dot :: emit_nmachhwo_dot_r_r_r
|
|
inst_vmr :: inst_vmr_r_r_r
|
|
emit_vmr :: emit_vmr_r_r_r
|
|
inst_machhwsuo :: inst_machhwsuo_r_r_r
|
|
emit_machhwsuo :: emit_machhwsuo_r_r_r
|
|
inst_machhwsuo_dot :: inst_machhwsuo_dot_r_r_r
|
|
emit_machhwsuo_dot :: emit_machhwsuo_dot_r_r_r
|
|
inst_machhwso :: inst_machhwso_r_r_r
|
|
emit_machhwso :: emit_machhwso_r_r_r
|
|
inst_machhwso_dot :: inst_machhwso_dot_r_r_r
|
|
emit_machhwso_dot :: emit_machhwso_dot_r_r_r
|
|
inst_nmachhwso :: inst_nmachhwso_r_r_r
|
|
emit_nmachhwso :: emit_nmachhwso_r_r_r
|
|
inst_nmachhwso_dot :: inst_nmachhwso_dot_r_r_r
|
|
emit_nmachhwso_dot :: emit_nmachhwso_dot_r_r_r
|
|
inst_vsubuqm :: inst_vsubuqm_r_r_r
|
|
emit_vsubuqm :: emit_vsubuqm_r_r_r
|
|
inst_vnot :: inst_vnot_r_r_r
|
|
emit_vnot :: emit_vnot_r_r_r
|
|
inst_vgbbd :: inst_vgbbd_r_r_r
|
|
emit_vgbbd :: emit_vgbbd_r_r_r
|
|
inst_macchwuo :: inst_macchwuo_r_r_r
|
|
emit_macchwuo :: emit_macchwuo_r_r_r
|
|
inst_macchwuo_dot :: inst_macchwuo_dot_r_r_r
|
|
emit_macchwuo_dot :: emit_macchwuo_dot_r_r_r
|
|
inst_macchwo :: inst_macchwo_r_r_r
|
|
emit_macchwo :: emit_macchwo_r_r_r
|
|
inst_macchwo_dot :: inst_macchwo_dot_r_r_r
|
|
emit_macchwo_dot :: emit_macchwo_dot_r_r_r
|
|
inst_nmacchwo :: inst_nmacchwo_r_r_r
|
|
emit_nmacchwo :: emit_nmacchwo_r_r_r
|
|
inst_nmacchwo_dot :: inst_nmacchwo_dot_r_r_r
|
|
emit_nmacchwo_dot :: emit_nmacchwo_dot_r_r_r
|
|
inst_macchwsuo :: inst_macchwsuo_r_r_r
|
|
emit_macchwsuo :: emit_macchwsuo_r_r_r
|
|
inst_macchwsuo_dot :: inst_macchwsuo_dot_r_r_r
|
|
emit_macchwsuo_dot :: emit_macchwsuo_dot_r_r_r
|
|
inst_vcmpequq_dot :: inst_vcmpequq_dot_r_r_r
|
|
emit_vcmpequq_dot :: emit_vcmpequq_dot_r_r_r
|
|
inst_macchwso :: inst_macchwso_r_r_r
|
|
emit_macchwso :: emit_macchwso_r_r_r
|
|
inst_macchwso_dot :: inst_macchwso_dot_r_r_r
|
|
emit_macchwso_dot :: emit_macchwso_dot_r_r_r
|
|
inst_nmacchwso :: inst_nmacchwso_r_r_r
|
|
emit_nmacchwso :: emit_nmacchwso_r_r_r
|
|
inst_nmacchwso_dot :: inst_nmacchwso_dot_r_r_r
|
|
emit_nmacchwso_dot :: emit_nmacchwso_dot_r_r_r
|
|
inst_vcmpgtuq_dot :: inst_vcmpgtuq_dot_r_r_r
|
|
emit_vcmpgtuq_dot :: emit_vcmpgtuq_dot_r_r_r
|
|
inst_maclhwuo :: inst_maclhwuo_r_r_r
|
|
emit_maclhwuo :: emit_maclhwuo_r_r_r
|
|
inst_maclhwuo_dot :: inst_maclhwuo_dot_r_r_r
|
|
emit_maclhwuo_dot :: emit_maclhwuo_dot_r_r_r
|
|
inst_maclhwo :: inst_maclhwo_r_r_r
|
|
emit_maclhwo :: emit_maclhwo_r_r_r
|
|
inst_maclhwo_dot :: inst_maclhwo_dot_r_r_r
|
|
emit_maclhwo_dot :: emit_maclhwo_dot_r_r_r
|
|
inst_nmaclhwo :: inst_nmaclhwo_r_r_r
|
|
emit_nmaclhwo :: emit_nmaclhwo_r_r_r
|
|
inst_nmaclhwo_dot :: inst_nmaclhwo_dot_r_r_r
|
|
emit_nmaclhwo_dot :: emit_nmaclhwo_dot_r_r_r
|
|
inst_vcmpgtsq_dot :: inst_vcmpgtsq_dot_r_r_r
|
|
emit_vcmpgtsq_dot :: emit_vcmpgtsq_dot_r_r_r
|
|
inst_maclhwsuo :: inst_maclhwsuo_r_r_r
|
|
emit_maclhwsuo :: emit_maclhwsuo_r_r_r
|
|
inst_maclhwsuo_dot :: inst_maclhwsuo_dot_r_r_r
|
|
emit_maclhwsuo_dot :: emit_maclhwsuo_dot_r_r_r
|
|
inst_maclhwso :: inst_maclhwso_r_r_r
|
|
emit_maclhwso :: emit_maclhwso_r_r_r
|
|
inst_maclhwso_dot :: inst_maclhwso_dot_r_r_r
|
|
emit_maclhwso_dot :: emit_maclhwso_dot_r_r_r
|
|
inst_nmaclhwso :: inst_nmaclhwso_r_r_r
|
|
emit_nmaclhwso :: emit_nmaclhwso_r_r_r
|
|
inst_nmaclhwso_dot :: inst_nmaclhwso_dot_r_r_r
|
|
emit_nmaclhwso_dot :: emit_nmaclhwso_dot_r_r_r
|
|
inst_dcbz_l :: inst_dcbz_l_r_r_r
|
|
emit_dcbz_l :: emit_dcbz_l_r_r_r
|
|
inst_muli :: inst_muli_r_r_imm
|
|
emit_muli :: emit_muli_r_r_imm
|
|
inst_sfi :: inst_sfi_r_r_imm
|
|
emit_sfi :: emit_sfi_r_r_imm
|
|
inst_dozi :: inst_dozi_r_r_imm
|
|
emit_dozi :: emit_dozi_r_r_imm
|
|
inst_ai :: inst_ai_r_r_imm
|
|
emit_ai :: emit_ai_r_r_imm
|
|
inst_subic :: inst_subic_r_r_imm
|
|
emit_subic :: emit_subic_r_r_imm
|
|
inst_ai_dot :: inst_ai_dot_r_r_imm
|
|
emit_ai_dot :: emit_ai_dot_r_r_imm
|
|
inst_subic_dot :: inst_subic_dot_r_r_imm
|
|
emit_subic_dot :: emit_subic_dot_r_r_imm
|
|
inst_lil :: inst_lil_r_r_imm
|
|
emit_lil :: emit_lil_r_r_imm
|
|
inst_cal :: inst_cal_r_r_imm
|
|
emit_cal :: emit_cal_r_r_imm
|
|
inst_subi :: inst_subi_r_r_imm
|
|
emit_subi :: emit_subi_r_r_imm
|
|
inst_liu :: inst_liu_r_r_imm
|
|
emit_liu :: emit_liu_r_r_imm
|
|
inst_cau :: inst_cau_r_r_imm
|
|
emit_cau :: emit_cau_r_r_imm
|
|
inst_subis :: inst_subis_r_r_imm
|
|
emit_subis :: emit_subis_r_r_imm
|
|
inst_crnot :: inst_crnot_r_r_imm
|
|
emit_crnot :: emit_crnot_r_r_imm
|
|
inst_rfci :: inst_rfci_r_r_imm
|
|
emit_rfci :: emit_rfci_r_r_imm
|
|
inst_rfscv :: inst_rfscv_r_r_imm
|
|
emit_rfscv :: emit_rfscv_r_r_imm
|
|
inst_rfsvc :: inst_rfsvc_r_r_imm
|
|
emit_rfsvc :: emit_rfsvc_r_r_imm
|
|
inst_rfgi :: inst_rfgi_r_r_imm
|
|
emit_rfgi :: emit_rfgi_r_r_imm
|
|
inst_ics :: inst_ics_r_r_imm
|
|
emit_ics :: emit_ics_r_r_imm
|
|
inst_crclr :: inst_crclr_r_r_imm
|
|
emit_crclr :: emit_crclr_r_r_imm
|
|
inst_dnh :: inst_dnh_r_r_imm
|
|
emit_dnh :: emit_dnh_r_r_imm
|
|
inst_crset :: inst_crset_r_r_imm
|
|
emit_crset :: emit_crset_r_r_imm
|
|
inst_urfid :: inst_urfid_r_r_imm
|
|
emit_urfid :: emit_urfid_r_r_imm
|
|
inst_doze :: inst_doze_r_r_imm
|
|
emit_doze :: emit_doze_r_r_imm
|
|
inst_crmove :: inst_crmove_r_r_imm
|
|
emit_crmove :: emit_crmove_r_r_imm
|
|
inst_sleep :: inst_sleep_r_r_imm
|
|
emit_sleep :: emit_sleep_r_r_imm
|
|
inst_rvwinkle :: inst_rvwinkle_r_r_imm
|
|
emit_rvwinkle :: emit_rvwinkle_r_r_imm
|
|
inst_oril :: inst_oril_r_r_imm
|
|
emit_oril :: emit_oril_r_r_imm
|
|
inst_oriu :: inst_oriu_r_r_imm
|
|
emit_oriu :: emit_oriu_r_r_imm
|
|
inst_xoril :: inst_xoril_r_r_imm
|
|
emit_xoril :: emit_xoril_r_r_imm
|
|
inst_xoriu :: inst_xoriu_r_r_imm
|
|
emit_xoriu :: emit_xoriu_r_r_imm
|
|
inst_andil_dot :: inst_andil_dot_r_r_imm
|
|
emit_andil_dot :: emit_andil_dot_r_r_imm
|
|
inst_andiu_dot :: inst_andiu_dot_r_r_imm
|
|
emit_andiu_dot :: emit_andiu_dot_r_r_imm
|
|
inst_rotldi_dot :: inst_rotldi_dot_r_r_r
|
|
emit_rotldi_dot :: emit_rotldi_dot_r_r_r
|
|
inst_rotrdi_dot :: inst_rotrdi_dot_r_r_r
|
|
emit_rotrdi_dot :: emit_rotrdi_dot_r_r_r
|
|
inst_clrldi_dot :: inst_clrldi_dot_r_r_r
|
|
emit_clrldi_dot :: emit_clrldi_dot_r_r_r
|
|
inst_srdi_dot :: inst_srdi_dot_r_r_r
|
|
emit_srdi_dot :: emit_srdi_dot_r_r_r
|
|
inst_extrdi_dot :: inst_extrdi_dot_r_r_r
|
|
emit_extrdi_dot :: emit_extrdi_dot_r_r_r
|
|
inst_clrrdi_dot :: inst_clrrdi_dot_r_r_r
|
|
emit_clrrdi_dot :: emit_clrrdi_dot_r_r_r
|
|
inst_sldi_dot :: inst_sldi_dot_r_r_r
|
|
emit_sldi_dot :: emit_sldi_dot_r_r_r
|
|
inst_extldi_dot :: inst_extldi_dot_r_r_r
|
|
emit_extldi_dot :: emit_extldi_dot_r_r_r
|
|
inst_clrlsldi :: inst_clrlsldi_r_r_r
|
|
emit_clrlsldi :: emit_clrlsldi_r_r_r
|
|
inst_clrlsldi_dot :: inst_clrlsldi_dot_r_r_r
|
|
emit_clrlsldi_dot :: emit_clrlsldi_dot_r_r_r
|
|
inst_insrdi :: inst_insrdi_r_r_r
|
|
emit_insrdi :: emit_insrdi_r_r_r
|
|
inst_insrdi_dot :: inst_insrdi_dot_r_r_r
|
|
emit_insrdi_dot :: emit_insrdi_dot_r_r_r
|
|
inst_rotld_dot :: inst_rotld_dot_r_r_r
|
|
emit_rotld_dot :: emit_rotld_dot_r_r_r
|
|
inst_t :: inst_t_r_r_r
|
|
emit_t :: emit_t_r_r_r
|
|
inst_sf :: inst_sf_r_r_r
|
|
emit_sf :: emit_sf_r_r_r
|
|
inst_sf_dot :: inst_sf_dot_r_r_r
|
|
emit_sf_dot :: emit_sf_dot_r_r_r
|
|
inst_a_dot :: inst_a_dot_r_r_r
|
|
emit_a_dot :: emit_a_dot_r_r_r
|
|
inst_lx :: inst_lx_r_r_r
|
|
emit_lx :: emit_lx_r_r_r
|
|
inst_sl :: inst_sl_r_r_r
|
|
emit_sl :: emit_sl_r_r_r
|
|
inst_sl_dot :: inst_sl_dot_r_r_r
|
|
emit_sl_dot :: emit_sl_dot_r_r_r
|
|
inst_cntlz :: inst_cntlz_r_r_r
|
|
emit_cntlz :: emit_cntlz_r_r_r
|
|
inst_cntlz_dot :: inst_cntlz_dot_r_r_r
|
|
emit_cntlz_dot :: emit_cntlz_dot_r_r_r
|
|
inst_maskg :: inst_maskg_r_r_r
|
|
emit_maskg :: emit_maskg_r_r_r
|
|
inst_maskg_dot :: inst_maskg_dot_r_r_r
|
|
emit_maskg_dot :: emit_maskg_dot_r_r_r
|
|
inst_ldepx :: inst_ldepx_r_r_r
|
|
emit_ldepx :: emit_ldepx_r_r_r
|
|
inst_waitasec :: inst_waitasec_r_r_r
|
|
emit_waitasec :: emit_waitasec_r_r_r
|
|
inst_mviwsplt :: inst_mviwsplt_r_r_r
|
|
emit_mviwsplt :: emit_mviwsplt_r_r_r
|
|
inst_mfvsrd :: inst_mfvsrd_r_r_r
|
|
emit_mfvsrd :: emit_mfvsrd_r_r_r
|
|
inst_eratilx :: inst_eratilx_r_r_r
|
|
emit_eratilx :: emit_eratilx_r_r_r
|
|
inst_lux :: inst_lux_r_r_r
|
|
emit_lux :: emit_lux_r_r_r
|
|
inst_subwus :: inst_subwus_r_r_r
|
|
emit_subwus :: emit_subwus_r_r_r
|
|
inst_subwus_dot :: inst_subwus_dot_r_r_r
|
|
emit_subwus_dot :: emit_subwus_dot_r_r_r
|
|
inst_subdus :: inst_subdus_r_r_r
|
|
emit_subdus :: emit_subdus_r_r_r
|
|
inst_subdus_dot :: inst_subdus_dot_r_r_r
|
|
emit_subdus_dot :: emit_subdus_dot_r_r_r
|
|
inst_subfus :: inst_subfus_r_r_r
|
|
emit_subfus :: emit_subfus_r_r_r
|
|
inst_subfus_dot :: inst_subfus_dot_r_r_r
|
|
emit_subfus_dot :: emit_subfus_dot_r_r_r
|
|
inst_dlmzb :: inst_dlmzb_r_r_r
|
|
emit_dlmzb :: emit_dlmzb_r_r_r
|
|
inst_dlmzb_dot :: inst_dlmzb_dot_r_r_r
|
|
emit_dlmzb_dot :: emit_dlmzb_dot_r_r_r
|
|
inst_dni :: inst_dni_r_r_r
|
|
emit_dni :: emit_dni_r_r_r
|
|
inst_mul :: inst_mul_r_r_r
|
|
emit_mul :: emit_mul_r_r_r
|
|
inst_mul_dot :: inst_mul_dot_r_r_r
|
|
emit_mul_dot :: emit_mul_dot_r_r_r
|
|
inst_mvidsplt :: inst_mvidsplt_r_r_r
|
|
emit_mvidsplt :: emit_mvidsplt_r_r_r
|
|
inst_mtsrdin :: inst_mtsrdin_r_r_r
|
|
emit_mtsrdin :: emit_mtsrdin_r_r_r
|
|
inst_mfvsrwz :: inst_mfvsrwz_r_r_r
|
|
emit_mfvsrwz :: emit_mfvsrwz_r_r_r
|
|
inst_clf :: inst_clf_r_r_r
|
|
emit_clf :: emit_clf_r_r_r
|
|
inst_dcbtstls :: inst_dcbtstls_r_r_r
|
|
emit_dcbtstls :: emit_dcbtstls_r_r_r
|
|
inst_sfe :: inst_sfe_r_r_r
|
|
emit_sfe :: emit_sfe_r_r_r
|
|
inst_sfe_dot :: inst_sfe_dot_r_r_r
|
|
emit_sfe_dot :: emit_sfe_dot_r_r_r
|
|
inst_ae :: inst_ae_r_r_r
|
|
emit_ae :: emit_ae_r_r_r
|
|
inst_ae_dot :: inst_ae_dot_r_r_r
|
|
emit_ae_dot :: emit_ae_dot_r_r_r
|
|
inst_dcbtstlse :: inst_dcbtstlse_r_r_r
|
|
emit_dcbtstlse :: emit_dcbtstlse_r_r_r
|
|
inst_mtsle :: inst_mtsle_r_r_r
|
|
emit_mtsle :: emit_mtsle_r_r_r
|
|
inst_eratsx :: inst_eratsx_r_r_r
|
|
emit_eratsx :: emit_eratsx_r_r_r
|
|
inst_eratsx_dot :: inst_eratsx_dot_r_r_r
|
|
emit_eratsx_dot :: emit_eratsx_dot_r_r_r
|
|
inst_stx :: inst_stx_r_r_r
|
|
emit_stx :: emit_stx_r_r_r
|
|
inst_slq :: inst_slq_r_r_r
|
|
emit_slq :: emit_slq_r_r_r
|
|
inst_slq_dot :: inst_slq_dot_r_r_r
|
|
emit_slq_dot :: emit_slq_dot_r_r_r
|
|
inst_sle :: inst_sle_r_r_r
|
|
emit_sle :: emit_sle_r_r_r
|
|
inst_sle_dot :: inst_sle_dot_r_r_r
|
|
emit_sle_dot :: emit_sle_dot_r_r_r
|
|
inst_stdepx :: inst_stdepx_r_r_r
|
|
emit_stdepx :: emit_stdepx_r_r_r
|
|
inst_dcbtls :: inst_dcbtls_r_r_r
|
|
emit_dcbtls :: emit_dcbtls_r_r_r
|
|
inst_dcbtlse :: inst_dcbtlse_r_r_r
|
|
emit_dcbtlse :: emit_dcbtlse_r_r_r
|
|
inst_mtvsrd :: inst_mtvsrd_r_r_r
|
|
emit_mtvsrd :: emit_mtvsrd_r_r_r
|
|
inst_eratre :: inst_eratre_r_r_r
|
|
emit_eratre :: emit_eratre_r_r_r
|
|
inst_wchkall :: inst_wchkall_r_r_r
|
|
emit_wchkall :: emit_wchkall_r_r_r
|
|
inst_stux :: inst_stux_r_r_r
|
|
emit_stux :: emit_stux_r_r_r
|
|
inst_sliq :: inst_sliq_r_r_r
|
|
emit_sliq :: emit_sliq_r_r_r
|
|
inst_sliq_dot :: inst_sliq_dot_r_r_r
|
|
emit_sliq_dot :: emit_sliq_dot_r_r_r
|
|
inst_icblq_dot :: inst_icblq_dot_r_r_r
|
|
emit_icblq_dot :: emit_icblq_dot_r_r_r
|
|
inst_sfze :: inst_sfze_r_r_r
|
|
emit_sfze :: emit_sfze_r_r_r
|
|
inst_sfze_dot :: inst_sfze_dot_r_r_r
|
|
emit_sfze_dot :: emit_sfze_dot_r_r_r
|
|
inst_aze :: inst_aze_r_r_r
|
|
emit_aze :: emit_aze_r_r_r
|
|
inst_aze_dot :: inst_aze_dot_r_r_r
|
|
emit_aze_dot :: emit_aze_dot_r_r_r
|
|
inst_mtvsrwa :: inst_mtvsrwa_r_r_r
|
|
emit_mtvsrwa :: emit_mtvsrwa_r_r_r
|
|
inst_eratwe :: inst_eratwe_r_r_r
|
|
emit_eratwe :: emit_eratwe_r_r_r
|
|
inst_ldawx_dot :: inst_ldawx_dot_r_r_r
|
|
emit_ldawx_dot :: emit_ldawx_dot_r_r_r
|
|
inst_sllq :: inst_sllq_r_r_r
|
|
emit_sllq :: emit_sllq_r_r_r
|
|
inst_sllq_dot :: inst_sllq_dot_r_r_r
|
|
emit_sllq_dot :: emit_sllq_dot_r_r_r
|
|
inst_sleq :: inst_sleq_r_r_r
|
|
emit_sleq :: emit_sleq_r_r_r
|
|
inst_sleq_dot :: inst_sleq_dot_r_r_r
|
|
emit_sleq_dot :: emit_sleq_dot_r_r_r
|
|
inst_sfme :: inst_sfme_r_r_r
|
|
emit_sfme :: emit_sfme_r_r_r
|
|
inst_sfme_dot :: inst_sfme_dot_r_r_r
|
|
emit_sfme_dot :: emit_sfme_dot_r_r_r
|
|
inst_ame :: inst_ame_r_r_r
|
|
emit_ame :: emit_ame_r_r_r
|
|
inst_ame_dot :: inst_ame_dot_r_r_r
|
|
emit_ame_dot :: emit_ame_dot_r_r_r
|
|
inst_muls :: inst_muls_r_r_r
|
|
emit_muls :: emit_muls_r_r_r
|
|
inst_muls_dot :: inst_muls_dot_r_r_r
|
|
emit_muls_dot :: emit_muls_dot_r_r_r
|
|
inst_icblce :: inst_icblce_r_r_r
|
|
emit_icblce :: emit_icblce_r_r_r
|
|
inst_mtsri :: inst_mtsri_r_r_r
|
|
emit_mtsri :: emit_mtsri_r_r_r
|
|
inst_mtvsrwz :: inst_mtvsrwz_r_r_r
|
|
emit_mtvsrwz :: emit_mtvsrwz_r_r_r
|
|
inst_dcbtstct :: inst_dcbtstct_r_r_r
|
|
emit_dcbtstct :: emit_dcbtstct_r_r_r
|
|
inst_dcbtstds :: inst_dcbtstds_r_r_r
|
|
emit_dcbtstds :: emit_dcbtstds_r_r_r
|
|
inst_slliq :: inst_slliq_r_r_r
|
|
emit_slliq :: emit_slliq_r_r_r
|
|
inst_slliq_dot :: inst_slliq_dot_r_r_r
|
|
emit_slliq_dot :: emit_slliq_dot_r_r_r
|
|
inst_mfdcrx :: inst_mfdcrx_r_r_r
|
|
emit_mfdcrx :: emit_mfdcrx_r_r_r
|
|
inst_mfdcrx_dot :: inst_mfdcrx_dot_r_r_r
|
|
emit_mfdcrx_dot :: emit_mfdcrx_dot_r_r_r
|
|
inst_lvexbx :: inst_lvexbx_r_r_r
|
|
emit_lvexbx :: emit_lvexbx_r_r_r
|
|
inst_lvepxl :: inst_lvepxl_r_r_r
|
|
emit_lvepxl :: emit_lvepxl_r_r_r
|
|
inst_doz :: inst_doz_r_r_r
|
|
emit_doz :: emit_doz_r_r_r
|
|
inst_doz_dot :: inst_doz_dot_r_r_r
|
|
emit_doz_dot :: emit_doz_dot_r_r_r
|
|
inst_cax :: inst_cax_r_r_r
|
|
emit_cax :: emit_cax_r_r_r
|
|
inst_cax_dot :: inst_cax_dot_r_r_r
|
|
emit_cax_dot :: emit_cax_dot_r_r_r
|
|
inst_ehpriv :: inst_ehpriv_r_r_r
|
|
emit_ehpriv :: emit_ehpriv_r_r_r
|
|
inst_mfapidi :: inst_mfapidi_r_r_r
|
|
emit_mfapidi :: emit_mfapidi_r_r_r
|
|
inst_lscbx :: inst_lscbx_r_r_r
|
|
emit_lscbx :: emit_lscbx_r_r_r
|
|
inst_lscbx_dot :: inst_lscbx_dot_r_r_r
|
|
emit_lscbx_dot :: emit_lscbx_dot_r_r_r
|
|
inst_dcbtct :: inst_dcbtct_r_r_r
|
|
emit_dcbtct :: emit_dcbtct_r_r_r
|
|
inst_dcbtds :: inst_dcbtds_r_r_r
|
|
emit_dcbtds :: emit_dcbtds_r_r_r
|
|
inst_mfdcrux :: inst_mfdcrux_r_r_r
|
|
emit_mfdcrux :: emit_mfdcrux_r_r_r
|
|
inst_lvexhx :: inst_lvexhx_r_r_r
|
|
emit_lvexhx :: emit_lvexhx_r_r_r
|
|
inst_lvepx :: inst_lvepx_r_r_r
|
|
emit_lvepx :: emit_lvepx_r_r_r
|
|
inst_mfbhrbe :: inst_mfbhrbe_r_r_r
|
|
emit_mfbhrbe :: emit_mfbhrbe_r_r_r
|
|
inst_tlbi :: inst_tlbi_r_r_r
|
|
emit_tlbi :: emit_tlbi_r_r_r
|
|
inst_eciwx :: inst_eciwx_r_r_r
|
|
emit_eciwx :: emit_eciwx_r_r_r
|
|
inst_mfdcr_dot :: inst_mfdcr_dot_r_r_r
|
|
emit_mfdcr_dot :: emit_mfdcr_dot_r_r_r
|
|
inst_lvexwx :: inst_lvexwx_r_r_r
|
|
emit_lvexwx :: emit_lvexwx_r_r_r
|
|
inst_dcread :: inst_dcread_r_r_r
|
|
emit_dcread :: emit_dcread_r_r_r
|
|
inst_div :: inst_div_r_r_r
|
|
emit_div :: emit_div_r_r_r
|
|
inst_div_dot :: inst_div_dot_r_r_r
|
|
emit_div_dot :: emit_div_dot_r_r_r
|
|
inst_mftmr :: inst_mftmr_r_r_r
|
|
emit_mftmr :: emit_mftmr_r_r_r
|
|
inst_abs :: inst_abs_r_r_r
|
|
emit_abs :: emit_abs_r_r_r
|
|
inst_abs_dot :: inst_abs_dot_r_r_r
|
|
emit_abs_dot :: emit_abs_dot_r_r_r
|
|
inst_divs :: inst_divs_r_r_r
|
|
emit_divs :: emit_divs_r_r_r
|
|
inst_divs_dot :: inst_divs_dot_r_r_r
|
|
emit_divs_dot :: emit_divs_dot_r_r_r
|
|
inst_lxvwsx :: inst_lxvwsx_r_r_r
|
|
emit_lxvwsx :: emit_lxvwsx_r_r_r
|
|
inst_tlbia :: inst_tlbia_r_r_r
|
|
emit_tlbia :: emit_tlbia_r_r_r
|
|
inst_setbc :: inst_setbc_r_r_r
|
|
emit_setbc :: emit_setbc_r_r_r
|
|
inst_mtdcrx :: inst_mtdcrx_r_r_r
|
|
emit_mtdcrx :: emit_mtdcrx_r_r_r
|
|
inst_mtdcrx_dot :: inst_mtdcrx_dot_r_r_r
|
|
emit_mtdcrx_dot :: emit_mtdcrx_dot_r_r_r
|
|
inst_stvexbx :: inst_stvexbx_r_r_r
|
|
emit_stvexbx :: emit_stvexbx_r_r_r
|
|
inst_dcblc :: inst_dcblc_r_r_r
|
|
emit_dcblc :: emit_dcblc_r_r_r
|
|
inst_dcblce :: inst_dcblce_r_r_r
|
|
emit_dcblce :: emit_dcblce_r_r_r
|
|
inst_pbt_dot :: inst_pbt_dot_r_r_r
|
|
emit_pbt_dot :: emit_pbt_dot_r_r_r
|
|
inst_icswx :: inst_icswx_r_r_r
|
|
emit_icswx :: emit_icswx_r_r_r
|
|
inst_icswx_dot :: inst_icswx_dot_r_r_r
|
|
emit_icswx_dot :: emit_icswx_dot_r_r_r
|
|
inst_setbcr :: inst_setbcr_r_r_r
|
|
emit_setbcr :: emit_setbcr_r_r_r
|
|
inst_mtdcrux :: inst_mtdcrux_r_r_r
|
|
emit_mtdcrux :: emit_mtdcrux_r_r_r
|
|
inst_stvexhx :: inst_stvexhx_r_r_r
|
|
emit_stvexhx :: emit_stvexhx_r_r_r
|
|
inst_dcblq_dot :: inst_dcblq_dot_r_r_r
|
|
emit_dcblq_dot :: emit_dcblq_dot_r_r_r
|
|
inst_clrbhrb :: inst_clrbhrb_r_r_r
|
|
emit_clrbhrb :: emit_clrbhrb_r_r_r
|
|
inst_ecowx :: inst_ecowx_r_r_r
|
|
emit_ecowx :: emit_ecowx_r_r_r
|
|
inst_setnbc :: inst_setnbc_r_r_r
|
|
emit_setnbc :: emit_setnbc_r_r_r
|
|
inst_mtdcr_dot :: inst_mtdcr_dot_r_r_r
|
|
emit_mtdcr_dot :: emit_mtdcr_dot_r_r_r
|
|
inst_stvexwx :: inst_stvexwx_r_r_r
|
|
emit_stvexwx :: emit_stvexwx_r_r_r
|
|
inst_dci :: inst_dci_r_r_r
|
|
emit_dci :: emit_dci_r_r_r
|
|
inst_mttmr :: inst_mttmr_r_r_r
|
|
emit_mttmr :: emit_mttmr_r_r_r
|
|
inst_setnbcr :: inst_setnbcr_r_r_r
|
|
emit_setnbcr :: emit_setnbcr_r_r_r
|
|
inst_dsn :: inst_dsn_r_r_r
|
|
emit_dsn :: emit_dsn_r_r_r
|
|
inst_nabs :: inst_nabs_r_r_r
|
|
emit_nabs :: emit_nabs_r_r_r
|
|
inst_nabs_dot :: inst_nabs_dot_r_r_r
|
|
emit_nabs_dot :: emit_nabs_dot_r_r_r
|
|
inst_icbtlse :: inst_icbtlse_r_r_r
|
|
emit_icbtlse :: emit_icbtlse_r_r_r
|
|
inst_cli :: inst_cli_r_r_r
|
|
emit_cli :: emit_cli_r_r_r
|
|
inst_mcrxr :: inst_mcrxr_r_r_r
|
|
emit_mcrxr :: emit_mcrxr_r_r_r
|
|
inst_lbdcbx :: inst_lbdcbx_r_r_r
|
|
emit_lbdcbx :: emit_lbdcbx_r_r_r
|
|
inst_lbdx :: inst_lbdx_r_r_r
|
|
emit_lbdx :: emit_lbdx_r_r_r
|
|
inst_bblels :: inst_bblels_r_r_r
|
|
emit_bblels :: emit_bblels_r_r_r
|
|
inst_lvlx :: inst_lvlx_r_r_r
|
|
emit_lvlx :: emit_lvlx_r_r_r
|
|
inst_subfco :: inst_subfco_r_r_r
|
|
emit_subfco :: emit_subfco_r_r_r
|
|
inst_sfo :: inst_sfo_r_r_r
|
|
emit_sfo :: emit_sfo_r_r_r
|
|
inst_subco :: inst_subco_r_r_r
|
|
emit_subco :: emit_subco_r_r_r
|
|
inst_subfco_dot :: inst_subfco_dot_r_r_r
|
|
emit_subfco_dot :: emit_subfco_dot_r_r_r
|
|
inst_sfo_dot :: inst_sfo_dot_r_r_r
|
|
emit_sfo_dot :: emit_sfo_dot_r_r_r
|
|
inst_subco_dot :: inst_subco_dot_r_r_r
|
|
emit_subco_dot :: emit_subco_dot_r_r_r
|
|
inst_addco :: inst_addco_r_r_r
|
|
emit_addco :: emit_addco_r_r_r
|
|
inst_ao :: inst_ao_r_r_r
|
|
emit_ao :: emit_ao_r_r_r
|
|
inst_addco_dot :: inst_addco_dot_r_r_r
|
|
emit_addco_dot :: emit_addco_dot_r_r_r
|
|
inst_ao_dot :: inst_ao_dot_r_r_r
|
|
emit_ao_dot :: emit_ao_dot_r_r_r
|
|
inst_clcs :: inst_clcs_r_r_r
|
|
emit_clcs :: emit_clcs_r_r_r
|
|
inst_lsx :: inst_lsx_r_r_r
|
|
emit_lsx :: emit_lsx_r_r_r
|
|
inst_lbrx :: inst_lbrx_r_r_r
|
|
emit_lbrx :: emit_lbrx_r_r_r
|
|
inst_sr_dot :: inst_sr_dot_r_r_r
|
|
emit_sr_dot :: emit_sr_dot_r_r_r
|
|
inst_rrib :: inst_rrib_r_r_r
|
|
emit_rrib :: emit_rrib_r_r_r
|
|
inst_rrib_dot :: inst_rrib_dot_r_r_r
|
|
emit_rrib_dot :: emit_rrib_dot_r_r_r
|
|
inst_maskir :: inst_maskir_r_r_r
|
|
emit_maskir :: emit_maskir_r_r_r
|
|
inst_maskir_dot :: inst_maskir_dot_r_r_r
|
|
emit_maskir_dot :: emit_maskir_dot_r_r_r
|
|
inst_lhdcbx :: inst_lhdcbx_r_r_r
|
|
emit_lhdcbx :: emit_lhdcbx_r_r_r
|
|
inst_lhdx :: inst_lhdx_r_r_r
|
|
emit_lhdx :: emit_lhdx_r_r_r
|
|
inst_lvtrx :: inst_lvtrx_r_r_r
|
|
emit_lvtrx :: emit_lvtrx_r_r_r
|
|
inst_bbelr :: inst_bbelr_r_r_r
|
|
emit_bbelr :: emit_bbelr_r_r_r
|
|
inst_lvrx :: inst_lvrx_r_r_r
|
|
emit_lvrx :: emit_lvrx_r_r_r
|
|
inst_subfo :: inst_subfo_r_r_r
|
|
emit_subfo :: emit_subfo_r_r_r
|
|
inst_subo :: inst_subo_r_r_r
|
|
emit_subo :: emit_subo_r_r_r
|
|
inst_subfo_dot :: inst_subfo_dot_r_r_r
|
|
emit_subfo_dot :: emit_subfo_dot_r_r_r
|
|
inst_subo_dot :: inst_subo_dot_r_r_r
|
|
emit_subo_dot :: emit_subo_dot_r_r_r
|
|
inst_lwdcbx :: inst_lwdcbx_r_r_r
|
|
emit_lwdcbx :: emit_lwdcbx_r_r_r
|
|
inst_lwdx :: inst_lwdx_r_r_r
|
|
emit_lwdx :: emit_lwdx_r_r_r
|
|
inst_lvtlx :: inst_lvtlx_r_r_r
|
|
emit_lvtlx :: emit_lvtlx_r_r_r
|
|
inst_lsi :: inst_lsi_r_r_r
|
|
emit_lsi :: emit_lsi_r_r_r
|
|
inst_dcs :: inst_dcs_r_r_r
|
|
emit_dcs :: emit_dcs_r_r_r
|
|
inst_mffgpr :: inst_mffgpr_r_r_r
|
|
emit_mffgpr :: emit_mffgpr_r_r_r
|
|
inst_lddx :: inst_lddx_r_r_r
|
|
emit_lddx :: emit_lddx_r_r_r
|
|
inst_lvswx :: inst_lvswx_r_r_r
|
|
emit_lvswx :: emit_lvswx_r_r_r
|
|
inst_nego :: inst_nego_r_r_r
|
|
emit_nego :: emit_nego_r_r_r
|
|
inst_nego_dot :: inst_nego_dot_r_r_r
|
|
emit_nego_dot :: emit_nego_dot_r_r_r
|
|
inst_mulo :: inst_mulo_r_r_r
|
|
emit_mulo :: emit_mulo_r_r_r
|
|
inst_mulo_dot :: inst_mulo_dot_r_r_r
|
|
emit_mulo_dot :: emit_mulo_dot_r_r_r
|
|
inst_mfsri :: inst_mfsri_r_r_r
|
|
emit_mfsri :: emit_mfsri_r_r_r
|
|
inst_dclst :: inst_dclst_r_r_r
|
|
emit_dclst :: emit_dclst_r_r_r
|
|
inst_stbdcbx :: inst_stbdcbx_r_r_r
|
|
emit_stbdcbx :: emit_stbdcbx_r_r_r
|
|
inst_stbdx :: inst_stbdx_r_r_r
|
|
emit_stbdx :: emit_stbdx_r_r_r
|
|
inst_stvlx :: inst_stvlx_r_r_r
|
|
emit_stvlx :: emit_stvlx_r_r_r
|
|
inst_subfeo :: inst_subfeo_r_r_r
|
|
emit_subfeo :: emit_subfeo_r_r_r
|
|
inst_sfeo :: inst_sfeo_r_r_r
|
|
emit_sfeo :: emit_sfeo_r_r_r
|
|
inst_subfeo_dot :: inst_subfeo_dot_r_r_r
|
|
emit_subfeo_dot :: emit_subfeo_dot_r_r_r
|
|
inst_sfeo_dot :: inst_sfeo_dot_r_r_r
|
|
emit_sfeo_dot :: emit_sfeo_dot_r_r_r
|
|
inst_addeo :: inst_addeo_r_r_r
|
|
emit_addeo :: emit_addeo_r_r_r
|
|
inst_aeo :: inst_aeo_r_r_r
|
|
emit_aeo :: emit_aeo_r_r_r
|
|
inst_addeo_dot :: inst_addeo_dot_r_r_r
|
|
emit_addeo_dot :: emit_addeo_dot_r_r_r
|
|
inst_aeo_dot :: inst_aeo_dot_r_r_r
|
|
emit_aeo_dot :: emit_aeo_dot_r_r_r
|
|
inst_hashstp :: inst_hashstp_r_r_r
|
|
emit_hashstp :: emit_hashstp_r_r_r
|
|
inst_stsx :: inst_stsx_r_r_r
|
|
emit_stsx :: emit_stsx_r_r_r
|
|
inst_stbrx :: inst_stbrx_r_r_r
|
|
emit_stbrx :: emit_stbrx_r_r_r
|
|
inst_srq :: inst_srq_r_r_r
|
|
emit_srq :: emit_srq_r_r_r
|
|
inst_srq_dot :: inst_srq_dot_r_r_r
|
|
emit_srq_dot :: emit_srq_dot_r_r_r
|
|
inst_sre :: inst_sre_r_r_r
|
|
emit_sre :: emit_sre_r_r_r
|
|
inst_sre_dot :: inst_sre_dot_r_r_r
|
|
emit_sre_dot :: emit_sre_dot_r_r_r
|
|
inst_sthdcbx :: inst_sthdcbx_r_r_r
|
|
emit_sthdcbx :: emit_sthdcbx_r_r_r
|
|
inst_sthdx :: inst_sthdx_r_r_r
|
|
emit_sthdx :: emit_sthdx_r_r_r
|
|
inst_stvfrx :: inst_stvfrx_r_r_r
|
|
emit_stvfrx :: emit_stvfrx_r_r_r
|
|
inst_stvrx :: inst_stvrx_r_r_r
|
|
emit_stvrx :: emit_stvrx_r_r_r
|
|
inst_hashchkp :: inst_hashchkp_r_r_r
|
|
emit_hashchkp :: emit_hashchkp_r_r_r
|
|
inst_sriq :: inst_sriq_r_r_r
|
|
emit_sriq :: emit_sriq_r_r_r
|
|
inst_sriq_dot :: inst_sriq_dot_r_r_r
|
|
emit_sriq_dot :: emit_sriq_dot_r_r_r
|
|
inst_stwdcbx :: inst_stwdcbx_r_r_r
|
|
emit_stwdcbx :: emit_stwdcbx_r_r_r
|
|
inst_stwdx :: inst_stwdx_r_r_r
|
|
emit_stwdx :: emit_stwdx_r_r_r
|
|
inst_stvflx :: inst_stvflx_r_r_r
|
|
emit_stvflx :: emit_stvflx_r_r_r
|
|
inst_subfzeo :: inst_subfzeo_r_r_r
|
|
emit_subfzeo :: emit_subfzeo_r_r_r
|
|
inst_sfzeo :: inst_sfzeo_r_r_r
|
|
emit_sfzeo :: emit_sfzeo_r_r_r
|
|
inst_subfzeo_dot :: inst_subfzeo_dot_r_r_r
|
|
emit_subfzeo_dot :: emit_subfzeo_dot_r_r_r
|
|
inst_sfzeo_dot :: inst_sfzeo_dot_r_r_r
|
|
emit_sfzeo_dot :: emit_sfzeo_dot_r_r_r
|
|
inst_addzeo :: inst_addzeo_r_r_r
|
|
emit_addzeo :: emit_addzeo_r_r_r
|
|
inst_azeo :: inst_azeo_r_r_r
|
|
emit_azeo :: emit_azeo_r_r_r
|
|
inst_addzeo_dot :: inst_addzeo_dot_r_r_r
|
|
emit_addzeo_dot :: emit_addzeo_dot_r_r_r
|
|
inst_azeo_dot :: inst_azeo_dot_r_r_r
|
|
emit_azeo_dot :: emit_azeo_dot_r_r_r
|
|
inst_hashst :: inst_hashst_r_r_r
|
|
emit_hashst :: emit_hashst_r_r_r
|
|
inst_stsi :: inst_stsi_r_r_r
|
|
emit_stsi :: emit_stsi_r_r_r
|
|
inst_srlq :: inst_srlq_r_r_r
|
|
emit_srlq :: emit_srlq_r_r_r
|
|
inst_srlq_dot :: inst_srlq_dot_r_r_r
|
|
emit_srlq_dot :: emit_srlq_dot_r_r_r
|
|
inst_sreq :: inst_sreq_r_r_r
|
|
emit_sreq :: emit_sreq_r_r_r
|
|
inst_sreq_dot :: inst_sreq_dot_r_r_r
|
|
emit_sreq_dot :: emit_sreq_dot_r_r_r
|
|
inst_mftgpr :: inst_mftgpr_r_r_r
|
|
emit_mftgpr :: emit_mftgpr_r_r_r
|
|
inst_stddx :: inst_stddx_r_r_r
|
|
emit_stddx :: emit_stddx_r_r_r
|
|
inst_stvswx :: inst_stvswx_r_r_r
|
|
emit_stvswx :: emit_stvswx_r_r_r
|
|
inst_subfmeo :: inst_subfmeo_r_r_r
|
|
emit_subfmeo :: emit_subfmeo_r_r_r
|
|
inst_sfmeo :: inst_sfmeo_r_r_r
|
|
emit_sfmeo :: emit_sfmeo_r_r_r
|
|
inst_subfmeo_dot :: inst_subfmeo_dot_r_r_r
|
|
emit_subfmeo_dot :: emit_subfmeo_dot_r_r_r
|
|
inst_sfmeo_dot :: inst_sfmeo_dot_r_r_r
|
|
emit_sfmeo_dot :: emit_sfmeo_dot_r_r_r
|
|
inst_mulldo :: inst_mulldo_r_r_r
|
|
emit_mulldo :: emit_mulldo_r_r_r
|
|
inst_mulldo_dot :: inst_mulldo_dot_r_r_r
|
|
emit_mulldo_dot :: emit_mulldo_dot_r_r_r
|
|
inst_addmeo :: inst_addmeo_r_r_r
|
|
emit_addmeo :: emit_addmeo_r_r_r
|
|
inst_ameo :: inst_ameo_r_r_r
|
|
emit_ameo :: emit_ameo_r_r_r
|
|
inst_addmeo_dot :: inst_addmeo_dot_r_r_r
|
|
emit_addmeo_dot :: emit_addmeo_dot_r_r_r
|
|
inst_ameo_dot :: inst_ameo_dot_r_r_r
|
|
emit_ameo_dot :: emit_ameo_dot_r_r_r
|
|
inst_mullwo :: inst_mullwo_r_r_r
|
|
emit_mullwo :: emit_mullwo_r_r_r
|
|
inst_mulso :: inst_mulso_r_r_r
|
|
emit_mulso :: emit_mulso_r_r_r
|
|
inst_mullwo_dot :: inst_mullwo_dot_r_r_r
|
|
emit_mullwo_dot :: emit_mullwo_dot_r_r_r
|
|
inst_mulso_dot :: inst_mulso_dot_r_r_r
|
|
emit_mulso_dot :: emit_mulso_dot_r_r_r
|
|
inst_tsr_dot :: inst_tsr_dot_r_r_r
|
|
emit_tsr_dot :: emit_tsr_dot_r_r_r
|
|
inst_hashchk :: inst_hashchk_r_r_r
|
|
emit_hashchk :: emit_hashchk_r_r_r
|
|
inst_srliq :: inst_srliq_r_r_r
|
|
emit_srliq :: emit_srliq_r_r_r
|
|
inst_srliq_dot :: inst_srliq_dot_r_r_r
|
|
emit_srliq_dot :: emit_srliq_dot_r_r_r
|
|
inst_lvsm :: inst_lvsm_r_r_r
|
|
emit_lvsm :: emit_lvsm_r_r_r
|
|
inst_stvepxl :: inst_stvepxl_r_r_r
|
|
emit_stvepxl :: emit_stvepxl_r_r_r
|
|
inst_lvlxl :: inst_lvlxl_r_r_r
|
|
emit_lvlxl :: emit_lvlxl_r_r_r
|
|
inst_dozo :: inst_dozo_r_r_r
|
|
emit_dozo :: emit_dozo_r_r_r
|
|
inst_dozo_dot :: inst_dozo_dot_r_r_r
|
|
emit_dozo_dot :: emit_dozo_dot_r_r_r
|
|
inst_addo :: inst_addo_r_r_r
|
|
emit_addo :: emit_addo_r_r_r
|
|
inst_caxo :: inst_caxo_r_r_r
|
|
emit_caxo :: emit_caxo_r_r_r
|
|
inst_addo_dot :: inst_addo_dot_r_r_r
|
|
emit_addo_dot :: emit_addo_dot_r_r_r
|
|
inst_caxo_dot :: inst_caxo_dot_r_r_r
|
|
emit_caxo_dot :: emit_caxo_dot_r_r_r
|
|
inst_lfqx :: inst_lfqx_r_r_r
|
|
emit_lfqx :: emit_lfqx_r_r_r
|
|
inst_sra :: inst_sra_r_r_r
|
|
emit_sra :: emit_sra_r_r_r
|
|
inst_sra_dot :: inst_sra_dot_r_r_r
|
|
emit_sra_dot :: emit_sra_dot_r_r_r
|
|
inst_evlddepx :: inst_evlddepx_r_r_r
|
|
emit_evlddepx :: emit_evlddepx_r_r_r
|
|
inst_lfddx :: inst_lfddx_r_r_r
|
|
emit_lfddx :: emit_lfddx_r_r_r
|
|
inst_lvtrxl :: inst_lvtrxl_r_r_r
|
|
emit_lvtrxl :: emit_lvtrxl_r_r_r
|
|
inst_stvepx :: inst_stvepx_r_r_r
|
|
emit_stvepx :: emit_stvepx_r_r_r
|
|
inst_lvrxl :: inst_lvrxl_r_r_r
|
|
emit_lvrxl :: emit_lvrxl_r_r_r
|
|
inst_rac :: inst_rac_r_r_r
|
|
emit_rac :: emit_rac_r_r_r
|
|
inst_erativax :: inst_erativax_r_r_r
|
|
emit_erativax :: emit_erativax_r_r_r
|
|
inst_lfqux :: inst_lfqux_r_r_r
|
|
emit_lfqux :: emit_lfqux_r_r_r
|
|
inst_srai :: inst_srai_r_r_r
|
|
emit_srai :: emit_srai_r_r_r
|
|
inst_srai_dot :: inst_srai_dot_r_r_r
|
|
emit_srai_dot :: emit_srai_dot_r_r_r
|
|
inst_lvtlxl :: inst_lvtlxl_r_r_r
|
|
emit_lvtlxl :: emit_lvtlxl_r_r_r
|
|
inst_divo :: inst_divo_r_r_r
|
|
emit_divo :: emit_divo_r_r_r
|
|
inst_divo_dot :: inst_divo_dot_r_r_r
|
|
emit_divo_dot :: emit_divo_dot_r_r_r
|
|
inst_tlbsrx_dot :: inst_tlbsrx_dot_r_r_r
|
|
emit_tlbsrx_dot :: emit_tlbsrx_dot_r_r_r
|
|
inst_slbiag :: inst_slbiag_r_r_r
|
|
emit_slbiag :: emit_slbiag_r_r_r
|
|
inst_lvswxl :: inst_lvswxl_r_r_r
|
|
emit_lvswxl :: emit_lvswxl_r_r_r
|
|
inst_abso :: inst_abso_r_r_r
|
|
emit_abso :: emit_abso_r_r_r
|
|
inst_abso_dot :: inst_abso_dot_r_r_r
|
|
emit_abso_dot :: emit_abso_dot_r_r_r
|
|
inst_divso :: inst_divso_r_r_r
|
|
emit_divso :: emit_divso_r_r_r
|
|
inst_divso_dot :: inst_divso_dot_r_r_r
|
|
emit_divso_dot :: emit_divso_dot_r_r_r
|
|
inst_rmieg :: inst_rmieg_r_r_r
|
|
emit_rmieg :: emit_rmieg_r_r_r
|
|
inst_stvlxl :: inst_stvlxl_r_r_r
|
|
emit_stvlxl :: emit_stvlxl_r_r_r
|
|
inst_divdeuo_dot :: inst_divdeuo_dot_r_r_r
|
|
emit_divdeuo_dot :: emit_divdeuo_dot_r_r_r
|
|
inst_divweuo_dot :: inst_divweuo_dot_r_r_r
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emit_divweuo_dot :: emit_divweuo_dot_r_r_r
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inst_tlbsx_dot :: inst_tlbsx_dot_r_r_r
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emit_tlbsx_dot :: emit_tlbsx_dot_r_r_r
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inst_stfqx :: inst_stfqx_r_r_r
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emit_stfqx :: emit_stfqx_r_r_r
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inst_sraq :: inst_sraq_r_r_r
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emit_sraq :: emit_sraq_r_r_r
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inst_sraq_dot :: inst_sraq_dot_r_r_r
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emit_sraq_dot :: emit_sraq_dot_r_r_r
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inst_srea :: inst_srea_r_r_r
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emit_srea :: emit_srea_r_r_r
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inst_srea_dot :: inst_srea_dot_r_r_r
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emit_srea_dot :: emit_srea_dot_r_r_r
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inst_exts :: inst_exts_r_r_r
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emit_exts :: emit_exts_r_r_r
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inst_exts_dot :: inst_exts_dot_r_r_r
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emit_exts_dot :: emit_exts_dot_r_r_r
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inst_evstddepx :: inst_evstddepx_r_r_r
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emit_evstddepx :: emit_evstddepx_r_r_r
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inst_stfddx :: inst_stfddx_r_r_r
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emit_stfddx :: emit_stfddx_r_r_r
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inst_stvfrxl :: inst_stvfrxl_r_r_r
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emit_stvfrxl :: emit_stvfrxl_r_r_r
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inst_wclrall :: inst_wclrall_r_r_r
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emit_wclrall :: emit_wclrall_r_r_r
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inst_wclr :: inst_wclr_r_r_r
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emit_wclr :: emit_wclr_r_r_r
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inst_stvrxl :: inst_stvrxl_r_r_r
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emit_stvrxl :: emit_stvrxl_r_r_r
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inst_divdeo_dot :: inst_divdeo_dot_r_r_r
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emit_divdeo_dot :: emit_divdeo_dot_r_r_r
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inst_divweo_dot :: inst_divweo_dot_r_r_r
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emit_divweo_dot :: emit_divweo_dot_r_r_r
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inst_icswepx :: inst_icswepx_r_r_r
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emit_icswepx :: emit_icswepx_r_r_r
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inst_icswepx_dot :: inst_icswepx_dot_r_r_r
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emit_icswepx_dot :: emit_icswepx_dot_r_r_r
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inst_stfqux :: inst_stfqux_r_r_r
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emit_stfqux :: emit_stfqux_r_r_r
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inst_sraiq :: inst_sraiq_r_r_r
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emit_sraiq :: emit_sraiq_r_r_r
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inst_sraiq_dot :: inst_sraiq_dot_r_r_r
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emit_sraiq_dot :: emit_sraiq_dot_r_r_r
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inst_stvflxl :: inst_stvflxl_r_r_r
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emit_stvflxl :: emit_stvflxl_r_r_r
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inst_ici :: inst_ici_r_r_r
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emit_ici :: emit_ici_r_r_r
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inst_divduo :: inst_divduo_r_r_r
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emit_divduo :: emit_divduo_r_r_r
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inst_divduo_dot :: inst_divduo_dot_r_r_r
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emit_divduo_dot :: emit_divduo_dot_r_r_r
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inst_divwuo :: inst_divwuo_r_r_r
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emit_divwuo :: emit_divwuo_r_r_r
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inst_divwuo_dot :: inst_divwuo_dot_r_r_r
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emit_divwuo_dot :: emit_divwuo_dot_r_r_r
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inst_slbfee_dot :: inst_slbfee_dot_r_r_r
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emit_slbfee_dot :: emit_slbfee_dot_r_r_r
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inst_stvswxl :: inst_stvswxl_r_r_r
|
|
emit_stvswxl :: emit_stvswxl_r_r_r
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inst_icread :: inst_icread_r_r_r
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emit_icread :: emit_icread_r_r_r
|
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inst_nabso :: inst_nabso_r_r_r
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|
emit_nabso :: emit_nabso_r_r_r
|
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inst_nabso_dot :: inst_nabso_dot_r_r_r
|
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emit_nabso_dot :: emit_nabso_dot_r_r_r
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inst_divdo :: inst_divdo_r_r_r
|
|
emit_divdo :: emit_divdo_r_r_r
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inst_divdo_dot :: inst_divdo_dot_r_r_r
|
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emit_divdo_dot :: emit_divdo_dot_r_r_r
|
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inst_divwo :: inst_divwo_r_r_r
|
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emit_divwo :: emit_divwo_r_r_r
|
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inst_divwo_dot :: inst_divwo_dot_r_r_r
|
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emit_divwo_dot :: emit_divwo_dot_r_r_r
|
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inst_dclz :: inst_dclz_r_r_r
|
|
emit_dclz :: emit_dclz_r_r_r
|
|
inst_lu :: inst_lu_r_mem
|
|
emit_lu :: emit_lu_r_mem
|
|
inst_st :: inst_st_r_mem
|
|
emit_st :: emit_st_r_mem
|
|
inst_stu :: inst_stu_r_mem
|
|
emit_stu :: emit_stu_r_mem
|
|
inst_lm :: inst_lm_r_mem
|
|
emit_lm :: emit_lm_r_mem
|
|
inst_stm :: inst_stm_r_mem
|
|
emit_stm :: emit_stm_r_mem
|
|
inst_lfq :: inst_lfq_fr_mem
|
|
emit_lfq :: emit_lfq_fr_mem
|
|
inst_lfqu :: inst_lfqu_fr_mem
|
|
emit_lfqu :: emit_lfqu_fr_mem
|
|
inst_stfq :: inst_stfq_fr_mem
|
|
emit_stfq :: emit_stfq_fr_mem
|
|
inst_stfqu :: inst_stfqu_fr_mem
|
|
emit_stfqu :: emit_stfqu_fr_mem
|
|
inst_fcir :: inst_fcir_fr_mem
|
|
emit_fcir :: emit_fcir_fr_mem
|
|
inst_fcir_dot :: inst_fcir_dot_fr_mem
|
|
emit_fcir_dot :: emit_fcir_dot_fr_mem
|
|
inst_fcirz :: inst_fcirz_fr_mem
|
|
emit_fcirz :: emit_fcirz_fr_mem
|
|
inst_fcirz_dot :: inst_fcirz_dot_fr_mem
|
|
emit_fcirz_dot :: emit_fcirz_dot_fr_mem
|
|
inst_fd :: inst_fd_fr_mem
|
|
emit_fd :: emit_fd_fr_mem
|
|
inst_fd_dot :: inst_fd_dot_fr_mem
|
|
emit_fd_dot :: emit_fd_dot_fr_mem
|
|
inst_fs :: inst_fs_fr_mem
|
|
emit_fs :: emit_fs_fr_mem
|
|
inst_fs_dot :: inst_fs_dot_fr_mem
|
|
emit_fs_dot :: emit_fs_dot_fr_mem
|
|
inst_fa :: inst_fa_fr_mem
|
|
emit_fa :: emit_fa_fr_mem
|
|
inst_fa_dot :: inst_fa_dot_fr_mem
|
|
emit_fa_dot :: emit_fa_dot_fr_mem
|
|
inst_fm :: inst_fm_fr_mem
|
|
emit_fm :: emit_fm_fr_mem
|
|
inst_fm_dot :: inst_fm_dot_fr_mem
|
|
emit_fm_dot :: emit_fm_dot_fr_mem
|
|
inst_fms :: inst_fms_fr_mem
|
|
emit_fms :: emit_fms_fr_mem
|
|
inst_fms_dot :: inst_fms_dot_fr_mem
|
|
emit_fms_dot :: emit_fms_dot_fr_mem
|
|
inst_fma :: inst_fma_fr_mem
|
|
emit_fma :: emit_fma_fr_mem
|
|
inst_fma_dot :: inst_fma_dot_fr_mem
|
|
emit_fma_dot :: emit_fma_dot_fr_mem
|
|
inst_fnms :: inst_fnms_fr_mem
|
|
emit_fnms :: emit_fnms_fr_mem
|
|
inst_fnms_dot :: inst_fnms_dot_fr_mem
|
|
emit_fnms_dot :: emit_fnms_dot_fr_mem
|
|
inst_fnma :: inst_fnma_fr_mem
|
|
emit_fnma :: emit_fnma_fr_mem
|
|
inst_fnma_dot :: inst_fnma_dot_fr_mem
|
|
emit_fnma_dot :: emit_fnma_dot_fr_mem
|
|
inst_dtstexq :: inst_dtstexq_fr_mem
|
|
emit_dtstexq :: emit_dtstexq_fr_mem
|
|
inst_xscmpexpqp :: inst_xscmpexpqp_fr_mem
|
|
emit_xscmpexpqp :: emit_xscmpexpqp_fr_mem
|
|
inst_dxexq :: inst_dxexq_fr_mem
|
|
emit_dxexq :: emit_dxexq_fr_mem
|
|
inst_dxexq_dot :: inst_dxexq_dot_fr_mem
|
|
emit_dxexq_dot :: emit_dxexq_dot_fr_mem
|
|
inst_dtstsfq :: inst_dtstsfq_fr_mem
|
|
emit_dtstsfq :: emit_dtstsfq_fr_mem
|
|
inst_evseteqb_dot :: inst_evseteqb_dot_r_r_r
|
|
emit_evseteqb_dot :: emit_evseteqb_dot_r_r_r
|
|
inst_evseteqh_dot :: inst_evseteqh_dot_r_r_r
|
|
emit_evseteqh_dot :: emit_evseteqh_dot_r_r_r
|
|
inst_evseteqw_dot :: inst_evseteqw_dot_r_r_r
|
|
emit_evseteqw_dot :: emit_evseteqw_dot_r_r_r
|
|
inst_evsetgthu_dot :: inst_evsetgthu_dot_r_r_r
|
|
emit_evsetgthu_dot :: emit_evsetgthu_dot_r_r_r
|
|
inst_evsetgths_dot :: inst_evsetgths_dot_r_r_r
|
|
emit_evsetgths_dot :: emit_evsetgths_dot_r_r_r
|
|
inst_evsetgtwu_dot :: inst_evsetgtwu_dot_r_r_r
|
|
emit_evsetgtwu_dot :: emit_evsetgtwu_dot_r_r_r
|
|
inst_evsetgtws_dot :: inst_evsetgtws_dot_r_r_r
|
|
emit_evsetgtws_dot :: emit_evsetgtws_dot_r_r_r
|
|
inst_evsetgtbu_dot :: inst_evsetgtbu_dot_r_r_r
|
|
emit_evsetgtbu_dot :: emit_evsetgtbu_dot_r_r_r
|
|
inst_evsetgtbs_dot :: inst_evsetgtbs_dot_r_r_r
|
|
emit_evsetgtbs_dot :: emit_evsetgtbs_dot_r_r_r
|
|
inst_evsetltbu_dot :: inst_evsetltbu_dot_r_r_r
|
|
emit_evsetltbu_dot :: emit_evsetltbu_dot_r_r_r
|
|
inst_evsetltbs_dot :: inst_evsetltbs_dot_r_r_r
|
|
emit_evsetltbs_dot :: emit_evsetltbs_dot_r_r_r
|
|
inst_evsetlthu_dot :: inst_evsetlthu_dot_r_r_r
|
|
emit_evsetlthu_dot :: emit_evsetlthu_dot_r_r_r
|
|
inst_evsetlths_dot :: inst_evsetlths_dot_r_r_r
|
|
emit_evsetlths_dot :: emit_evsetlths_dot_r_r_r
|
|
inst_evsetltwu_dot :: inst_evsetltwu_dot_r_r_r
|
|
emit_evsetltwu_dot :: emit_evsetltwu_dot_r_r_r
|
|
inst_evsetltws_dot :: inst_evsetltws_dot_r_r_r
|
|
emit_evsetltws_dot :: emit_evsetltws_dot_r_r_r
|