mirror of
https://github.com/odin-lang/Odin.git
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47fc72e0ba
Every mnemonic with an encode form now has a generated inst_<mnem>/emit_<mnem> overload group. The per-arch generators map ALL operand types — nothing is skipped: arm64 gains shifted/extended registers (multi-param via op_shifted/op_extended), SVE Z-regs + predicates, SME tile/slice, NEON arrangements/lanes, bitmask/sysreg/pattern immediates and condition codes (427 -> 777 mnemonics); arm32 gains shifted/register-shifted regs, register lists, NEON lanes and all encoded-immediate subclasses (479 -> 592); x86 gains m80 and descriptor-table memory operands — FBLD/FBSTP, LGDT/SGDT/LIDT/SIDT, FLD/FSTP, far-indirect JMP/CALL, BOUND (1167 -> 1175). Mnemonic-specific builders are now fully generated, not hand-written: deleted the hand-written helpers the generated groups collided with — riscv inst_jal/inst_jalr, arm64 inst_b_cond/inst_cbz/inst_tbz/inst_csel, mos6502 inst_tst — and let the generators own those names (arm64 also gains inst_cbnz/tbnz/csinc/csinv/csneg). Updated the affected test call-sites. The generic operand-shape helpers (inst_r_r, inst_r_r_i, inst_ldst, ...) remain as delegation targets. Decode-only mnemonics with no encode form are correctly left without builders. ppc/ppc_vle/rsp/mos65816 were already complete. All 10 ISAs: structure + compile + tests pass; generators idempotent.
112 lines
4.4 KiB
Odin
112 lines
4.4 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_riscv
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// =============================================================================
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// INSTRUCTION
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// =============================================================================
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//
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// All non-C base instructions are 4 bytes. The `length` field is
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// preserved for shape parity with arches that have variable-length
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// (mos65816, mos6502) -- here it's always 4.
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Instruction_Flags :: bit_field u8 {
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_: u8 | 8,
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}
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Instruction :: struct #packed {
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ops: [4]Operand `fmt:"v,operand_count"`, // 40 bytes
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mnemonic: Mnemonic, // 2
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operand_count: u8, // 1
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flags: Instruction_Flags, // 1
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length: u8, // 1 -- always 4 for non-C
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_: [3]u8, // 3
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}
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#assert(size_of(Instruction) == 48)
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// =============================================================================
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// Builders (shape spelled out, comma-separated)
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// =============================================================================
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@(require_results)
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inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 0, length = 4}
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}
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// R-type: rd, rs1, rs2
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@(require_results)
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inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1, rs2: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_reg(rs1), op_reg(rs2), {}}}
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}
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// I-type (ALU): rd, rs1, imm12
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@(require_results)
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inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1: Register, imm: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_reg(rs1), op_imm(imm, 2), {}}}
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}
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// I-type (shift): rd, rs1, shamt
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@(require_results)
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inst_shift :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1: Register, shamt: u8) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_reg(rs1), op_imm(i64(shamt), 1), {}}}
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}
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// I-type load: rd, disp(base)
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@(require_results)
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inst_load :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, mm: Memory) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rd), op_mem(mm), {}, {}}}
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}
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// S-type store: rs2 (data), disp(base)
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@(require_results)
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inst_store :: #force_inline proc "contextless" (m: Mnemonic, rs2: Register, mm: Memory) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rs2), op_mem(mm), {}, {}}}
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}
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// U-type: rd, imm20
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@(require_results)
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inst_u :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, imm: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rd), op_imm(imm, 4), {}, {}}}
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}
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// B-type branch: rs1, rs2, label
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@(require_results)
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inst_branch :: #force_inline proc "contextless" (m: Mnemonic, rs1, rs2: Register, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rs1), op_reg(rs2), op_label(label_id, 2), {}}}
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}
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// CSR ops: rd, csr, rs1
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@(require_results)
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inst_csr :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, csr: u16, rs1: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_imm(i64(csr), 2), op_reg(rs1), {}}}
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}
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// CSR immediate ops: rd, csr, zimm5
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@(require_results)
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inst_csr_i :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, csr: u16, zimm5: u8) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_imm(i64(csr), 2), op_imm(i64(zimm5), 1), {}}}
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}
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// FP R4-type: rd, rs1, rs2, rs3 (FMADD/FMSUB/FNMADD/FNMSUB)
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@(require_results)
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inst_r4 :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1, rs2, rs3: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 4, length = 4,
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ops = {op_reg(rd), op_reg(rs1), op_reg(rs2), op_reg(rs3)}}
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}
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// FP R-type with 2 regs: rd, rs1 (FSQRT, FCVT, FMV, FCLASS, ...)
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@(require_results)
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inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rs1: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rd), op_reg(rs1), {}, {}}}
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}
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