mirror of
https://github.com/odin-lang/Odin.git
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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
255 lines
7.7 KiB
Odin
255 lines
7.7 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_rsp
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import "../isa"
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// =============================================================================
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// N64 RSP DECODER
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// =============================================================================
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//
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// Two passes, mirroring mips/decoder.odin. The RSP-specific bits live in
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// `extract_operand_inline`: VR / VR_ELEM operands carry an element field
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// extracted from bits 24-21 of the word, and VMEM operands collect base,
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// element offset, and signed 7-bit byte offset from their respective
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// positions in the LWC2/SWC2 layout.
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Instruction_Info :: struct {
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offset: u32,
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decode_entry: u16,
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_: u16,
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}
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#assert(size_of(Instruction_Info) == 8)
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decode :: proc(
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data: []u8,
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relocs: []Relocation,
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instructions: ^[dynamic]Instruction,
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inst_info: ^[dynamic]Instruction_Info,
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label_defs: ^[dynamic]Label_Definition,
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errors: ^[dynamic]Error,
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endianness: Endianness = .BIG,
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) -> Result {
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n_bytes := u32(len(data)) & ~u32(3) // drop dangling tail
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errors_start := u32(len(errors))
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pending_branches: [dynamic]isa.Branch_Target
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defer delete(pending_branches)
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pc: u32 = 0
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for pc < n_bytes {
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word := read_u32(data, pc, endianness)
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inst: Instruction
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info: Instruction_Info
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entry_idx := decode_one_inline(word, pc, &inst, &info)
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if entry_idx < 0 {
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append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE})
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inst = Instruction{mnemonic = .INVALID, length = 4}
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info = Instruction_Info{offset = pc}
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} else {
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inst_idx_for_branches := u32(len(instructions))
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for slot in 0..<inst.operand_count {
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op := &inst.ops[slot]
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if op.kind == .RELATIVE && op.relative >= 0 {
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append(&pending_branches, isa.Branch_Target{
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inst_idx = inst_idx_for_branches,
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op_idx = slot,
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target = u32(op.relative),
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})
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}
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}
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}
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append(instructions, inst)
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append(inst_info, info)
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pc += 4
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}
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isa.infer_labels_from_branches(pending_branches[:], pc, label_defs, relocs)
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return Result{byte_count = pc, success = u32(len(errors)) == errors_start}
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}
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// =============================================================================
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// Internal
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// =============================================================================
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@(private="file")
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decode_one_inline :: #force_inline proc "contextless" (
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word: u32, pc: u32, inst: ^Instruction, info: ^Instruction_Info,
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) -> int {
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primary := (word >> 26) & 0x3F
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range: Decode_Index
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switch primary {
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case 0x00: range = DECODE_INDEX_SPECIAL[word & 0x3F]
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case 0x01: range = DECODE_INDEX_REGIMM [(word >> 16) & 0x1F]
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case 0x12: range = DECODE_INDEX_COP2 [word & 0x3F]
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case 0x32: range = DECODE_INDEX_LWC2 [(word >> 11) & 0x1F]
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case 0x3A: range = DECODE_INDEX_SWC2 [(word >> 11) & 0x1F]
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case: range = DECODE_INDEX_PRIMARY[primary]
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}
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if range.count == 0 { return -1 }
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base := int(range.start)
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cnt := int(range.count)
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matched_idx := -1
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for i in 0..<cnt {
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e := &DECODE_ENTRIES[base + i]
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if (word & e.mask) == e.bits {
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matched_idx = base + i
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break
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}
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}
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if matched_idx < 0 { return -1 }
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entry := &DECODE_ENTRIES[matched_idx]
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inst.mnemonic = entry.mnemonic
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inst.length = 4
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inst.flags = {}
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cnt_used: u8 = 0
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if entry.ops[0] != .NONE {
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inst.ops[0] = extract_operand_inline(word, pc, entry.ops[0], entry.enc[0])
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cnt_used = 1
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if entry.ops[1] != .NONE {
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inst.ops[1] = extract_operand_inline(word, pc, entry.ops[1], entry.enc[1])
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cnt_used = 2
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if entry.ops[2] != .NONE {
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inst.ops[2] = extract_operand_inline(word, pc, entry.ops[2], entry.enc[2])
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cnt_used = 3
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if entry.ops[3] != .NONE {
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inst.ops[3] = extract_operand_inline(word, pc, entry.ops[3], entry.enc[3])
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cnt_used = 4
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}
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}
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}
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}
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inst.operand_count = cnt_used
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info.offset = pc
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info.decode_entry = u16(matched_idx)
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return matched_idx
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}
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@(private="file")
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extract_operand_inline :: #force_inline proc "contextless" (
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word: u32, pc: u32, ot: Operand_Type, en: Operand_Encoding,
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) -> Operand {
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switch en {
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case .NONE:
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return {}
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// Scalar GPR slots ------------------------------------------------------
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case .RS:
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return reg_operand_scalar(decode_gpr(word, 21, ot), ot)
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case .RT:
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return reg_operand_scalar(decode_gpr(word, 16, ot), ot)
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case .RD:
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return reg_operand_scalar(decode_gpr(word, 11, ot), ot)
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case .SHAMT:
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return Operand{immediate = i64((word >> 6) & 0x1F), kind = .IMMEDIATE, size = 1}
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// Immediates ------------------------------------------------------------
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case .IMM_16:
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imm: i64
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if ot == .IMM16S {
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imm = i64(i16(word & 0xFFFF))
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} else {
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imm = i64(word & 0xFFFF)
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}
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return Operand{immediate = imm, kind = .IMMEDIATE, size = 2}
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case .IMM_5:
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return Operand{immediate = i64((word >> 6) & 0x1F), kind = .IMMEDIATE, size = 1}
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case .IMM_20:
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return Operand{immediate = i64((word >> 6) & 0xFFFFF), kind = .IMMEDIATE, size = 4}
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case .IMM_26:
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if ot == .REL_J26 {
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field := word & 0x3FFFFFF
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target := ((pc + 4) & 0xF0000000) | (field << 2)
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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}
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return Operand{immediate = i64(word & 0x3FFFFFF), kind = .IMMEDIATE, size = 4}
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// Scalar memory ---------------------------------------------------------
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case .OFFSET_BASE:
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base_hw := u16((word >> 21) & 0x1F)
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disp := i32(i16(word & 0xFFFF))
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m := Memory{base = Register(REG_GPR | base_hw), disp = disp}
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return Operand{mem = m, kind = .MEMORY, size = 4}
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case .BRANCH_16:
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rel := i32(i16(word & 0xFFFF)) << 2
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target := u32(i32(pc) + 4 + rel)
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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case .IMPL:
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return {}
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// Vector ALU register slots --------------------------------------------
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// VT pulls vt hw number (bits 20-16) AND element selector (bits 24-21).
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case .VT:
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hw := u16((word >> 16) & 0x1F)
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elem := u8 ((word >> 21) & 0x0F)
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return Operand{
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reg = Register(REG_VR | hw),
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kind = ot == .VR_ELEM ? .VECTOR_REG : .VECTOR_REG,
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size = 16,
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element = elem,
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}
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case .VS:
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hw := u16((word >> 11) & 0x1F)
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return Operand{reg = Register(REG_VR | hw), kind = .VECTOR_REG, size = 16}
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case .VD:
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hw := u16((word >> 6) & 0x1F)
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return Operand{reg = Register(REG_VR | hw), kind = .VECTOR_REG, size = 16}
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case .ELEM:
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return Operand{immediate = i64((word >> 21) & 0x0F), kind = .IMMEDIATE, size = 1}
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// Vector L/S placements -------------------------------------------------
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case .VT_LS:
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hw := u16((word >> 16) & 0x1F)
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return Operand{reg = Register(REG_VR | hw), kind = .VECTOR_REG, size = 16}
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case .VOP:
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return {} // static, not an operand at runtime
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case .VELEM_LS:
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return Operand{immediate = i64((word >> 7) & 0x0F), kind = .IMMEDIATE, size = 1}
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case .VOFFSET:
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// Sign-extend the 7-bit field.
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v := i32(word & 0x7F)
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if v & 0x40 != 0 { v |= ~i32(0x7F) }
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
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case .VBASE:
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// The VBASE encoding emits the full Vector_Mem (base + element + offset).
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base_hw := u16((word >> 21) & 0x1F)
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elem := u8 ((word >> 7) & 0x0F)
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v := i32(word & 0x7F)
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if v & 0x40 != 0 { v |= ~i32(0x7F) }
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vm := Vector_Mem{
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base = Register(REG_GPR | base_hw),
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element = elem,
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offset = v,
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}
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return Operand{vmem = vm, kind = .VECTOR_MEM, size = 16}
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}
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return {}
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}
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@(private="file")
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decode_gpr :: #force_inline proc "contextless" (word: u32, shift: u8, ot: Operand_Type) -> Register {
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hw: u16 = u16((word >> shift) & 0x1F)
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class: u16 = REG_GPR
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#partial switch ot {
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case .CP0_REG: class = REG_CP0
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case .CP2_CTRL: class = REG_VC
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}
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return Register(class | hw)
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}
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@(private="file")
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reg_operand_scalar :: #force_inline proc "contextless" (r: Register, ot: Operand_Type) -> Operand {
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return Operand{reg = r, kind = .REGISTER, size = 4}
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}
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