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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
84 lines
2.2 KiB
Odin
84 lines
2.2 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_rsp
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// =============================================================================
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// N64 RSP MNEMONICS
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// =============================================================================
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//
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// Two halves: a strict MIPS I subset for the scalar core (no
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// MULT/DIV/HI/LO/SYNC/LWL/LWR/SWL/SWR/64-bit), and the vector unit
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// (VMULF.../VLT.../VRCP.../etc. + LBV..LTV loads, SBV..STV stores).
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Mnemonic :: enum u16 {
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INVALID = 0,
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// -------------------------------------------------------------------------
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// Scalar core — MIPS I subset
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// -------------------------------------------------------------------------
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// R-type arithmetic / logical / shift
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ADD, ADDU, SUB, SUBU,
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AND, OR, XOR, NOR,
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SLT, SLTU,
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SLL, SRL, SRA,
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SLLV, SRLV, SRAV,
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// I-type
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ADDI, ADDIU,
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SLTI, SLTIU,
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ANDI, ORI, XORI,
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LUI,
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// Branches (with delay slot)
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BEQ, BNE, BLEZ, BGTZ,
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BLTZ, BGEZ, BLTZAL, BGEZAL,
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// Jumps
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J, JAL, JR, JALR,
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// Load / Store (no LWL/LWR/SWL/SWR on the RSP).
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LB, LH, LW, LBU, LHU,
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SB, SH, SW,
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// System
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BREAK, NOP,
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// Coprocessor moves
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MFC0, MTC0,
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MFC2, MTC2, CFC2, CTC2,
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// -------------------------------------------------------------------------
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// Vector ALU (COP2, CO=1; opcode 0x12 with funct selecting)
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// -------------------------------------------------------------------------
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VMULF, VMULU,
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VMUDL, VMUDM, VMUDN, VMUDH,
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VMACF, VMACU,
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VMADL, VMADM, VMADN, VMADH,
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VADD, VSUB, VABS,
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VADDC, VSUBC,
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VSAR,
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VLT, VEQ, VNE, VGE,
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VCL, VCH, VCR, VMRG,
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VAND, VNAND, VOR, VNOR, VXOR, VNXOR,
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VRCP, VRCPL, VRCPH,
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VMOV,
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VRSQ, VRSQL, VRSQH,
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VNOP,
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// -------------------------------------------------------------------------
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// Vector loads (LWC2 = opcode 0x32 with op2 selector)
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// -------------------------------------------------------------------------
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LBV, LSV, LLV, LDV, LQV, LRV,
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LPV, LUV, LHV, LFV, LWV, LTV,
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// -------------------------------------------------------------------------
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// Vector stores (SWC2 = opcode 0x3A with op2 selector)
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// -------------------------------------------------------------------------
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SBV, SSV, SLV, SDV, SQV, SRV,
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SPV, SUV, SHV, SFV, SWV, STV,
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}
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