mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-19 16:42:33 +00:00
4cc6977321
Merge gingerBill's latest into bill/rexcode. His changes: minimize the Instruction/Operand structs across ISAs with packed raw-unions (+ the compiler support for #raw_union #packed), the new core:rexcode/wasm arch and wasm/module, encode() now returns (byte_count, ok) instead of a Result struct, decode_one made public, and assorted formatting/inlining. Conflict: arm64/tests/pipeline_smoke.odin CSEL test -- kept the generated 4-arg inst_csel(dst,src,src2,cond) (mnemonic_builders.odin is generated, not from Bill's branch) and adopted Bill's (byte_count, success) encode signature. Required rebuilding ./odin from the merged source for the packed-union syntax. Re-validated after the repack: regenerated all artifacts (idempotent -- no spurious churn), all 10 arches gen/builders/check/test green, and byte-compared the new arm32 BF + mips PS/MMI/DSP/R6 forms to confirm no field truncation. arm64/arm32/mips still 100%.
284 lines
10 KiB
Odin
284 lines
10 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm64
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// =============================================================================
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// AArch64 OPERANDS
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// =============================================================================
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//
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// AArch64 has a rich addressing repertoire:
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//
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// [Xn] OFFSET with imm=0
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// [Xn, #imm] OFFSET (signed 9 or unsigned scaled 12)
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// [Xn, #imm]! PRE_INDEXED (writeback before)
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// [Xn], #imm POST_INDEXED (writeback after)
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// [Xn, Xm{, LSL #s}] REG_OFFSET (shift = log2(size) when present)
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// [Xn, Wm, SXTW|UXTW|SXTX #s] EXT_REG_OFFSET
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// label LITERAL (PC-relative for LDR literal)
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//
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// `Shift_Type` and `Extend` enumerate the shifter/extender flavours that
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// data-processing register and memory operand encodings need.
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Operand_Kind :: enum u8 {
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NONE,
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REGISTER,
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IMMEDIATE,
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MEMORY,
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RELATIVE,
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SHIFTED_REG, // X reg + shift type + shift amount
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EXTENDED_REG, // X/W reg + extend + amount
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COND, // 4-bit condition code (EQ/NE/.../AL/NV)
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}
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Shift_Type :: enum u8 {
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LSL = 0,
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LSR = 1,
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ASR = 2,
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ROR = 3,
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}
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Extend :: enum u8 {
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UXTB = 0,
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UXTH = 1,
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UXTW = 2,
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UXTX = 3,
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SXTB = 4,
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SXTH = 5,
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SXTW = 6,
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SXTX = 7,
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}
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Address_Mode :: enum u8 {
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OFFSET, // [Xn, #imm] (imm may be 0)
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PRE_INDEXED, // [Xn, #imm]!
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POST_INDEXED, // [Xn], #imm
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REG_OFFSET, // [Xn, Xm{, LSL #s}]
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EXT_REG_OFFSET, // [Xn, Wm, SXTW|UXTW|SXTX #s]
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LITERAL, // PC-rel target (LDR literal)
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}
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// 16-byte memory operand: base + optional index + signed disp + addressing
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// metadata. Index is `NONE` for non-register-offset modes.
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Memory :: struct #packed {
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base: Register, // 2
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index: Register, // 2 (NONE for OFFSET/PRE/POST/LITERAL)
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disp: i32, // 4 (signed; pre/post can be -256..255 unscaled,
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// OFFSET supports 0..32760 scaled via imm12*size)
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extend: Extend, // 1 (for EXT_REG_OFFSET; UXTX otherwise)
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shift: u8, // 1 (0..4 for register-offset / extended; or
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// shift amount for shifted-register operands
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// when reused there)
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mode: Address_Mode, // 1
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_: u8, // 1
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}
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#assert(size_of(Memory) == 12)
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Shifted_Reg :: struct #packed {
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reg: Register, // 2
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type: Shift_Type, // 1
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amount: u8, // 1 (0..63 for 64-bit; 0..31 for 32-bit)
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}
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#assert(size_of(Shifted_Reg) == 4)
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Extended_Reg :: struct #packed {
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reg: Register, // 2
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extend: Extend, // 1
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amount: u8, // 1 (0..4)
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}
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#assert(size_of(Extended_Reg) == 4)
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// 16-byte tagged operand. The union holds whichever payload matches `kind`.
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Operand :: struct #packed {
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using _: struct #raw_union #packed {
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reg: Register, // 2
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mem: Memory, // 12
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immediate: i64, // 8
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relative: i64, // 8
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shifted: Shifted_Reg, // 8
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extended: Extended_Reg, // 8
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cond: u8, // 1
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}, // 12 total because of alignment
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kind: Operand_Kind, // 1
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size: u8, // 1 -- carried width info; meaning varies
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}
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#assert(size_of(Operand) == 14)
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// -----------------------------------------------------------------------------
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// Constructors -- generic
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// -----------------------------------------------------------------------------
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@(require_results)
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op_reg :: #force_inline proc "contextless" (r: Register) -> Operand {
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return Operand{reg = r, kind = .REGISTER, size = 4}
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}
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@(require_results)
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op_imm :: #force_inline proc "contextless" (v: i64, size: u8 = 4) -> Operand {
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return Operand{immediate = v, kind = .IMMEDIATE, size = size}
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}
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@(require_results)
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op_label :: #force_inline proc "contextless" (label_id: u32, size: u8 = 4) -> Operand {
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return Operand{relative = i64(label_id), kind = .RELATIVE, size = size}
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}
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@(require_results)
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op_rel_offset :: #force_inline proc "contextless" (off: i64) -> Operand {
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return Operand{relative = off, kind = .RELATIVE, size = 4}
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}
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@(require_results)
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op_mem :: #force_inline proc "contextless" (m: Memory) -> Operand {
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return Operand{mem = m, kind = .MEMORY, size = 4}
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}
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@(require_results)
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op_shifted :: #force_inline proc "contextless" (r: Register, type: Shift_Type, amount: u8) -> Operand {
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return Operand{shifted = Shifted_Reg{reg = r, type = type, amount = amount}, kind = .SHIFTED_REG, size = 4}
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}
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@(require_results)
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op_extended :: #force_inline proc "contextless" (r: Register, ext: Extend, amount: u8) -> Operand {
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return Operand{extended = Extended_Reg{reg = r, extend = ext, amount = amount}, kind = .EXTENDED_REG, size = 4}
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}
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@(require_results)
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op_cond :: #force_inline proc "contextless" (c: Cond) -> Operand {
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return Operand{cond = u8(c), kind = .COND, size = 1}
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}
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// -----------------------------------------------------------------------------
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// SVE Z-register builders -- encode the element arrangement in op.size
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// (B=1, H=2, S=4, D=8). Matcher uses op.size to disambiguate the right
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// table form when multiple element sizes share a base mnemonic.
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// -----------------------------------------------------------------------------
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@(require_results)
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op_z_b :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_Z | u16(n & 0x1F)), kind = .REGISTER, size = 1}
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}
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@(require_results)
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op_z_h :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_Z | u16(n & 0x1F)), kind = .REGISTER, size = 2}
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}
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@(require_results)
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op_z_s :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_Z | u16(n & 0x1F)), kind = .REGISTER, size = 4}
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}
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@(require_results)
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op_z_d :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_Z | u16(n & 0x1F)), kind = .REGISTER, size = 8}
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}
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// -----------------------------------------------------------------------------
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// NEON V-register arrangement builders -- op.size encodes lanes*elem-bytes:
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// .8B = 8 .16B = 16
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// .4H = 24 .8H = 32
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// .2S = 40 .4S = 48
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// .1D = 56 .2D = 64
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// (Encoded so that no two arrangements collide and so the value is easy
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// to inspect.)
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// -----------------------------------------------------------------------------
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@(require_results)
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op_v_8b :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 8}
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}
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@(require_results)
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op_v_16b :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 16}
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}
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@(require_results)
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op_v_4h :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 24}
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}
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@(require_results)
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op_v_8h :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 32}
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}
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@(require_results)
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op_v_2s :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 40}
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}
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@(require_results)
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op_v_4s :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 48}
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}
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@(require_results)
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op_v_1d :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 56}
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}
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@(require_results)
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op_v_2d :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 64}
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}
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// Element-indexed V views (V0.B[i]/.H[i]/.S[i]/.D[i]). The element size rides
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// in op.size (1/2/4/8) so the matcher can disambiguate DUP/INS forms; the lane
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// index is a separate immediate operand.
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@(require_results)
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op_v_elem_b :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 1}
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}
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@(require_results)
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op_v_elem_h :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 2}
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}
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@(require_results)
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op_v_elem_s :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 4}
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}
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@(require_results)
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op_v_elem_d :: #force_inline proc "contextless" (n: u8) -> Operand {
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return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 8}
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}
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// -----------------------------------------------------------------------------
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// Memory constructors (one per addressing mode)
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// -----------------------------------------------------------------------------
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@(require_results)
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mem_offset :: #force_inline proc "contextless" (base: Register, disp: i32 = 0) -> Memory {
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return Memory{base = base, index = NONE, disp = disp, mode = .OFFSET}
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}
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@(require_results)
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mem_pre :: #force_inline proc "contextless" (base: Register, disp: i32) -> Memory {
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return Memory{base = base, index = NONE, disp = disp, mode = .PRE_INDEXED}
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}
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@(require_results)
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mem_post :: #force_inline proc "contextless" (base: Register, disp: i32) -> Memory {
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return Memory{base = base, index = NONE, disp = disp, mode = .POST_INDEXED}
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}
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@(require_results)
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mem_reg :: #force_inline proc "contextless" (base, index: Register, shift_amount: u8 = 0) -> Memory {
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return Memory{base = base, index = index, mode = .REG_OFFSET, shift = shift_amount, extend = .UXTX}
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}
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@(require_results)
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mem_ext :: #force_inline proc "contextless" (base, index: Register, ext: Extend, shift_amount: u8 = 0) -> Memory {
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return Memory{base = base, index = index, mode = .EXT_REG_OFFSET, extend = ext, shift = shift_amount}
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}
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// -----------------------------------------------------------------------------
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// Condition codes
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// -----------------------------------------------------------------------------
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Cond :: enum u8 {
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EQ = 0x0,
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NE = 0x1,
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CS = 0x2, // unsigned higher or same (alias HS)
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CC = 0x3, // unsigned lower (alias LO)
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MI = 0x4,
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PL = 0x5,
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VS = 0x6,
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VC = 0x7,
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HI = 0x8,
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LS = 0x9,
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GE = 0xA,
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LT = 0xB,
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GT = 0xC,
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LE = 0xD,
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AL = 0xE,
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NV = 0xF,
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}
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// Architectural aliases for the two carry-style conditions.
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COND_HS :: Cond.CS
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COND_LO :: Cond.CC
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