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An instruction carried four operands. The coprocessor transfers need six -- `mcr p15, #0, r0, c0, c0, #0` -- and dropping the tail is not merely printing short: an opc2 that is not zero encoded as zero, which is a different instruction. Six operands do not fit alongside the rest in 64 bytes, since Operand is 11 and Memory cannot go below 8, so Instruction is 128 now and straddles two cache lines rather than one. With room for them, the block itself turns out to have been wrong throughout. CDP, MCR and MRC took CRd from bits 19:16, which is CRn; CRd is 15:12. MCR and MRC read a four-bit opc1 where theirs is the three bits at 23:21. Neither they nor CDP read opc2 at all. MCRR and MRRC dropped CRm. LDC and STC were worse: they took CRd from the base register's field, read the offset with the halfword-load encoding rather than as an imm8 counting words, and their base pattern named P=0 W=0, which is the unindexed form whose syntax is `{option}` and not what they printed. They now have the offset, pre-indexed and post-indexed forms, with U left out of the mask because it is the offset's sign and belongs to the memory operand. The N bit asks the coprocessor for the long transfer and the syntax spells that as an L, so LDCL, STCL, LDC2L and STC2L are mnemonics of their own. None of this is reachable from the table sweep, which decodes each form's canonical word with every variable field zero -- for these that means p0, which ARMv8 reserves and no assembler will take. So twelve hand-picked words go in the pipeline test instead, checked against the text an assembler accepts for them, including a p15 system-register read. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA