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1b72d425d4
Add generated mnemonic_builders.odin (inst_<mnem>/emit_<mnem> typed overload sets) for arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502 and mos65816, matching the existing x86 builders. Each is produced by a per-arch tools/gen_mnemonic_builders.odin that walks ENCODE_FORMS and maps operand types to typed params + op_* constructors. Anchor every generator's output via #directory so regeneration is CWD-independent; previously the bare "mnemonic_builders.odin" path wrote to the current directory and misfired when run from the repo root. Wire a --builders task into build.lua (folded into 'all', covered by --idempotent, enforced by the structural invariants) and document it in the README.
490 lines
60 KiB
Odin
490 lines
60 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_rsp
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// =============================================================================
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// GENERATED FILE - DO NOT EDIT
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// =============================================================================
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//
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// Generated by tools/gen_mnemonic_builders.odin from ENCODE_FORMS.
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// Regenerate with: odin run rsp/tools/gen_mnemonic_builders.odin -file
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//
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// This file provides typed mnemonic builder procedures with overloading.
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// Each mnemonic has an inst_<mnem> constructor (returns an Instruction) and an
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// emit_<mnem> helper (appends to a ^[dynamic]Instruction). Vector operands with
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// an element selector (.VR_ELEM) take a trailing 'element: u8 = 0' parameter.
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// =============================================================================
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// Individual Typed Builder Procedures
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// =============================================================================
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inst_add_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_add_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_add_gpr_gpr_gpr(a, b, c)) }
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inst_addu_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .ADDU, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_addu_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_addu_gpr_gpr_gpr(a, b, c)) }
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inst_sub_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_sub_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_sub_gpr_gpr_gpr(a, b, c)) }
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inst_subu_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .SUBU, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_subu_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_subu_gpr_gpr_gpr(a, b, c)) }
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inst_and_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_and_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_and_gpr_gpr_gpr(a, b, c)) }
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inst_or_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .OR, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_or_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_or_gpr_gpr_gpr(a, b, c)) }
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inst_xor_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .XOR, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_xor_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_xor_gpr_gpr_gpr(a, b, c)) }
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inst_nor_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .NOR, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_nor_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_nor_gpr_gpr_gpr(a, b, c)) }
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inst_slt_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .SLT, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_slt_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_slt_gpr_gpr_gpr(a, b, c)) }
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inst_sltu_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .SLTU, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_sltu_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_sltu_gpr_gpr_gpr(a, b, c)) }
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inst_sll_gpr_gpr_imm5 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .SLL, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 1), {}} } }
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emit_sll_gpr_gpr_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_sll_gpr_gpr_imm5(a, b, imm)) }
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inst_srl_gpr_gpr_imm5 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .SRL, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 1), {}} } }
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emit_srl_gpr_gpr_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_srl_gpr_gpr_imm5(a, b, imm)) }
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inst_sra_gpr_gpr_imm5 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .SRA, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 1), {}} } }
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emit_sra_gpr_gpr_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_sra_gpr_gpr_imm5(a, b, imm)) }
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inst_sllv_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .SLLV, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_sllv_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_sllv_gpr_gpr_gpr(a, b, c)) }
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inst_srlv_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .SRLV, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_srlv_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_srlv_gpr_gpr_gpr(a, b, c)) }
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inst_srav_gpr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register) -> Instruction { return Instruction{ mnemonic = .SRAV, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_reg(c), {}} } }
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emit_srav_gpr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register) { append(instructions, inst_srav_gpr_gpr_gpr(a, b, c)) }
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inst_addi_gpr_gpr_imm16 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .ADDI, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 2), {}} } }
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emit_addi_gpr_gpr_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_addi_gpr_gpr_imm16(a, b, imm)) }
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inst_addiu_gpr_gpr_imm16 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .ADDIU, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 2), {}} } }
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emit_addiu_gpr_gpr_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_addiu_gpr_gpr_imm16(a, b, imm)) }
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inst_slti_gpr_gpr_imm16 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .SLTI, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 2), {}} } }
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emit_slti_gpr_gpr_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_slti_gpr_gpr_imm16(a, b, imm)) }
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inst_sltiu_gpr_gpr_imm16 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .SLTIU, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 2), {}} } }
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emit_sltiu_gpr_gpr_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_sltiu_gpr_gpr_imm16(a, b, imm)) }
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inst_andi_gpr_gpr_imm16 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .ANDI, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 2), {}} } }
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emit_andi_gpr_gpr_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_andi_gpr_gpr_imm16(a, b, imm)) }
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inst_ori_gpr_gpr_imm16 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .ORI, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 2), {}} } }
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emit_ori_gpr_gpr_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_ori_gpr_gpr_imm16(a, b, imm)) }
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inst_xori_gpr_gpr_imm16 :: #force_inline proc "contextless" (a: Register, b: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .XORI, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_imm(imm, 2), {}} } }
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emit_xori_gpr_gpr_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, imm: i64) { append(instructions, inst_xori_gpr_gpr_imm16(a, b, imm)) }
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inst_lui_gpr_imm16 :: #force_inline proc "contextless" (a: Register, imm: i64) -> Instruction { return Instruction{ mnemonic = .LUI, operand_count = 2, length = 4, ops = {op_reg(a), op_imm(imm, 2), {}, {}} } }
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emit_lui_gpr_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, imm: i64) { append(instructions, inst_lui_gpr_imm16(a, imm)) }
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inst_beq_gpr_gpr_rel :: #force_inline proc "contextless" (a: Register, b: Register, label_id: u32) -> Instruction { return Instruction{ mnemonic = .BEQ, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_label(label_id), {}} } }
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emit_beq_gpr_gpr_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, label_id: u32) { append(instructions, inst_beq_gpr_gpr_rel(a, b, label_id)) }
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inst_bne_gpr_gpr_rel :: #force_inline proc "contextless" (a: Register, b: Register, label_id: u32) -> Instruction { return Instruction{ mnemonic = .BNE, operand_count = 3, length = 4, ops = {op_reg(a), op_reg(b), op_label(label_id), {}} } }
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emit_bne_gpr_gpr_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, label_id: u32) { append(instructions, inst_bne_gpr_gpr_rel(a, b, label_id)) }
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inst_blez_gpr_rel :: #force_inline proc "contextless" (a: Register, label_id: u32) -> Instruction { return Instruction{ mnemonic = .BLEZ, operand_count = 2, length = 4, ops = {op_reg(a), op_label(label_id), {}, {}} } }
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emit_blez_gpr_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) { append(instructions, inst_blez_gpr_rel(a, label_id)) }
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inst_bgtz_gpr_rel :: #force_inline proc "contextless" (a: Register, label_id: u32) -> Instruction { return Instruction{ mnemonic = .BGTZ, operand_count = 2, length = 4, ops = {op_reg(a), op_label(label_id), {}, {}} } }
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emit_bgtz_gpr_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) { append(instructions, inst_bgtz_gpr_rel(a, label_id)) }
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inst_bltz_gpr_rel :: #force_inline proc "contextless" (a: Register, label_id: u32) -> Instruction { return Instruction{ mnemonic = .BLTZ, operand_count = 2, length = 4, ops = {op_reg(a), op_label(label_id), {}, {}} } }
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emit_bltz_gpr_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) { append(instructions, inst_bltz_gpr_rel(a, label_id)) }
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inst_bgez_gpr_rel :: #force_inline proc "contextless" (a: Register, label_id: u32) -> Instruction { return Instruction{ mnemonic = .BGEZ, operand_count = 2, length = 4, ops = {op_reg(a), op_label(label_id), {}, {}} } }
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emit_bgez_gpr_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) { append(instructions, inst_bgez_gpr_rel(a, label_id)) }
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inst_bltzal_gpr_rel :: #force_inline proc "contextless" (a: Register, label_id: u32) -> Instruction { return Instruction{ mnemonic = .BLTZAL, operand_count = 2, length = 4, ops = {op_reg(a), op_label(label_id), {}, {}} } }
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emit_bltzal_gpr_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) { append(instructions, inst_bltzal_gpr_rel(a, label_id)) }
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inst_bgezal_gpr_rel :: #force_inline proc "contextless" (a: Register, label_id: u32) -> Instruction { return Instruction{ mnemonic = .BGEZAL, operand_count = 2, length = 4, ops = {op_reg(a), op_label(label_id), {}, {}} } }
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emit_bgezal_gpr_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, label_id: u32) { append(instructions, inst_bgezal_gpr_rel(a, label_id)) }
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inst_j_rel :: #force_inline proc "contextless" (label_id: u32) -> Instruction { return Instruction{ mnemonic = .J, operand_count = 1, length = 4, ops = {op_label(label_id), {}, {}, {}} } }
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emit_j_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label_id: u32) { append(instructions, inst_j_rel(label_id)) }
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inst_jal_rel :: #force_inline proc "contextless" (label_id: u32) -> Instruction { return Instruction{ mnemonic = .JAL, operand_count = 1, length = 4, ops = {op_label(label_id), {}, {}, {}} } }
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emit_jal_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label_id: u32) { append(instructions, inst_jal_rel(label_id)) }
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inst_jr_gpr :: #force_inline proc "contextless" (a: Register) -> Instruction { return Instruction{ mnemonic = .JR, operand_count = 1, length = 4, ops = {op_reg(a), {}, {}, {}} } }
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emit_jr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register) { append(instructions, inst_jr_gpr(a)) }
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inst_jalr_gpr_gpr :: #force_inline proc "contextless" (a: Register, b: Register) -> Instruction { return Instruction{ mnemonic = .JALR, operand_count = 2, length = 4, ops = {op_reg(a), op_reg(b), {}, {}} } }
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emit_jalr_gpr_gpr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) { append(instructions, inst_jalr_gpr_gpr(a, b)) }
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inst_lb_gpr_mem :: #force_inline proc "contextless" (a: Register, m: Memory) -> Instruction { return Instruction{ mnemonic = .LB, operand_count = 2, length = 4, ops = {op_reg(a), op_mem(m, 4), {}, {}} } }
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emit_lb_gpr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) { append(instructions, inst_lb_gpr_mem(a, m)) }
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inst_lh_gpr_mem :: #force_inline proc "contextless" (a: Register, m: Memory) -> Instruction { return Instruction{ mnemonic = .LH, operand_count = 2, length = 4, ops = {op_reg(a), op_mem(m, 4), {}, {}} } }
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emit_lh_gpr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) { append(instructions, inst_lh_gpr_mem(a, m)) }
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inst_lw_gpr_mem :: #force_inline proc "contextless" (a: Register, m: Memory) -> Instruction { return Instruction{ mnemonic = .LW, operand_count = 2, length = 4, ops = {op_reg(a), op_mem(m, 4), {}, {}} } }
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emit_lw_gpr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) { append(instructions, inst_lw_gpr_mem(a, m)) }
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inst_lbu_gpr_mem :: #force_inline proc "contextless" (a: Register, m: Memory) -> Instruction { return Instruction{ mnemonic = .LBU, operand_count = 2, length = 4, ops = {op_reg(a), op_mem(m, 4), {}, {}} } }
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emit_lbu_gpr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) { append(instructions, inst_lbu_gpr_mem(a, m)) }
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inst_lhu_gpr_mem :: #force_inline proc "contextless" (a: Register, m: Memory) -> Instruction { return Instruction{ mnemonic = .LHU, operand_count = 2, length = 4, ops = {op_reg(a), op_mem(m, 4), {}, {}} } }
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emit_lhu_gpr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) { append(instructions, inst_lhu_gpr_mem(a, m)) }
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inst_sb_gpr_mem :: #force_inline proc "contextless" (a: Register, m: Memory) -> Instruction { return Instruction{ mnemonic = .SB, operand_count = 2, length = 4, ops = {op_reg(a), op_mem(m, 4), {}, {}} } }
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emit_sb_gpr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) { append(instructions, inst_sb_gpr_mem(a, m)) }
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inst_sh_gpr_mem :: #force_inline proc "contextless" (a: Register, m: Memory) -> Instruction { return Instruction{ mnemonic = .SH, operand_count = 2, length = 4, ops = {op_reg(a), op_mem(m, 4), {}, {}} } }
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emit_sh_gpr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) { append(instructions, inst_sh_gpr_mem(a, m)) }
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inst_sw_gpr_mem :: #force_inline proc "contextless" (a: Register, m: Memory) -> Instruction { return Instruction{ mnemonic = .SW, operand_count = 2, length = 4, ops = {op_reg(a), op_mem(m, 4), {}, {}} } }
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emit_sw_gpr_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Memory) { append(instructions, inst_sw_gpr_mem(a, m)) }
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inst_break_imm20 :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{ mnemonic = .BREAK, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}} } }
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emit_break_imm20 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_break_imm20(imm)) }
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inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{ mnemonic = .NOP, operand_count = 0, length = 4, ops = {{}, {}, {}, {}} } }
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emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) }
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inst_mfc0_gpr_cp0 :: #force_inline proc "contextless" (a: Register, b: Register) -> Instruction { return Instruction{ mnemonic = .MFC0, operand_count = 2, length = 4, ops = {op_reg(a), op_reg(b), {}, {}} } }
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emit_mfc0_gpr_cp0 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) { append(instructions, inst_mfc0_gpr_cp0(a, b)) }
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inst_mtc0_gpr_cp0 :: #force_inline proc "contextless" (a: Register, b: Register) -> Instruction { return Instruction{ mnemonic = .MTC0, operand_count = 2, length = 4, ops = {op_reg(a), op_reg(b), {}, {}} } }
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emit_mtc0_gpr_cp0 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) { append(instructions, inst_mtc0_gpr_cp0(a, b)) }
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inst_mfc2_gpr_vr :: #force_inline proc "contextless" (a: Register, b: Register) -> Instruction { return Instruction{ mnemonic = .MFC2, operand_count = 2, length = 4, ops = {op_reg(a), op_vr(b), {}, {}} } }
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emit_mfc2_gpr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) { append(instructions, inst_mfc2_gpr_vr(a, b)) }
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inst_mtc2_gpr_vr :: #force_inline proc "contextless" (a: Register, b: Register) -> Instruction { return Instruction{ mnemonic = .MTC2, operand_count = 2, length = 4, ops = {op_reg(a), op_vr(b), {}, {}} } }
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emit_mtc2_gpr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) { append(instructions, inst_mtc2_gpr_vr(a, b)) }
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inst_cfc2_gpr_cp2 :: #force_inline proc "contextless" (a: Register, b: Register) -> Instruction { return Instruction{ mnemonic = .CFC2, operand_count = 2, length = 4, ops = {op_reg(a), op_reg(b), {}, {}} } }
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emit_cfc2_gpr_cp2 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) { append(instructions, inst_cfc2_gpr_cp2(a, b)) }
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inst_ctc2_gpr_cp2 :: #force_inline proc "contextless" (a: Register, b: Register) -> Instruction { return Instruction{ mnemonic = .CTC2, operand_count = 2, length = 4, ops = {op_reg(a), op_reg(b), {}, {}} } }
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emit_ctc2_gpr_cp2 :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register) { append(instructions, inst_ctc2_gpr_cp2(a, b)) }
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inst_vmulf_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMULF, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmulf_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmulf_vr_vr_vr(a, b, c, element)) }
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inst_vmulu_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMULU, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmulu_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmulu_vr_vr_vr(a, b, c, element)) }
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inst_vmudl_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMUDL, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmudl_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmudl_vr_vr_vr(a, b, c, element)) }
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inst_vmudm_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMUDM, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmudm_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmudm_vr_vr_vr(a, b, c, element)) }
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inst_vmudn_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMUDN, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmudn_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmudn_vr_vr_vr(a, b, c, element)) }
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inst_vmudh_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMUDH, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmudh_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmudh_vr_vr_vr(a, b, c, element)) }
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inst_vmacf_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMACF, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmacf_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmacf_vr_vr_vr(a, b, c, element)) }
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inst_vmacu_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMACU, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmacu_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmacu_vr_vr_vr(a, b, c, element)) }
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inst_vmadl_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMADL, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmadl_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmadl_vr_vr_vr(a, b, c, element)) }
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inst_vmadm_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMADM, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmadm_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmadm_vr_vr_vr(a, b, c, element)) }
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inst_vmadn_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMADN, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmadn_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmadn_vr_vr_vr(a, b, c, element)) }
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inst_vmadh_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMADH, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmadh_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmadh_vr_vr_vr(a, b, c, element)) }
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inst_vadd_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VADD, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vadd_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vadd_vr_vr_vr(a, b, c, element)) }
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inst_vsub_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VSUB, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vsub_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vsub_vr_vr_vr(a, b, c, element)) }
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inst_vabs_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VABS, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vabs_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vabs_vr_vr_vr(a, b, c, element)) }
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inst_vaddc_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VADDC, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vaddc_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vaddc_vr_vr_vr(a, b, c, element)) }
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inst_vsubc_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VSUBC, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vsubc_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vsubc_vr_vr_vr(a, b, c, element)) }
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inst_vsar_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VSAR, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vsar_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vsar_vr_vr_vr(a, b, c, element)) }
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inst_vlt_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VLT, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vlt_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vlt_vr_vr_vr(a, b, c, element)) }
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inst_veq_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VEQ, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_veq_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_veq_vr_vr_vr(a, b, c, element)) }
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inst_vne_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VNE, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vne_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vne_vr_vr_vr(a, b, c, element)) }
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inst_vge_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VGE, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vge_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vge_vr_vr_vr(a, b, c, element)) }
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inst_vcl_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VCL, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vcl_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vcl_vr_vr_vr(a, b, c, element)) }
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inst_vch_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VCH, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vch_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vch_vr_vr_vr(a, b, c, element)) }
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inst_vcr_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VCR, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vcr_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vcr_vr_vr_vr(a, b, c, element)) }
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inst_vmrg_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMRG, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vmrg_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vmrg_vr_vr_vr(a, b, c, element)) }
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inst_vand_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VAND, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vand_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vand_vr_vr_vr(a, b, c, element)) }
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inst_vnand_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VNAND, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vnand_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vnand_vr_vr_vr(a, b, c, element)) }
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inst_vor_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VOR, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vor_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vor_vr_vr_vr(a, b, c, element)) }
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inst_vnor_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VNOR, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vnor_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vnor_vr_vr_vr(a, b, c, element)) }
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inst_vxor_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VXOR, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vxor_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vxor_vr_vr_vr(a, b, c, element)) }
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inst_vnxor_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VNXOR, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vnxor_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vnxor_vr_vr_vr(a, b, c, element)) }
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inst_vrcp_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VRCP, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vrcp_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vrcp_vr_vr_vr(a, b, c, element)) }
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inst_vrcpl_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VRCPL, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vrcpl_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vrcpl_vr_vr_vr(a, b, c, element)) }
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inst_vrcph_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VRCPH, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vrcph_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vrcph_vr_vr_vr(a, b, c, element)) }
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inst_vmov_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VMOV, operand_count = 2, length = 4, ops = {op_vr(a), op_vr(b, element), {}, {}} } }
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emit_vmov_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, element: u8 = 0) { append(instructions, inst_vmov_vr_vr(a, b, element)) }
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inst_vrsq_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VRSQ, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vrsq_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vrsq_vr_vr_vr(a, b, c, element)) }
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inst_vrsql_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VRSQL, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vrsql_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vrsql_vr_vr_vr(a, b, c, element)) }
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inst_vrsqh_vr_vr_vr :: #force_inline proc "contextless" (a: Register, b: Register, c: Register, element: u8 = 0) -> Instruction { return Instruction{ mnemonic = .VRSQH, operand_count = 3, length = 4, ops = {op_vr(a), op_vr(b), op_vr(c, element), {}} } }
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emit_vrsqh_vr_vr_vr :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, b: Register, c: Register, element: u8 = 0) { append(instructions, inst_vrsqh_vr_vr_vr(a, b, c, element)) }
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inst_vnop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{ mnemonic = .VNOP, operand_count = 0, length = 4, ops = {{}, {}, {}, {}} } }
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emit_vnop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vnop_none()) }
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inst_lbv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LBV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_lbv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_lbv_vr_vmem(a, m)) }
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inst_lsv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LSV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_lsv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_lsv_vr_vmem(a, m)) }
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inst_llv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LLV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
|
|
emit_llv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_llv_vr_vmem(a, m)) }
|
|
inst_ldv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LDV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
|
|
emit_ldv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_ldv_vr_vmem(a, m)) }
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|
inst_lqv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LQV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
|
|
emit_lqv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_lqv_vr_vmem(a, m)) }
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|
inst_lrv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LRV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
|
|
emit_lrv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_lrv_vr_vmem(a, m)) }
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inst_lpv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LPV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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|
emit_lpv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_lpv_vr_vmem(a, m)) }
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|
inst_luv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LUV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_luv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_luv_vr_vmem(a, m)) }
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inst_lhv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LHV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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|
emit_lhv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_lhv_vr_vmem(a, m)) }
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inst_lfv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LFV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_lfv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_lfv_vr_vmem(a, m)) }
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inst_lwv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LWV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_lwv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_lwv_vr_vmem(a, m)) }
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inst_ltv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .LTV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_ltv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_ltv_vr_vmem(a, m)) }
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inst_sbv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SBV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_sbv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_sbv_vr_vmem(a, m)) }
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inst_ssv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SSV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_ssv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_ssv_vr_vmem(a, m)) }
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inst_slv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SLV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_slv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_slv_vr_vmem(a, m)) }
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inst_sdv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SDV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_sdv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_sdv_vr_vmem(a, m)) }
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inst_sqv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SQV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_sqv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_sqv_vr_vmem(a, m)) }
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inst_srv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SRV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_srv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_srv_vr_vmem(a, m)) }
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inst_spv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SPV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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emit_spv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_spv_vr_vmem(a, m)) }
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inst_suv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SUV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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|
emit_suv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_suv_vr_vmem(a, m)) }
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inst_shv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SHV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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|
emit_shv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_shv_vr_vmem(a, m)) }
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inst_sfv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SFV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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|
emit_sfv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_sfv_vr_vmem(a, m)) }
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inst_swv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .SWV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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|
emit_swv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_swv_vr_vmem(a, m)) }
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inst_stv_vr_vmem :: #force_inline proc "contextless" (a: Register, m: Vector_Mem) -> Instruction { return Instruction{ mnemonic = .STV, operand_count = 2, length = 4, ops = {op_vr(a), op_vmem(m, 16), {}, {}} } }
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|
emit_stv_vr_vmem :: #force_inline proc(instructions: ^[dynamic]Instruction, a: Register, m: Vector_Mem) { append(instructions, inst_stv_vr_vmem(a, m)) }
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|
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// =============================================================================
|
|
// Overload Groups
|
|
// =============================================================================
|
|
|
|
inst_add :: inst_add_gpr_gpr_gpr
|
|
emit_add :: emit_add_gpr_gpr_gpr
|
|
inst_addu :: inst_addu_gpr_gpr_gpr
|
|
emit_addu :: emit_addu_gpr_gpr_gpr
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|
inst_sub :: inst_sub_gpr_gpr_gpr
|
|
emit_sub :: emit_sub_gpr_gpr_gpr
|
|
inst_subu :: inst_subu_gpr_gpr_gpr
|
|
emit_subu :: emit_subu_gpr_gpr_gpr
|
|
inst_and :: inst_and_gpr_gpr_gpr
|
|
emit_and :: emit_and_gpr_gpr_gpr
|
|
inst_or :: inst_or_gpr_gpr_gpr
|
|
emit_or :: emit_or_gpr_gpr_gpr
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|
inst_xor :: inst_xor_gpr_gpr_gpr
|
|
emit_xor :: emit_xor_gpr_gpr_gpr
|
|
inst_nor :: inst_nor_gpr_gpr_gpr
|
|
emit_nor :: emit_nor_gpr_gpr_gpr
|
|
inst_slt :: inst_slt_gpr_gpr_gpr
|
|
emit_slt :: emit_slt_gpr_gpr_gpr
|
|
inst_sltu :: inst_sltu_gpr_gpr_gpr
|
|
emit_sltu :: emit_sltu_gpr_gpr_gpr
|
|
inst_sll :: inst_sll_gpr_gpr_imm5
|
|
emit_sll :: emit_sll_gpr_gpr_imm5
|
|
inst_srl :: inst_srl_gpr_gpr_imm5
|
|
emit_srl :: emit_srl_gpr_gpr_imm5
|
|
inst_sra :: inst_sra_gpr_gpr_imm5
|
|
emit_sra :: emit_sra_gpr_gpr_imm5
|
|
inst_sllv :: inst_sllv_gpr_gpr_gpr
|
|
emit_sllv :: emit_sllv_gpr_gpr_gpr
|
|
inst_srlv :: inst_srlv_gpr_gpr_gpr
|
|
emit_srlv :: emit_srlv_gpr_gpr_gpr
|
|
inst_srav :: inst_srav_gpr_gpr_gpr
|
|
emit_srav :: emit_srav_gpr_gpr_gpr
|
|
inst_addi :: inst_addi_gpr_gpr_imm16
|
|
emit_addi :: emit_addi_gpr_gpr_imm16
|
|
inst_addiu :: inst_addiu_gpr_gpr_imm16
|
|
emit_addiu :: emit_addiu_gpr_gpr_imm16
|
|
inst_slti :: inst_slti_gpr_gpr_imm16
|
|
emit_slti :: emit_slti_gpr_gpr_imm16
|
|
inst_sltiu :: inst_sltiu_gpr_gpr_imm16
|
|
emit_sltiu :: emit_sltiu_gpr_gpr_imm16
|
|
inst_andi :: inst_andi_gpr_gpr_imm16
|
|
emit_andi :: emit_andi_gpr_gpr_imm16
|
|
inst_ori :: inst_ori_gpr_gpr_imm16
|
|
emit_ori :: emit_ori_gpr_gpr_imm16
|
|
inst_xori :: inst_xori_gpr_gpr_imm16
|
|
emit_xori :: emit_xori_gpr_gpr_imm16
|
|
inst_lui :: inst_lui_gpr_imm16
|
|
emit_lui :: emit_lui_gpr_imm16
|
|
inst_beq :: inst_beq_gpr_gpr_rel
|
|
emit_beq :: emit_beq_gpr_gpr_rel
|
|
inst_bne :: inst_bne_gpr_gpr_rel
|
|
emit_bne :: emit_bne_gpr_gpr_rel
|
|
inst_blez :: inst_blez_gpr_rel
|
|
emit_blez :: emit_blez_gpr_rel
|
|
inst_bgtz :: inst_bgtz_gpr_rel
|
|
emit_bgtz :: emit_bgtz_gpr_rel
|
|
inst_bltz :: inst_bltz_gpr_rel
|
|
emit_bltz :: emit_bltz_gpr_rel
|
|
inst_bgez :: inst_bgez_gpr_rel
|
|
emit_bgez :: emit_bgez_gpr_rel
|
|
inst_bltzal :: inst_bltzal_gpr_rel
|
|
emit_bltzal :: emit_bltzal_gpr_rel
|
|
inst_bgezal :: inst_bgezal_gpr_rel
|
|
emit_bgezal :: emit_bgezal_gpr_rel
|
|
inst_j :: inst_j_rel
|
|
emit_j :: emit_j_rel
|
|
inst_jal :: inst_jal_rel
|
|
emit_jal :: emit_jal_rel
|
|
inst_jr :: inst_jr_gpr
|
|
emit_jr :: emit_jr_gpr
|
|
inst_jalr :: inst_jalr_gpr_gpr
|
|
emit_jalr :: emit_jalr_gpr_gpr
|
|
inst_lb :: inst_lb_gpr_mem
|
|
emit_lb :: emit_lb_gpr_mem
|
|
inst_lh :: inst_lh_gpr_mem
|
|
emit_lh :: emit_lh_gpr_mem
|
|
inst_lw :: inst_lw_gpr_mem
|
|
emit_lw :: emit_lw_gpr_mem
|
|
inst_lbu :: inst_lbu_gpr_mem
|
|
emit_lbu :: emit_lbu_gpr_mem
|
|
inst_lhu :: inst_lhu_gpr_mem
|
|
emit_lhu :: emit_lhu_gpr_mem
|
|
inst_sb :: inst_sb_gpr_mem
|
|
emit_sb :: emit_sb_gpr_mem
|
|
inst_sh :: inst_sh_gpr_mem
|
|
emit_sh :: emit_sh_gpr_mem
|
|
inst_sw :: inst_sw_gpr_mem
|
|
emit_sw :: emit_sw_gpr_mem
|
|
inst_break :: inst_break_imm20
|
|
emit_break :: emit_break_imm20
|
|
inst_nop :: inst_nop_none
|
|
emit_nop :: emit_nop_none
|
|
inst_mfc0 :: inst_mfc0_gpr_cp0
|
|
emit_mfc0 :: emit_mfc0_gpr_cp0
|
|
inst_mtc0 :: inst_mtc0_gpr_cp0
|
|
emit_mtc0 :: emit_mtc0_gpr_cp0
|
|
inst_mfc2 :: inst_mfc2_gpr_vr
|
|
emit_mfc2 :: emit_mfc2_gpr_vr
|
|
inst_mtc2 :: inst_mtc2_gpr_vr
|
|
emit_mtc2 :: emit_mtc2_gpr_vr
|
|
inst_cfc2 :: inst_cfc2_gpr_cp2
|
|
emit_cfc2 :: emit_cfc2_gpr_cp2
|
|
inst_ctc2 :: inst_ctc2_gpr_cp2
|
|
emit_ctc2 :: emit_ctc2_gpr_cp2
|
|
inst_vmulf :: inst_vmulf_vr_vr_vr
|
|
emit_vmulf :: emit_vmulf_vr_vr_vr
|
|
inst_vmulu :: inst_vmulu_vr_vr_vr
|
|
emit_vmulu :: emit_vmulu_vr_vr_vr
|
|
inst_vmudl :: inst_vmudl_vr_vr_vr
|
|
emit_vmudl :: emit_vmudl_vr_vr_vr
|
|
inst_vmudm :: inst_vmudm_vr_vr_vr
|
|
emit_vmudm :: emit_vmudm_vr_vr_vr
|
|
inst_vmudn :: inst_vmudn_vr_vr_vr
|
|
emit_vmudn :: emit_vmudn_vr_vr_vr
|
|
inst_vmudh :: inst_vmudh_vr_vr_vr
|
|
emit_vmudh :: emit_vmudh_vr_vr_vr
|
|
inst_vmacf :: inst_vmacf_vr_vr_vr
|
|
emit_vmacf :: emit_vmacf_vr_vr_vr
|
|
inst_vmacu :: inst_vmacu_vr_vr_vr
|
|
emit_vmacu :: emit_vmacu_vr_vr_vr
|
|
inst_vmadl :: inst_vmadl_vr_vr_vr
|
|
emit_vmadl :: emit_vmadl_vr_vr_vr
|
|
inst_vmadm :: inst_vmadm_vr_vr_vr
|
|
emit_vmadm :: emit_vmadm_vr_vr_vr
|
|
inst_vmadn :: inst_vmadn_vr_vr_vr
|
|
emit_vmadn :: emit_vmadn_vr_vr_vr
|
|
inst_vmadh :: inst_vmadh_vr_vr_vr
|
|
emit_vmadh :: emit_vmadh_vr_vr_vr
|
|
inst_vadd :: inst_vadd_vr_vr_vr
|
|
emit_vadd :: emit_vadd_vr_vr_vr
|
|
inst_vsub :: inst_vsub_vr_vr_vr
|
|
emit_vsub :: emit_vsub_vr_vr_vr
|
|
inst_vabs :: inst_vabs_vr_vr_vr
|
|
emit_vabs :: emit_vabs_vr_vr_vr
|
|
inst_vaddc :: inst_vaddc_vr_vr_vr
|
|
emit_vaddc :: emit_vaddc_vr_vr_vr
|
|
inst_vsubc :: inst_vsubc_vr_vr_vr
|
|
emit_vsubc :: emit_vsubc_vr_vr_vr
|
|
inst_vsar :: inst_vsar_vr_vr_vr
|
|
emit_vsar :: emit_vsar_vr_vr_vr
|
|
inst_vlt :: inst_vlt_vr_vr_vr
|
|
emit_vlt :: emit_vlt_vr_vr_vr
|
|
inst_veq :: inst_veq_vr_vr_vr
|
|
emit_veq :: emit_veq_vr_vr_vr
|
|
inst_vne :: inst_vne_vr_vr_vr
|
|
emit_vne :: emit_vne_vr_vr_vr
|
|
inst_vge :: inst_vge_vr_vr_vr
|
|
emit_vge :: emit_vge_vr_vr_vr
|
|
inst_vcl :: inst_vcl_vr_vr_vr
|
|
emit_vcl :: emit_vcl_vr_vr_vr
|
|
inst_vch :: inst_vch_vr_vr_vr
|
|
emit_vch :: emit_vch_vr_vr_vr
|
|
inst_vcr :: inst_vcr_vr_vr_vr
|
|
emit_vcr :: emit_vcr_vr_vr_vr
|
|
inst_vmrg :: inst_vmrg_vr_vr_vr
|
|
emit_vmrg :: emit_vmrg_vr_vr_vr
|
|
inst_vand :: inst_vand_vr_vr_vr
|
|
emit_vand :: emit_vand_vr_vr_vr
|
|
inst_vnand :: inst_vnand_vr_vr_vr
|
|
emit_vnand :: emit_vnand_vr_vr_vr
|
|
inst_vor :: inst_vor_vr_vr_vr
|
|
emit_vor :: emit_vor_vr_vr_vr
|
|
inst_vnor :: inst_vnor_vr_vr_vr
|
|
emit_vnor :: emit_vnor_vr_vr_vr
|
|
inst_vxor :: inst_vxor_vr_vr_vr
|
|
emit_vxor :: emit_vxor_vr_vr_vr
|
|
inst_vnxor :: inst_vnxor_vr_vr_vr
|
|
emit_vnxor :: emit_vnxor_vr_vr_vr
|
|
inst_vrcp :: inst_vrcp_vr_vr_vr
|
|
emit_vrcp :: emit_vrcp_vr_vr_vr
|
|
inst_vrcpl :: inst_vrcpl_vr_vr_vr
|
|
emit_vrcpl :: emit_vrcpl_vr_vr_vr
|
|
inst_vrcph :: inst_vrcph_vr_vr_vr
|
|
emit_vrcph :: emit_vrcph_vr_vr_vr
|
|
inst_vmov :: inst_vmov_vr_vr
|
|
emit_vmov :: emit_vmov_vr_vr
|
|
inst_vrsq :: inst_vrsq_vr_vr_vr
|
|
emit_vrsq :: emit_vrsq_vr_vr_vr
|
|
inst_vrsql :: inst_vrsql_vr_vr_vr
|
|
emit_vrsql :: emit_vrsql_vr_vr_vr
|
|
inst_vrsqh :: inst_vrsqh_vr_vr_vr
|
|
emit_vrsqh :: emit_vrsqh_vr_vr_vr
|
|
inst_vnop :: inst_vnop_none
|
|
emit_vnop :: emit_vnop_none
|
|
inst_lbv :: inst_lbv_vr_vmem
|
|
emit_lbv :: emit_lbv_vr_vmem
|
|
inst_lsv :: inst_lsv_vr_vmem
|
|
emit_lsv :: emit_lsv_vr_vmem
|
|
inst_llv :: inst_llv_vr_vmem
|
|
emit_llv :: emit_llv_vr_vmem
|
|
inst_ldv :: inst_ldv_vr_vmem
|
|
emit_ldv :: emit_ldv_vr_vmem
|
|
inst_lqv :: inst_lqv_vr_vmem
|
|
emit_lqv :: emit_lqv_vr_vmem
|
|
inst_lrv :: inst_lrv_vr_vmem
|
|
emit_lrv :: emit_lrv_vr_vmem
|
|
inst_lpv :: inst_lpv_vr_vmem
|
|
emit_lpv :: emit_lpv_vr_vmem
|
|
inst_luv :: inst_luv_vr_vmem
|
|
emit_luv :: emit_luv_vr_vmem
|
|
inst_lhv :: inst_lhv_vr_vmem
|
|
emit_lhv :: emit_lhv_vr_vmem
|
|
inst_lfv :: inst_lfv_vr_vmem
|
|
emit_lfv :: emit_lfv_vr_vmem
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inst_lwv :: inst_lwv_vr_vmem
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emit_lwv :: emit_lwv_vr_vmem
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inst_ltv :: inst_ltv_vr_vmem
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emit_ltv :: emit_ltv_vr_vmem
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inst_sbv :: inst_sbv_vr_vmem
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emit_sbv :: emit_sbv_vr_vmem
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inst_ssv :: inst_ssv_vr_vmem
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emit_ssv :: emit_ssv_vr_vmem
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inst_slv :: inst_slv_vr_vmem
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emit_slv :: emit_slv_vr_vmem
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inst_sdv :: inst_sdv_vr_vmem
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emit_sdv :: emit_sdv_vr_vmem
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inst_sqv :: inst_sqv_vr_vmem
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emit_sqv :: emit_sqv_vr_vmem
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inst_srv :: inst_srv_vr_vmem
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emit_srv :: emit_srv_vr_vmem
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inst_spv :: inst_spv_vr_vmem
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emit_spv :: emit_spv_vr_vmem
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inst_suv :: inst_suv_vr_vmem
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emit_suv :: emit_suv_vr_vmem
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inst_shv :: inst_shv_vr_vmem
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emit_shv :: emit_shv_vr_vmem
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inst_sfv :: inst_sfv_vr_vmem
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emit_sfv :: emit_sfv_vr_vmem
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inst_swv :: inst_swv_vr_vmem
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emit_swv :: emit_swv_vr_vmem
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inst_stv :: inst_stv_vr_vmem
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emit_stv :: emit_stv_vr_vmem
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