mirror of
https://github.com/odin-lang/Odin.git
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fae15847a3
Roll the encode/decode buffer-sizing helpers (added for x86 in 49787b7de) out
to every other ISA, and document them in the cross-arch naming contract.
Per arch (arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816):
- encode_max_code_size / encode_max_relocation_count now key off the
[]Instruction slice (were int counts); bodies unchanged (* MAX_INST_SIZE).
- encode_reserve(code, relocs, instructions): grows the caller's code []u8 by
length and reserves relocs by capacity; allocates no new buffers.
- decode_max_instruction_count / decode_estimate_instruction_count: exact
ceiling and typical estimate, keyed off the min/avg instruction size per
arch (fixed-4: arm64/mips/ppc/rsp; min-2: arm32/riscv/ppc_vle; min-1: mos).
- decode_reserve(instructions, inst_info, label_defs, data, exact=false).
docs/cross_arch_design.md: helpers added to the naming contract.
No behavior change to the existing size helpers (signature only). All 10 ISAs
check + test green (x86 2282, arm32 600, arm64 461, mips 281, riscv 154, ppc 31,
ppc_vle 281, rsp 70, mos6502 148, mos65816 53).
315 lines
10 KiB
Odin
315 lines
10 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mos65816
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import "core:rexcode/isa"
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// =============================================================================
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// W65C816S ENCODER
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// =============================================================================
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//
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// Variable-length 1..4 byte pipeline. Same 2-pass shape as mos6502/encoder.
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// The 65816-specific twists:
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//
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// * Mode-dependent immediates: the matcher distinguishes IMM_M8/IMM_M16
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// and IMM_X8/IMM_X16 by `op.size`. The user picks which width to emit
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// via `inst_i8` or `inst_i16` and the encoder produces the matching
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// opcode form.
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//
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// * 24-bit addresses: long ($nnnnnn) and long,X forms emit 3 LE bytes.
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//
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// * Block moves (MVN/MVP): the source-then-destination user syntax is
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// emitted as `opcode | dst_bank | src_bank` -- the encoder routes
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// ops[0] -> BYTE_2_BANK (offset 2) and ops[1] -> BYTE_1_BANK (offset 1).
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MAX_INST_SIZE :: 4
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encode_max_code_size :: #force_inline proc "contextless" (instructions: []Instruction) -> int {
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return len(instructions) * MAX_INST_SIZE
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}
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encode_max_relocation_count :: #force_inline proc "contextless" (instructions: []Instruction) -> int {
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return len(instructions)
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}
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// Pre-size the caller's encode outputs (code grown by length so code[:] is a
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// valid emit target; relocs reserved by capacity) so the encode hot path never
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// reallocates. Allocates no new buffers; pass nil to skip either array.
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encode_reserve :: proc(code: ^[dynamic]u8, relocs: ^[dynamic]Relocation, instructions: []Instruction) {
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if code != nil {
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size := encode_max_code_size(instructions)
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if len(code) < size {
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resize(code, size)
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}
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}
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if relocs != nil {
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reserve(relocs, len(relocs) + encode_max_relocation_count(instructions))
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}
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}
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encode :: proc(
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instructions: []Instruction,
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label_defs: []Label_Definition,
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code: []u8,
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relocs: ^[dynamic]Relocation,
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errors: ^[dynamic]Error,
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resolve: bool = true,
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base_address: u64 = 0,
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) -> (byte_count: u32, ok: bool) {
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n_inst := u32(len(instructions))
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errors_start := u32(len(errors))
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pending_start := u32(len(relocs))
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inst_offsets := make([]u32, n_inst, context.temp_allocator)
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for i in 0..<n_inst {
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inst_offsets[i] = byte_count
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inst := &instructions[i]
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form := find_form_inline(inst, u16(i), errors) or_return
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if byte_count + u32(form.length) > u32(len(code)) {
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append(errors, Error{inst_idx = i, code = .BUFFER_OVERFLOW})
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return
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}
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code[byte_count] = form.opcode
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if form.enc[0] != .NONE { pack_operand_inline(&inst.ops[0], form.enc[0], byte_count, u16(i), code, relocs) }
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if form.enc[1] != .NONE { pack_operand_inline(&inst.ops[1], form.enc[1], byte_count, u16(i), code, relocs) }
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inst.length = form.length
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byte_count += u32(form.length)
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}
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isa.rewrite_label_defs_to_offsets(label_defs, inst_offsets)
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if !resolve {
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ok = u32(len(errors)) == errors_start
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return
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}
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n_relocs := u32(len(relocs))
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write_idx := pending_start
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for read_idx in pending_start..<n_relocs {
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r := relocs[read_idx]
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if resolve_relocation_inline(code, label_defs, &r, base_address, errors) {
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continue
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}
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if write_idx != read_idx {
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relocs[write_idx] = r
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}
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write_idx += 1
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}
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if write_idx != n_relocs {
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resize(relocs, int(write_idx))
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}
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ok = u32(len(errors)) == errors_start
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return
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}
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// =============================================================================
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// Internal: form matching / operand packing
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// =============================================================================
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@(private="file")
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find_form_inline :: #force_inline proc(
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inst: ^Instruction, inst_idx: u16, errors: ^[dynamic]Error,
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) -> (form: ^Encoding, ok: bool) {
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if inst.mnemonic == .INVALID {
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append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC})
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return nil, false
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}
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forms := encoding_forms(inst.mnemonic)
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if len(forms) == 0 {
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append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC})
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return nil, false
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}
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for &f in forms {
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if encoding_matches_inline(inst, &f) {
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return &f, true
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}
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}
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append(errors, Error{inst_idx = u32(inst_idx), code = .NO_MATCHING_ENCODING})
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return nil, false
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}
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@(private="file")
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encoding_matches_inline :: #force_inline proc "contextless" (
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inst: ^Instruction, form: ^Encoding,
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) -> bool {
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return operand_matches_inline(&inst.ops[0], form.ops[0]) &&
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operand_matches_inline(&inst.ops[1], form.ops[1])
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}
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@(private="file")
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operand_matches_inline :: #force_inline proc "contextless" (
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op: ^Operand, ot: Operand_Type,
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) -> bool {
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switch ot {
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case .NONE: return op.kind == .NONE
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case .A_IMPL: return op.kind == .REGISTER && op.reg == A
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case .IMM_8: return op.kind == .IMMEDIATE && op.size == 1
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case .IMM_M8: return op.kind == .IMMEDIATE && op.size == 1
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case .IMM_M16: return op.kind == .IMMEDIATE && op.size == 2
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case .IMM_X8: return op.kind == .IMMEDIATE && op.size == 1
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case .IMM_X16: return op.kind == .IMMEDIATE && op.size == 2
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case .REL: return op.kind == .RELATIVE && op.size == 1
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case .REL_LONG: return op.kind == .RELATIVE && op.size == 2
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case .MEM_DP: return op.kind == .MEMORY && op.mem.mode == .DP
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case .MEM_DP_X: return op.kind == .MEMORY && op.mem.mode == .DP_X
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case .MEM_DP_Y: return op.kind == .MEMORY && op.mem.mode == .DP_Y
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case .MEM_DP_IND: return op.kind == .MEMORY && op.mem.mode == .DP_IND
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case .MEM_DP_IND_X: return op.kind == .MEMORY && op.mem.mode == .DP_IND_X
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case .MEM_DP_IND_Y: return op.kind == .MEMORY && op.mem.mode == .DP_IND_Y
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case .MEM_DP_IND_LONG: return op.kind == .MEMORY && op.mem.mode == .DP_IND_LONG
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case .MEM_DP_IND_LONG_Y: return op.kind == .MEMORY && op.mem.mode == .DP_IND_LONG_Y
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// MEM_ABS / MEM_LONG also accept RELATIVE-kind labels for forward
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// references (JMP/JSR/JML/JSL to a label).
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case .MEM_ABS: return (op.kind == .MEMORY && op.mem.mode == .ABS) ||
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(op.kind == .RELATIVE && op.size == 2)
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case .MEM_ABS_X: return op.kind == .MEMORY && op.mem.mode == .ABS_X
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case .MEM_ABS_Y: return op.kind == .MEMORY && op.mem.mode == .ABS_Y
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case .MEM_ABS_IND: return op.kind == .MEMORY && op.mem.mode == .ABS_IND
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case .MEM_ABS_IND_LONG: return op.kind == .MEMORY && op.mem.mode == .ABS_IND_LONG
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case .MEM_ABS_IND_X: return op.kind == .MEMORY && op.mem.mode == .ABS_IND_X
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case .MEM_LONG: return (op.kind == .MEMORY && op.mem.mode == .LONG) ||
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(op.kind == .RELATIVE && op.size == 3)
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case .MEM_LONG_X: return op.kind == .MEMORY && op.mem.mode == .LONG_X
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case .MEM_SR: return op.kind == .MEMORY && op.mem.mode == .SR
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case .MEM_SR_IND_Y: return op.kind == .MEMORY && op.mem.mode == .SR_IND_Y
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case .BANK_SRC: return op.kind == .IMMEDIATE
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case .BANK_DST: return op.kind == .IMMEDIATE
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}
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return false
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}
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@(private="file")
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pack_operand_inline :: #force_inline proc(
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op: ^Operand,
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enc: Operand_Encoding,
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pc: u32,
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inst_idx: u16,
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code: []u8,
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relocs: ^[dynamic]Relocation,
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) {
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switch enc {
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case .NONE, .IMPL:
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case .BYTE_1_IMM:
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code[pc+1] = u8(op.immediate)
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case .WORD_1_IMM:
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v := u16(op.immediate)
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code[pc+1] = u8(v)
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code[pc+2] = u8(v >> 8)
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case .BYTE_1_ADDR:
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code[pc+1] = u8(op.mem.address)
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case .WORD_1_ADDR:
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if op.kind == .RELATIVE {
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append(relocs, Relocation{
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offset = pc + 1, label_id = u32(op.relative),
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type = .ABS16, size = 2, inst_idx = inst_idx,
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})
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code[pc+1] = 0
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code[pc+2] = 0
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} else {
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addr := u16(op.mem.address)
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code[pc+1] = u8(addr)
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code[pc+2] = u8(addr >> 8)
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}
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case .LONG_1_ADDR:
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if op.kind == .RELATIVE {
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append(relocs, Relocation{
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offset = pc + 1, label_id = u32(op.relative),
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type = .ABS24, size = 3, inst_idx = inst_idx,
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})
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code[pc+1] = 0
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code[pc+2] = 0
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code[pc+3] = 0
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} else {
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addr := op.mem.address & 0xFFFFFF
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code[pc+1] = u8(addr)
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code[pc+2] = u8(addr >> 8)
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code[pc+3] = u8(addr >> 16)
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}
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case .BYTE_1_REL:
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append(relocs, Relocation{
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offset = pc + 1, label_id = u32(op.relative),
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type = .REL8, size = 1, inst_idx = inst_idx,
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})
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code[pc+1] = 0
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case .WORD_1_REL:
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append(relocs, Relocation{
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offset = pc + 1, label_id = u32(op.relative),
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type = .REL16, size = 2, inst_idx = inst_idx,
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})
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code[pc+1] = 0
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code[pc+2] = 0
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case .BYTE_1_BANK:
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code[pc+1] = u8(op.immediate)
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case .BYTE_2_BANK:
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code[pc+2] = u8(op.immediate)
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}
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}
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// =============================================================================
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// Pass 2 -- relocation resolver
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// =============================================================================
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@(private="file")
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resolve_relocation_inline :: #force_inline proc(
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code: []u8,
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label_defs: []Label_Definition,
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relocation: ^Relocation,
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base_address: u64,
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errors: ^[dynamic]Error,
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) -> bool {
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if int(relocation.label_id) >= len(label_defs) { return false }
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ld := label_defs[relocation.label_id]
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if ld == LABEL_UNDEFINED { return false }
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target := u32(ld)
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switch relocation.type {
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case .REL8:
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next_pc := relocation.offset + 1
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rel := i32(target) - i32(next_pc) + relocation.addend
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if rel < -128 || rel > 127 {
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append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
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code[relocation.offset] = u8(i8(rel))
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return true
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}
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code[relocation.offset] = u8(i8(rel))
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case .REL16:
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next_pc := relocation.offset + 2
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rel := i32(target) - i32(next_pc) + relocation.addend
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if rel < -32768 || rel > 32767 {
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append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
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}
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v := u16(rel)
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code[relocation.offset+0] = u8(v)
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code[relocation.offset+1] = u8(v >> 8)
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case .ABS16:
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abs := u16(u64(target) + base_address + u64(relocation.addend))
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code[relocation.offset+0] = u8(abs)
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code[relocation.offset+1] = u8(abs >> 8)
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case .ABS24:
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abs := u32((u64(target) + base_address + u64(relocation.addend)) & 0xFFFFFF)
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code[relocation.offset+0] = u8(abs)
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code[relocation.offset+1] = u8(abs >> 8)
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code[relocation.offset+2] = u8(abs >> 16)
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case .NONE:
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return false
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}
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return true
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}
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