mirror of
https://github.com/odin-lang/Odin.git
synced 2026-06-19 08:32:33 +00:00
fae15847a3
Roll the encode/decode buffer-sizing helpers (added for x86 in 49787b7de) out
to every other ISA, and document them in the cross-arch naming contract.
Per arch (arm32, arm64, mips, riscv, ppc, ppc_vle, rsp, mos6502, mos65816):
- encode_max_code_size / encode_max_relocation_count now key off the
[]Instruction slice (were int counts); bodies unchanged (* MAX_INST_SIZE).
- encode_reserve(code, relocs, instructions): grows the caller's code []u8 by
length and reserves relocs by capacity; allocates no new buffers.
- decode_max_instruction_count / decode_estimate_instruction_count: exact
ceiling and typical estimate, keyed off the min/avg instruction size per
arch (fixed-4: arm64/mips/ppc/rsp; min-2: arm32/riscv/ppc_vle; min-1: mos).
- decode_reserve(instructions, inst_info, label_defs, data, exact=false).
docs/cross_arch_design.md: helpers added to the naming contract.
No behavior change to the existing size helpers (signature only). All 10 ISAs
check + test green (x86 2282, arm32 600, arm64 461, mips 281, riscv 154, ppc 31,
ppc_vle 281, rsp 70, mos6502 148, mos65816 53).
598 lines
20 KiB
Odin
598 lines
20 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_riscv
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// =============================================================================
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// RISC-V ENCODER
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// =============================================================================
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//
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// Fixed-width 4-byte ISA. Two-pass design mirroring mips/encoder.odin:
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//
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// PASS 1 - encode each instruction to a u32 word; emit Relocation
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// entries for B-type (BRANCH) and J-type (JAL) operands.
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// PASS 1.5 - rewrite label_defs from instruction-index to byte-offset
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// (just multiply by 4).
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// PASS 2 - patch resolvable BRANCH / JAL relocations.
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//
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// The interesting bits vs other arches:
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//
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// * The B-type and J-type immediates are *scattered* across non-
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// contiguous positions in the word. `scatter_b` and `scatter_j`
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// rearrange a contiguous signed value into the wire bits.
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//
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// * Memory operands come in three flavours -- OFFSET_BASE_I for loads
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// and JALR (I-type imm), OFFSET_BASE_S for stores (S-type scatter),
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// and OFFSET_BASE_A for atomics (rs1 only, disp must be 0).
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MAX_INST_SIZE :: 4
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encode_max_code_size :: #force_inline proc "contextless" (instructions: []Instruction) -> int {
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return len(instructions) * MAX_INST_SIZE
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}
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encode_max_relocation_count :: #force_inline proc "contextless" (instructions: []Instruction) -> int {
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return len(instructions)
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}
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// Pre-size the caller's encode outputs (code grown by length so code[:] is a
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// valid emit target; relocs reserved by capacity) so the encode hot path never
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// reallocates. Allocates no new buffers; pass nil to skip either array.
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encode_reserve :: proc(code: ^[dynamic]u8, relocs: ^[dynamic]Relocation, instructions: []Instruction) {
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if code != nil {
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size := encode_max_code_size(instructions)
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if len(code) < size {
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resize(code, size)
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}
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}
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if relocs != nil {
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reserve(relocs, len(relocs) + encode_max_relocation_count(instructions))
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}
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}
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encode :: proc(
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instructions: []Instruction,
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label_defs: []Label_Definition,
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code: []u8,
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relocs: ^[dynamic]Relocation,
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errors: ^[dynamic]Error,
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resolve: bool = true,
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base_address: u64 = 0,
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) -> (byte_count: u32, ok: bool) {
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n_inst := u32(len(instructions))
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if u32(len(code)) < n_inst * 4 {
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append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW})
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return
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}
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errors_start := u32(len(errors))
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pending_start := u32(len(relocs))
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// Per-instruction byte offsets so label_defs (instruction-indexed)
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// can be rewritten to byte-offset after pass 1 in the presence of
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// mixed 2/4-byte (RVC) instructions.
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inst_pc := make([]u32, n_inst, context.temp_allocator)
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// ---- PASS 1 -----------------------------------------------------------
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for i in 0..<n_inst {
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inst_pc[i] = byte_count
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inst := &instructions[i]
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word, ilen := encode_one_inline(inst, byte_count, u16(i), relocs, errors) or_return
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if ilen == 2 {
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write_u16_le(code, byte_count, u16(word))
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} else {
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write_u32_le(code, byte_count, word)
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}
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byte_count += u32(ilen)
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}
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// ---- PASS 1.5: rewrite label_defs (instruction-index -> byte-offset) --
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for &ld in label_defs {
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if ld != LABEL_UNDEFINED {
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idx := u32(ld)
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if idx < n_inst {
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ld = Label_Definition(inst_pc[idx])
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} else {
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ld = LABEL_UNDEFINED
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}
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}
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}
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if !resolve {
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ok = u32(len(errors)) == errors_start
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return
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}
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// ---- PASS 2: resolve relocations --------------------------------------
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n_relocs := u32(len(relocs))
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write_idx := pending_start
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for read_idx in pending_start..<n_relocs {
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r := relocs[read_idx]
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if resolve_relocation_inline(code, label_defs, &r, base_address, errors) {
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continue
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}
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if write_idx != read_idx { relocs[write_idx] = r }
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write_idx += 1
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}
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if write_idx != n_relocs { resize(relocs, int(write_idx)) }
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ok = u32(len(errors)) == errors_start
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return
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}
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// =============================================================================
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// Internal: encode one instruction
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// =============================================================================
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@(private="file")
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encode_one_inline :: #force_inline proc(
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inst: ^Instruction,
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pc: u32,
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inst_idx: u16,
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relocs: ^[dynamic]Relocation,
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errors: ^[dynamic]Error,
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) -> (word: u32, ilen: u8, ok: bool) {
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if inst.mnemonic == .INVALID {
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append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC})
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return 0, 0, false
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}
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forms := encoding_forms(inst.mnemonic)
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if len(forms) == 0 {
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append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC})
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return 0, 0, false
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}
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form: ^Encoding
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for &f in forms {
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if encoding_matches_inline(inst, &f) {
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form = &f
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break
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}
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}
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if form == nil {
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append(errors, Error{inst_idx = u32(inst_idx), code = .NO_MATCHING_ENCODING})
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return 0, 0, false
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}
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word = form.bits
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if form.enc[0] != .NONE { word |= pack_operand_inline(&inst.ops[0], form.enc[0], pc, inst_idx, relocs) }
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if form.enc[1] != .NONE { word |= pack_operand_inline(&inst.ops[1], form.enc[1], pc, inst_idx, relocs) }
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if form.enc[2] != .NONE { word |= pack_operand_inline(&inst.ops[2], form.enc[2], pc, inst_idx, relocs) }
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if form.enc[3] != .NONE { word |= pack_operand_inline(&inst.ops[3], form.enc[3], pc, inst_idx, relocs) }
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return word, inst_size_from_bits(form.bits), true
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}
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@(private="file")
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encoding_matches_inline :: #force_inline proc "contextless" (
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inst: ^Instruction, form: ^Encoding,
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) -> bool {
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return operand_matches_inline(&inst.ops[0], form.ops[0]) &&
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operand_matches_inline(&inst.ops[1], form.ops[1]) &&
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operand_matches_inline(&inst.ops[2], form.ops[2]) &&
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operand_matches_inline(&inst.ops[3], form.ops[3])
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}
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@(private="file")
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operand_matches_inline :: #force_inline proc "contextless" (
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op: ^Operand, ot: Operand_Type,
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) -> bool {
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switch ot {
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case .NONE: return op.kind == .NONE
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case .GPR: return op.kind == .REGISTER && reg_class(op.reg) == REG_GPR
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case .FPR: return op.kind == .REGISTER && reg_class(op.reg) == REG_FPR
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case .IMM12, .IMM12U, .IMM5, .IMM6, .IMM20,
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.CSR, .FENCE_FLAGS, .ROUND_MODE, .ZIMM5,
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.IMM_C6S, .IMM_C6U, .IMM_C8U, .IMM_C10S, .IMM_C18S:
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return op.kind == .IMMEDIATE
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case .REL13, .REL21, .REL9, .REL12:
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return op.kind == .RELATIVE
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case .MEM, .MEM_C_W, .MEM_C_D, .MEM_C_SP_W, .MEM_C_SP_D:
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return op.kind == .MEMORY
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// ---- C extension ----
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case .GPR_C:
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if op.kind != .REGISTER || reg_class(op.reg) != REG_GPR { return false }
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hw := reg_hw(op.reg)
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return hw >= 8 && hw <= 15
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case .FPR_C:
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if op.kind != .REGISTER || reg_class(op.reg) != REG_FPR { return false }
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hw := reg_hw(op.reg)
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return hw >= 8 && hw <= 15
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case .GPR_SP:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_GPR && reg_hw(op.reg) == 2
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case .GPR_NONZERO:
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return op.kind == .REGISTER && reg_class(op.reg) == REG_GPR && reg_hw(op.reg) != 0
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}
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return false
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}
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// =============================================================================
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// Operand packer
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// =============================================================================
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@(private="file")
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pack_operand_inline :: #force_inline proc(
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op: ^Operand,
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enc: Operand_Encoding,
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pc: u32,
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inst_idx: u16,
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relocs: ^[dynamic]Relocation,
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) -> u32 {
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switch enc {
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case .NONE:
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return 0
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// ---- Register slots ----------------------------------------------------
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case .RD: return (u32(reg_hw(op.reg)) & 0x1F) << 7
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case .RS1: return (u32(reg_hw(op.reg)) & 0x1F) << 15
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case .RS2: return (u32(reg_hw(op.reg)) & 0x1F) << 20
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case .RS3: return (u32(reg_hw(op.reg)) & 0x1F) << 27
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// ---- Shift amounts -----------------------------------------------------
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case .SHAMT5: return (u32(op.immediate) & 0x1F) << 20
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case .SHAMT6: return (u32(op.immediate) & 0x3F) << 20
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// ---- Immediates --------------------------------------------------------
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case .IMM_I:
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return (u32(op.immediate) & 0xFFF) << 20
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case .IMM_S:
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v := u32(op.immediate)
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return ((v >> 5) & 0x7F) << 25 | (v & 0x1F) << 7
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case .IMM_U:
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return (u32(op.immediate) & 0xFFFFF) << 12
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case .IMM_B:
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// B-type PC-rel branch. Always paired with a RELATIVE operand
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// (label or raw offset).
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .BRANCH, size = 4, inst_idx = inst_idx,
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})
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return 0
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case .IMM_J:
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// J-type PC-rel JAL.
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .JAL, size = 4, inst_idx = inst_idx,
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})
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return 0
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// ---- Memory operand variants ------------------------------------------
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case .OFFSET_BASE_I:
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base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 15
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imm_bits := (u32(op.mem.disp) & 0xFFF) << 20
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return base_bits | imm_bits
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case .OFFSET_BASE_S:
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base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 15
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v := u32(op.mem.disp)
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imm_bits := ((v >> 5) & 0x7F) << 25 | (v & 0x1F) << 7
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return base_bits | imm_bits
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case .OFFSET_BASE_A:
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return (u32(reg_hw(op.mem.base)) & 0x1F) << 15
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// ---- Specialty fields --------------------------------------------------
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case .CSR_FIELD:
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return (u32(op.immediate) & 0xFFF) << 20
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case .ZIMM_FIELD:
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return (u32(op.immediate) & 0x1F) << 15
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case .FENCE_PRED:
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return (u32(op.immediate) & 0xF) << 24
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case .FENCE_SUCC:
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return (u32(op.immediate) & 0xF) << 20
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case .ROUND_FIELD:
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return (u32(op.immediate) & 0x7) << 12
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case .AQRL:
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return (u32(op.immediate) & 0x3) << 25
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// ---- C extension register slots ---------------------------------------
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case .C_RD_RS1:
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return (u32(reg_hw(op.reg)) & 0x1F) << 7
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case .C_RS2:
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return (u32(reg_hw(op.reg)) & 0x1F) << 2
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case .C_RD_PRIMED, .C_RS2_PRIMED:
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return (u32(reg_hw(op.reg)) & 0x7) << 2
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case .C_RS1_PRIMED, .C_RD_RS1_PRIMED:
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return (u32(reg_hw(op.reg)) & 0x7) << 7
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// ---- C extension immediates -------------------------------------------
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case .C_IMM_CI_S, .C_IMM_CI_U:
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// CI-form 6-bit imm: bit 5 -> bit 12, bits 4:0 -> bits 6:2.
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v := u32(op.immediate)
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return ((v >> 5) & 0x1) << 12 | (v & 0x1F) << 2
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case .C_IMM_CIW:
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// C.ADDI4SPN: imm[9:2] (multiple of 4, non-zero) packed as:
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// imm[5:4] @ 12:11, imm[9:6] @ 10:7, imm[2] @ 6, imm[3] @ 5
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// imm here is the byte offset (already times 4 in the source).
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v := u32(op.immediate)
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return ((v >> 4) & 0x3) << 11 |
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((v >> 6) & 0xF) << 7 |
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((v >> 2) & 0x1) << 6 |
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((v >> 3) & 0x1) << 5
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case .C_IMM_LUI:
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// C.LUI: imm[17:12] sign-extended. imm[17] @12, imm[16:12] @6:2.
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v := u32(op.immediate) >> 12
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return ((v >> 5) & 0x1) << 12 | (v & 0x1F) << 2
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case .C_IMM_ADDI16SP:
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// C.ADDI16SP: imm[9:4] non-zero, scaled by 16. Encoded as:
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// imm[9] @12, imm[4] @6, imm[6] @5, imm[8:7] @4:3, imm[5] @2
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v := u32(op.immediate)
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return ((v >> 9) & 0x1) << 12 |
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((v >> 4) & 0x1) << 6 |
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((v >> 6) & 0x1) << 5 |
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((v >> 7) & 0x3) << 3 |
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((v >> 5) & 0x1) << 2
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case .C_IMM_CSS_W:
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// C.SWSP: imm scaled by 4, range 0..252. imm[5:2] @ 12:9, imm[7:6] @ 8:7.
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v := u32(op.immediate)
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return ((v >> 2) & 0xF) << 9 | ((v >> 6) & 0x3) << 7
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case .C_IMM_CSS_D:
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// C.SDSP: imm scaled by 8, range 0..504. imm[5:3] @ 12:10, imm[8:6] @ 9:7.
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v := u32(op.immediate)
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return ((v >> 3) & 0x7) << 10 | ((v >> 6) & 0x7) << 7
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case .C_IMM_CL_W:
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// C.LW/SW: imm[5:3] @12:10, imm[2] @6, imm[6] @5. Scaled by 4 (0..124).
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v := u32(op.immediate)
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return ((v >> 3) & 0x7) << 10 | ((v >> 2) & 0x1) << 6 | ((v >> 6) & 0x1) << 5
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case .C_IMM_CL_D:
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// C.LD/SD: imm[5:3] @12:10, imm[7:6] @6:5. Scaled by 8 (0..248).
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v := u32(op.immediate)
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return ((v >> 3) & 0x7) << 10 | ((v >> 6) & 0x3) << 5
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// ---- C extension memory operands --------------------------------------
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case .C_OFFSET_BASE_W:
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// [rs1', disp] with disp scaled by 4.
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base := (u32(reg_hw(op.mem.base)) & 0x7) << 7
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v := u32(op.mem.disp)
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imm := ((v >> 3) & 0x7) << 10 | ((v >> 2) & 0x1) << 6 | ((v >> 6) & 0x1) << 5
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return base | imm
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case .C_OFFSET_BASE_D:
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base := (u32(reg_hw(op.mem.base)) & 0x7) << 7
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v := u32(op.mem.disp)
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imm := ((v >> 3) & 0x7) << 10 | ((v >> 6) & 0x3) << 5
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return base | imm
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case .C_SP_OFFSET_W:
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// C.LWSP: imm[5] @12, imm[4:2] @6:4, imm[7:6] @3:2. Base is implicit SP.
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v := u32(op.mem.disp)
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return ((v >> 5) & 0x1) << 12 | ((v >> 2) & 0x7) << 4 | ((v >> 6) & 0x3) << 2
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case .C_SP_OFFSET_D:
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// C.LDSP: imm[5] @12, imm[4:3] @6:5, imm[8:6] @4:2. Base is implicit SP.
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v := u32(op.mem.disp)
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return ((v >> 5) & 0x1) << 12 | ((v >> 3) & 0x3) << 5 | ((v >> 6) & 0x7) << 2
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// ---- C extension PC-relative branches/jumps ---------------------------
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case .C_BRANCH9:
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .C_BRANCH, size = 2, inst_idx = inst_idx,
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})
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return 0
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case .C_BRANCH12:
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append(relocs, Relocation{
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offset = pc, label_id = u32(op.relative),
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type = .C_JUMP, size = 2, inst_idx = inst_idx,
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})
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return 0
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}
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return 0
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}
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// =============================================================================
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// Pass 2 -- relocation resolver
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// =============================================================================
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@(private="file")
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resolve_relocation_inline :: #force_inline proc(
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code: []u8,
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label_defs: []Label_Definition,
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relocation: ^Relocation,
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base_address: u64,
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errors: ^[dynamic]Error,
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) -> bool {
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if int(relocation.label_id) >= len(label_defs) { return false }
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ld := label_defs[relocation.label_id]
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if ld == LABEL_UNDEFINED { return false }
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target := u32(ld)
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// 16-bit (RVC) relocations write a halfword; 32-bit ones write a full word.
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if relocation.size == 2 {
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hword := read_u16_le(code, relocation.offset)
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switch relocation.type {
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case .C_BRANCH:
|
|
rel := i32(target) - i32(relocation.offset) + relocation.addend
|
|
if rel & 1 != 0 || rel < -256 || rel > 254 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
hword |= u16(scatter_c_branch(u32(rel)))
|
|
case .C_JUMP:
|
|
rel := i32(target) - i32(relocation.offset) + relocation.addend
|
|
if rel & 1 != 0 || rel < -2048 || rel > 2046 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
hword |= u16(scatter_c_jump(u32(rel)))
|
|
case .NONE, .BRANCH, .JAL, .PCREL_HI20, .PCREL_LO12_I, .PCREL_LO12_S,
|
|
.HI20, .LO12_I, .LO12_S, .CALL:
|
|
return false
|
|
}
|
|
write_u16_le(code, relocation.offset, hword)
|
|
return true
|
|
}
|
|
|
|
word := read_u32_le(code, relocation.offset)
|
|
|
|
switch relocation.type {
|
|
case .BRANCH:
|
|
rel := i32(target) - i32(relocation.offset) + relocation.addend
|
|
if rel & 1 != 0 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
if rel < -4096 || rel > 4094 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
word |= scatter_b(u32(rel))
|
|
|
|
case .JAL:
|
|
rel := i32(target) - i32(relocation.offset) + relocation.addend
|
|
if rel & 1 != 0 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
if rel < -(1 << 20) || rel > (1 << 20) - 2 {
|
|
append(errors, Error{inst_idx = u32(relocation.inst_idx), code = .LABEL_OUT_OF_RANGE})
|
|
return true
|
|
}
|
|
word |= scatter_j(u32(rel))
|
|
|
|
case .NONE, .PCREL_HI20, .PCREL_LO12_I, .PCREL_LO12_S,
|
|
.HI20, .LO12_I, .LO12_S, .CALL, .C_BRANCH, .C_JUMP:
|
|
// Not auto-resolved by the encoder pass 2; the assembler caller
|
|
// supplies the raw values via %hi/%lo or expands CALL itself.
|
|
return false
|
|
}
|
|
|
|
write_u32_le(code, relocation.offset, word)
|
|
return true
|
|
}
|
|
|
|
// =============================================================================
|
|
// Scatter / gather helpers for B-type and J-type immediates
|
|
// =============================================================================
|
|
|
|
@(private="package")
|
|
scatter_b :: #force_inline proc "contextless" (v: u32) -> u32 {
|
|
return ((v >> 12) & 1) << 31 |
|
|
((v >> 5) & 0x3F) << 25 |
|
|
((v >> 1) & 0xF) << 8 |
|
|
((v >> 11) & 1) << 7
|
|
}
|
|
|
|
@(private="package")
|
|
scatter_j :: #force_inline proc "contextless" (v: u32) -> u32 {
|
|
return ((v >> 20) & 1) << 31 |
|
|
((v >> 1) & 0x3FF) << 21 |
|
|
((v >> 11) & 1) << 20 |
|
|
((v >> 12) & 0xFF) << 12
|
|
}
|
|
|
|
// Inverse for decoder. Returns sign-extended offset.
|
|
@(private="package")
|
|
gather_b :: #force_inline proc "contextless" (word: u32) -> i32 {
|
|
v := ((word >> 31) & 1) << 12 |
|
|
((word >> 7) & 1) << 11 |
|
|
((word >> 25) & 0x3F) << 5 |
|
|
((word >> 8) & 0xF) << 1
|
|
// sign-extend from bit 12
|
|
if v & (1 << 12) != 0 { v |= ~u32(0x1FFF) }
|
|
return i32(v)
|
|
}
|
|
|
|
@(private="package")
|
|
gather_j :: #force_inline proc "contextless" (word: u32) -> i32 {
|
|
v := ((word >> 31) & 1) << 20 |
|
|
((word >> 12) & 0xFF) << 12 |
|
|
((word >> 20) & 1) << 11 |
|
|
((word >> 21) & 0x3FF) << 1
|
|
if v & (1 << 20) != 0 { v |= ~u32(0x1FFFFF) }
|
|
return i32(v)
|
|
}
|
|
|
|
// I-type sign-extended immediate (bits 31-20)
|
|
@(private="package")
|
|
gather_i :: #force_inline proc "contextless" (word: u32) -> i32 {
|
|
return i32(word) >> 20 // arithmetic shift sign-extends
|
|
}
|
|
|
|
// S-type sign-extended immediate (bits 31-25 || 11-7)
|
|
@(private="package")
|
|
gather_s :: #force_inline proc "contextless" (word: u32) -> i32 {
|
|
v := ((word >> 25) & 0x7F) << 5 | ((word >> 7) & 0x1F)
|
|
if v & (1 << 11) != 0 { v |= ~u32(0xFFF) }
|
|
return i32(v)
|
|
}
|
|
|
|
// ---- C extension scatter/gather --------------------------------------------
|
|
//
|
|
// C.BEQZ / C.BNEZ -- 9-bit signed PC-rel offset, scattered as:
|
|
// imm[8] @ bit 12 imm[4:3] @ bits 11:10
|
|
// imm[7:6] @ bits 6:5 imm[2:1] @ bits 4:3 imm[5] @ bit 2
|
|
@(private="package")
|
|
scatter_c_branch :: #force_inline proc "contextless" (v: u32) -> u32 {
|
|
return ((v >> 8) & 0x1) << 12 |
|
|
((v >> 3) & 0x3) << 10 |
|
|
((v >> 6) & 0x3) << 5 |
|
|
((v >> 1) & 0x3) << 3 |
|
|
((v >> 5) & 0x1) << 2
|
|
}
|
|
|
|
@(private="package")
|
|
gather_c_branch :: #force_inline proc "contextless" (hword: u32) -> i32 {
|
|
v := ((hword >> 12) & 0x1) << 8 |
|
|
((hword >> 10) & 0x3) << 3 |
|
|
((hword >> 5) & 0x3) << 6 |
|
|
((hword >> 3) & 0x3) << 1 |
|
|
((hword >> 2) & 0x1) << 5
|
|
if v & (1 << 8) != 0 { v |= ~u32(0x1FF) }
|
|
return i32(v)
|
|
}
|
|
|
|
// C.J / C.JAL -- 12-bit signed PC-rel offset, scattered as:
|
|
// imm[11] @12, imm[4] @11, imm[9:8] @10:9, imm[10] @8, imm[6] @7,
|
|
// imm[7] @6, imm[3:1] @5:3, imm[5] @2
|
|
@(private="package")
|
|
scatter_c_jump :: #force_inline proc "contextless" (v: u32) -> u32 {
|
|
return ((v >> 11) & 0x1) << 12 |
|
|
((v >> 4) & 0x1) << 11 |
|
|
((v >> 8) & 0x3) << 9 |
|
|
((v >> 10) & 0x1) << 8 |
|
|
((v >> 6) & 0x1) << 7 |
|
|
((v >> 7) & 0x1) << 6 |
|
|
((v >> 1) & 0x7) << 3 |
|
|
((v >> 5) & 0x1) << 2
|
|
}
|
|
|
|
@(private="package")
|
|
gather_c_jump :: #force_inline proc "contextless" (hword: u32) -> i32 {
|
|
v := ((hword >> 12) & 0x1) << 11 |
|
|
((hword >> 11) & 0x1) << 4 |
|
|
((hword >> 9) & 0x3) << 8 |
|
|
((hword >> 8) & 0x1) << 10 |
|
|
((hword >> 7) & 0x1) << 6 |
|
|
((hword >> 6) & 0x1) << 7 |
|
|
((hword >> 3) & 0x7) << 1 |
|
|
((hword >> 2) & 0x1) << 5
|
|
if v & (1 << 11) != 0 { v |= ~u32(0xFFF) }
|
|
return i32(v)
|
|
}
|
|
|
|
// =============================================================================
|
|
// Little-endian word I/O
|
|
// =============================================================================
|
|
|
|
@(private="package")
|
|
write_u32_le :: #force_inline proc "contextless" (code: []u8, offset, word: u32) {
|
|
code[offset+0] = u8(word)
|
|
code[offset+1] = u8(word >> 8)
|
|
code[offset+2] = u8(word >> 16)
|
|
code[offset+3] = u8(word >> 24)
|
|
}
|
|
|
|
@(private="package")
|
|
read_u32_le :: #force_inline proc "contextless" (code: []u8, offset: u32) -> u32 {
|
|
return u32(code[offset+0]) |
|
|
(u32(code[offset+1]) << 8) |
|
|
(u32(code[offset+2]) << 16) |
|
|
(u32(code[offset+3]) << 24)
|
|
}
|
|
|
|
@(private="package")
|
|
write_u16_le :: #force_inline proc "contextless" (code: []u8, offset: u32, word: u16) {
|
|
code[offset+0] = u8(word)
|
|
code[offset+1] = u8(word >> 8)
|
|
}
|
|
|
|
@(private="package")
|
|
read_u16_le :: #force_inline proc "contextless" (code: []u8, offset: u32) -> u16 {
|
|
return u16(code[offset+0]) | (u16(code[offset+1]) << 8)
|
|
}
|