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Register widens to a u32: hw number in bits 0-4, class byte in bits 8-15 -- bit-identical to the old u16 layout -- and, for the new REG_SYS class only, the 15-bit MRS/MSR field in bits 16-30. System_Register, its Operand_Kind, and the union's sysreg member are gone; a system register is now a plain .REGISTER operand distinguished by class, so it flows through matching, packing, and printing like any other register. Memory is untouched: every class legal in an address still lives entirely in the low 16 bits of the u32, so its 16-bit register slots stay lossless and NONE round-trips (verified: Odin bit_fields zero-extend on read and reject overflowing constants at compile time). Operand stays 11 bytes -- the union's largest member is still 8 -- and Instruction stays exactly 64. op_sysreg survives as an op_reg alias so MRS/MSR call sites read as what they are, and the sysreg constants keep their field value in their name: NZCV is now Register(0x5A10_1000) where it was System_Register(0x5A10). New pipeline test: every SYSREG_NAMES entry round-trips encode -> decode -> print byte-exactly, with the expected word derived from the table value. All 330 table + 134 pipeline checks pass; benchmarks show encode ~3% faster, decode and print at parity. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01AFeLCDKi5kRMtHrskUaRfw