vim-patch:d1caa941d876

Update runtime files
d1caa941d8

Cherry-pick error E452 from patch v8.2.0486.
This commit is contained in:
Jan Edmund Lazo
2021-04-27 21:48:38 -04:00
parent d894b3da1e
commit e612a0a76a
14 changed files with 107 additions and 52 deletions

View File

@@ -1,9 +1,9 @@
" Vim syntax file
" Vim reST syntax file
" Language: reStructuredText documentation format
" Maintainer: Marshall Ward <marshall.ward@gmail.com>
" Previous Maintainer: Nikolai Weibull <now@bitwi.se>
" Website: https://github.com/marshallward/vim-restructuredtext
" Latest Revision: 2018-12-29
" Latest Revision: 2020-03-31
if exists("b:current_syntax")
finish
@@ -21,7 +21,7 @@ syn cluster rstCruft contains=rstEmphasis,rstStrongEmphasis,
\ rstInlineInternalTargets,rstFootnoteReference,rstHyperlinkReference
syn region rstLiteralBlock matchgroup=rstDelimiter
\ start='::\_s*\n\ze\z(\s\+\)' skip='^$' end='^\z1\@!'
\ start='\(^\z(\s*\).*\)\@<=::\n\s*\n' skip='^\s*$' end='^\(\z1\s\+\)\@!'
\ contains=@NoSpell
syn region rstQuotedLiteralBlock matchgroup=rstDelimiter
@@ -90,16 +90,28 @@ execute 'syn match rstSubstitutionDefinition contained' .
\ ' /|.*|\_s\+/ nextgroup=@rstDirectives'
function! s:DefineOneInlineMarkup(name, start, middle, end, char_left, char_right)
" Only escape the first char of a multichar delimiter (e.g. \* inside **)
if a:start[0] == '\'
let first = a:start[0:1]
else
let first = a:start[0]
endif
execute 'syn match rstEscape'.a:name.' +\\\\\|\\'.first.'+'.' contained'
execute 'syn region rst' . a:name .
\ ' start=+' . a:char_left . '\zs' . a:start .
\ '\ze[^[:space:]' . a:char_right . a:start[strlen(a:start) - 1] . ']+' .
\ a:middle .
\ ' end=+\S' . a:end . '\ze\%($\|\s\|[''")\]}>/:.,;!?\\-]\)+'
\ ' end=+' . a:end . '\ze\%($\|\s\|[''")\]}>/:.,;!?\\-]\)+' .
\ ' contains=rstEscape' . a:name
execute 'hi def link rstEscape'.a:name.' Special'
endfunction
function! s:DefineInlineMarkup(name, start, middle, end)
let middle = a:middle != "" ?
\ (' skip=+\\\\\|\\' . a:middle . '+') :
\ (' skip=+\\\\\|\\' . a:middle . '\|\s' . a:middle . '+') :
\ ""
call s:DefineOneInlineMarkup(a:name, a:start, middle, a:end, "'", "'")
@@ -161,7 +173,7 @@ syn match rstStandaloneHyperlink contains=@NoSpell
\ "\<\%(\%(\%(https\=\|file\|ftp\|gopher\)://\|\%(mailto\|news\):\)[^[:space:]'\"<>]\+\|www[[:alnum:]_-]*\.[[:alnum:]_-]\+\.[^[:space:]'\"<>]\+\)[[:alnum:]/]"
syn region rstCodeBlock contained matchgroup=rstDirective
\ start=+\%(sourcecode\|code\%(-block\)\=\)::\s\+.*\_s*\n\ze\z(\s\+\)+
\ start=+\%(sourcecode\|code\%(-block\)\=\)::\s*\(\S*\)\?\s*\n\%(\s*:.*:\s*.*\s*\n\)*\n\ze\z(\s\+\)+
\ skip=+^$+
\ end=+^\z1\@!+
\ contains=@NoSpell

View File

@@ -3,7 +3,7 @@
" Maintainer: Daniel Kho <daniel.kho@logik.haus>
" Previous Maintainer: Czo <Olivier.Sirol@lip6.fr>
" Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn>
" Last Changed: 2020 Mar 09 by Daniel Kho
" Last Changed: 2020 Apr 04 by Daniel Kho
" quit when a syntax file was already loaded
if exists("b:current_syntax")
@@ -16,10 +16,10 @@ set cpo&vim
" case is not significant
syn case ignore
" VHDL keywords
syn keyword vhdlStatement access after alias all assert
" VHDL 1076-2019 keywords
syn keyword vhdlStatement access after alias all
syn keyword vhdlStatement architecture array attribute
syn keyword vhdlStatement assume assume_guarantee
syn keyword vhdlStatement assert assume
syn keyword vhdlStatement begin block body buffer bus
syn keyword vhdlStatement case component configuration constant
syn keyword vhdlStatement context cover
@@ -34,20 +34,19 @@ syn keyword vhdlStatement map
syn keyword vhdlStatement new next null
syn keyword vhdlStatement of on open others out
syn keyword vhdlStatement package port postponed procedure process pure
syn keyword vhdlStatement parameter property protected
syn keyword vhdlStatement parameter property protected private
syn keyword vhdlStatement range record register reject report return
syn keyword vhdlStatement release restrict restrict_guarantee
syn keyword vhdlStatement select severity signal shared
syn keyword vhdlStatement subtype
syn keyword vhdlStatement release restrict
syn keyword vhdlStatement select severity signal shared subtype
syn keyword vhdlStatement sequence strong
syn keyword vhdlStatement then to transport type
syn keyword vhdlStatement unaffected units until use
syn keyword vhdlStatement variable
" VHDL-2019 interface
syn keyword vhdlStatement view
syn keyword vhdlStatement vmode vprop vunit
syn keyword vhdlStatement variable view
syn keyword vhdlStatement vpkg vmode vprop vunit
syn keyword vhdlStatement wait when while with
syn keyword vhdlStatement note warning error failure
" VHDL predefined severity levels
syn keyword vhdlAttribute note warning error failure
" Linting of conditionals.
syn match vhdlStatement "\<\(if\|else\)\>"
@@ -265,4 +264,5 @@ let b:current_syntax = "vhdl"
let &cpo = s:cpo_save
unlet s:cpo_save
" vim: ts=8