mirrors/neovim
1
0
Fork 0
mirror of https://github.com/neovim/neovim.git synced 2026-05-03 12:35:00 +00:00
Code Issues Packages Projects Releases Wiki Activity

vim-patch:77cdfd1

Browse Source 
Updated runtime files.

77cdfd1038

Ignore changes to:
* doc/channel.txt, doc/eval.txt: Channel related docs
* doc/options.txt: GUI related docs
* doc/tags: Generated at build time
* doc/todo.txt: Irrelevant for Neovim
This commit is contained in:
James McCoy
2016-06-20 10:37:19 -04:00
parent 1f54d253e1
commit ea18b4a60f
20 changed files with 261 additions and 211 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
runtime/syntax/vhdl.vim
View File

@@ -54,37 +54,37 @@ syn match vhdlError "\<else\s\+if\>"
" Types and type qualifiers
" Predefined standard VHDL types
syn match vhdlType "bit[\']*"
syn match vhdlType "boolean[\']*"
syn match vhdlType "natural[\']*"
syn match vhdlType "positive[\']*"
syn match vhdlType "integer[\']*"
syn match vhdlType "real[\']*"
syn match vhdlType "time[\']*"
syn match vhdlType "\<bit\>\'\="
syn match vhdlType "\<boolean\>\'\="
syn match vhdlType "\<natural\>\'\="
syn match vhdlType "\<positive\>\'\="
syn match vhdlType "\<integer\>\'\="
syn match vhdlType "\<real\>\'\="
syn match vhdlType "\<time\>\'\="
syn match vhdlType "bit_vector[\']*"
syn match vhdlType "boolean_vector[\']*"
syn match vhdlType "integer_vector[\']*"
syn match vhdlType "real_vector[\']*"
syn match vhdlType "time_vector[\']*"
syn match vhdlType "\<bit_vector\>\'\="
syn match vhdlType "\<boolean_vector\>\'\="
syn match vhdlType "\<integer_vector\>\'\="
syn match vhdlType "\<real_vector\>\'\="
syn match vhdlType "\<time_vector\>\'\="
syn match vhdlType "character[\']*"
syn match vhdlType "string[\']*"
syn match vhdlType "\<character\>\'\="
syn match vhdlType "\<string\>\'\="
"syn keyword vhdlType severity_level
syn match vhdlType "line[\']*"
syn match vhdlType "text[\']*"
syn keyword vhdlType line
syn keyword vhdlType text
" Predefined standard IEEE VHDL types
syn match vhdlType "std_ulogic[\']*"
syn match vhdlType "std_logic[\']*"
syn match vhdlType "std_ulogic_vector[\']*"
syn match vhdlType "std_logic_vector[\']*"
syn match vhdlType "unresolved_signed[\']*"
syn match vhdlType "unresolved_unsigned[\']*"
syn match vhdlType "u_signed[\']*"
syn match vhdlType "u_unsigned[\']*"
syn match vhdlType "signed[\']*"
syn match vhdlType "unsigned[\']*"
syn match vhdlType "\<std_ulogic\>\'\="
syn match vhdlType "\<std_logic\>\'\="
syn match vhdlType "\<std_ulogic_vector\>\'\="
syn match vhdlType "\<std_logic_vector\>\'\="
syn match vhdlType "\<unresolved_signed\>\'\="
syn match vhdlType "\<unresolved_unsigned\>\'\="
syn match vhdlType "\<u_signed\>\'\="
syn match vhdlType "\<u_unsigned\>\'\="
syn match vhdlType "\<signed\>\'\="
syn match vhdlType "\<unsigned\>\'\="
" array attributes