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vm fix for bitwise signed ints (#10507)

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* fixes #10482

* add missing file

* bug fix
This commit is contained in:
cooldome
2019-01-31 18:48:39 +00:00
committed by Arne Döring
parent fc99ddc648
commit 1d5437e9d2
2 changed files with 43 additions and 4 deletions
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8
compiler/vmgen.nim
View File

@@ -987,10 +987,10 @@ proc genMagic(c: PCtx; n: PNode; dest: var TDest; m: TMagic) =
c.freeTemp(tmp2)
of mShlI: genBinaryABCnarrowU(c, n, dest, opcShlInt)
of mAshrI: genBinaryABCnarrow(c, n, dest, opcAshrInt)
of mBitandI: genBinaryABCnarrowU(c, n, dest, opcBitandInt)
of mBitorI: genBinaryABCnarrowU(c, n, dest, opcBitorInt)
of mBitxorI: genBinaryABCnarrowU(c, n, dest, opcBitxorInt)
of mAshrI: genBinaryABC(c, n, dest, opcAshrInt)
of mBitandI: genBinaryABC(c, n, dest, opcBitandInt)
of mBitorI: genBinaryABC(c, n, dest, opcBitorInt)
of mBitxorI: genBinaryABC(c, n, dest, opcBitxorInt)
of mAddU: genBinaryABCnarrowU(c, n, dest, opcAddu)
of mSubU: genBinaryABCnarrowU(c, n, dest, opcSubu)
of mMulU: genBinaryABCnarrowU(c, n, dest, opcMulu)

39
tests/vm/tbitops.nim Normal file
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@@ -0,0 +1,39 @@
discard """
output: ""
"""
import strutils
const x = [1'i32, -1, -10, 10, -10, 10, -20, 30, -40, 50, 7 shl 28, -(7 shl 28), 7 shl 28, -(7 shl 28)]
const y = [-1'i32, 1, -10, -10, 10, 10, -20, -30, 40, 50, 1 shl 30, 1 shl 30, -(1 shl 30), -(1 shl 30)]
const res_xor = block:
var tmp: seq[int64]
for i in 0..<x.len:
tmp.add(int64(x[i] xor y[i]))
tmp
const res_and = block:
var tmp: seq[int64]
for i in 0..<x.len:
tmp.add(int64(x[i] and y[i]))
tmp
const res_or = block:
var tmp: seq[int64]
for i in 0..<x.len:
tmp.add(int64(x[i] or y[i]))
tmp
let xx = x
let yy = y
for i in 0..<xx.len:
let z_xor = int64(xx[i] xor yy[i])
let z_and = int64(xx[i] and yy[i])
let z_or = int64(xx[i] or yy[i])
doAssert(z_xor == res_xor[i], $i & ": " & $res_xor[i] & " " & $z_xor)
doAssert(z_and == res_and[i], $i & ": " & $res_and[i] & " " & $z_and)
doAssert(z_or == res_or[i], $i & ": " & $res_or[i] & " " & $z_or)