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fix logical right shift in VM. (#5916)

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Parashurama
2017-06-05 17:25:04 +02:00
committed by Andreas Rumpf
parent 2c5053caef
commit f603e1b268
2 changed files with 19 additions and 1 deletions
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18
compiler/vmgen.nim
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@@ -826,7 +826,23 @@ proc genMagic(c: PCtx; n: PNode; dest: var TDest; m: TMagic) =
of mSubF64: genBinaryABC(c, n, dest, opcSubFloat)
of mMulF64: genBinaryABC(c, n, dest, opcMulFloat)
of mDivF64: genBinaryABC(c, n, dest, opcDivFloat)
of mShrI: genBinaryABCnarrowU(c, n, dest, opcShrInt)
of mShrI:
# the idea here is to narrow type if needed before executing right shift
# inlined modified: genNarrowU(c, n, dest)
let t = skipTypes(n.typ, abstractVar-{tyTypeDesc})
# uint is uint64 in the VM, we we only need to mask the result for
# other unsigned types:
let tmp = c.genx(n.sons[1])
if t.kind in {tyUInt8..tyUInt32, tyInt8..tyInt32}:
c.gABC(n, opcNarrowU, tmp, TRegister(t.size*8))
# inlined modified: genBinaryABC(c, n, dest, opcShrInt)
let tmp2 = c.genx(n.sons[2])
if dest < 0: dest = c.getTemp(n.typ)
c.gABC(n, opcShrInt, dest, tmp, tmp2)
c.freeTemp(tmp)
c.freeTemp(tmp2)
of mShlI: genBinaryABCnarrowU(c, n, dest, opcShlInt)
of mBitandI: genBinaryABCnarrowU(c, n, dest, opcBitandInt)
of mBitorI: genBinaryABCnarrowU(c, n, dest, opcBitorInt)

2
tests/arithm/tshr.nim
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@@ -16,3 +16,5 @@ proc T() =
T()
static:
T()