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rexcode/arm32: stop presetting operand-driven bits in a form's fixed pattern

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The encoder builds a word by ORing packed operand fields onto the form's
`bits`. It can only ever set a bit that way, never clear one -- so any bit
`bits` presets that an operand is supposed to drive is stuck at 1 forever.

72 forms did that, and two families show what it cost:

  * The U bit (23) on the whole A32 load/store family. U selects add vs
    subtract for the displacement, and the encoder derives it from the sign of
    mem.disp -- but every form had it preset, so `ldr r0, [r1, #-4]` silently
    encoded as `[r1, #4]`. Every negative displacement in the family was wrong.
  * The Vn high bit (7) on the NEON lane-indexed forms. That bit is the top of
    the register number, so presetting it meant Vn could only ever name
    d16..d31; d0..d15 were unreachable.

Which bits are operand-driven was decided by llvm-mc rather than by reading
the manual: for each of the 230 bits a form preset outside its mask, take the
form's canonical word with the bit set and cleared and disassemble both. Same
mnemonic, different operands means the bit belongs to an operand (clear it);
a different mnemonic, or an undecodable word, means the bit is genuinely fixed
for that form. The split was not per-bit -- bit 7 is a register bit for
VMUL/VMLA/VFMA but distinguishes VNEG from VABS and VCMPE from VCMP, and bit
23 is the U bit for LDR but the load/store select for VCX3 -- so every form
was classified individually.

Ten test expectations asserted the old values and were corrected; each had the
bug baked in. Verified byte-exact against llvm-mc across the load/store family
including every negative-displacement form, and the 1680/1680 decode sweep and
all other suites are unchanged.

The other half of `bits & ~mask != 0` -- 130 forms where the bit really is
fixed and the MASK is merely too loose -- is deliberately not in this commit.
Widening those masks alone breaks decode: a bit that distinguishes two
mnemonics has to be added to BOTH forms' masks in the same pass, and doing
only the ones that set it made LSL swallow MOVS, CX3 swallow VADDLVA and VABAV
swallow VRMLSLDAVH. That needs each form's true mask derived empirically
(vary the operands, see which bits move) the way specgen does it.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
This commit is contained in:
Brendan Punsky
2026-08-27 02:45:39 -04:00
committed by Flāvius
parent 440bd9df3f
commit 02cce151ca
8 changed files with 406 additions and 406 deletions
Download Patch File Download Diff File Expand all files Collapse all files

144
core/rexcode/isa/arm32/tablegen/encoding_table.odin
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@@ -956,7 +956,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.PLI = {
{.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {cond_in_28=false}, {}},
{.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF450F000, 0xFF70F000, .V7, .A32, {cond_in_28=false}, {}},
// T32 PLI imm12: 0xF990F000
{.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}, {}},
},
@@ -973,13 +973,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// We split into three variants per direction: imm-offset, pre-index, post-index.
.LDR = {
// LDR imm12 offset: P=1 W=0
{.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {}},
{.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {}},
// LDR imm12 pre-index: P=1 W=1
{.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {}},
{.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05300000, 0x0F700000, .BASE, .A32, {}, {}},
// LDR imm12 post-index: P=0 W=0
{.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {}},
{.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {}},
// LDR reg offset: cond 011 P U 0 W 1 Rn Rt shift_imm shift_type 0 Rm
{.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {}},
{.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07100000, 0x0F700010, .BASE, .A32, {}, {}},
// T16 Format 6 LDR PC-relative: 01001 Rd imm8 (LDR Rd, [PC, #imm8 << 2])
{.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_LITERAL, .NONE, .NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}},
// T16 Format 7 LDR reg-offset: 0101 100 Rm Rb Rd
@@ -996,10 +996,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_LITERAL, .NONE, .NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.STR = {
{.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {}},
{.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {}},
{.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {}},
{.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {}},
{.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {}},
{.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {}},
{.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {}},
{.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07000000, 0x0F700010, .BASE, .A32, {}, {}},
// T16 Format 7 STR reg-offset: 0101 000 Rm Rb Rd
{.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}},
// T16 Format 9 STR imm5: 01100 imm5 Rb Rd (offset = imm5 << 2)
@@ -1012,10 +1012,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.LDRB = {
{.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {}},
{.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {}},
{.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {}},
{.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {}},
{.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05500000, 0x0F700000, .BASE, .A32, {}, {}},
{.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05700000, 0x0F700000, .BASE, .A32, {}, {}},
{.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {}},
{.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07500000, 0x0F700010, .BASE, .A32, {}, {}},
// T16 Format 7 LDRB reg-offset: 0101 110 Rm Rb Rd
{.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}},
// T16 Format 9 LDRB imm5: 01111 imm5 Rb Rd
@@ -1025,10 +1025,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.STRB = {
{.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}, {}},
{.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}, {}},
{.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}, {}},
{.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}, {}},
{.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05400000, 0x0F700000, .BASE, .A32, {}, {}},
{.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05600000, 0x0F700000, .BASE, .A32, {}, {}},
{.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {}},
{.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07400000, 0x0F700010, .BASE, .A32, {}, {}},
// T16 Format 7 STRB reg-offset: 0101 010 Rm Rb Rd
{.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}},
// T16 Format 9 STRB imm5: 01110 imm5 Rb Rd
@@ -1042,11 +1042,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// where op2 = 01 (halfword), 10 (signed byte), 11 (signed half / doubleword)
.LDRH = {
// LDRH imm offset (P=1 W=0): cond 000 1 U 1 0 1 Rn Rt imm4H 1011 imm4L
{.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x015000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
// LDRH reg offset: cond 000 1 U 0 0 1 Rn Rt 0000 1011 Rm
{.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}, {}},
{.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x011000B0, 0x0F700FF0, .BASE, .A32, {}, {}},
// T16 Format 7 LDRH reg-offset: 0101 101 Rm Rb Rd
{.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}},
// T16 Format 10 LDRH imm5: 10001 imm5 Rb Rd (offset = imm5 << 1)
@@ -1056,10 +1056,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.STRH = {
{.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}, {}},
{.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x014000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x010000B0, 0x0F700FF0, .BASE, .A32, {}, {}},
// T16 Format 7 STRH reg-offset: 0101 001 Rm Rb Rd
{.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}},
// T16 Format 10 STRH imm5: 10000 imm5 Rb Rd
@@ -1069,10 +1069,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.LDRSB = {
{.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}, {}},
{.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x015000D0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x011000D0, 0x0F700FF0, .BASE, .A32, {}, {}},
// T16 Format 7 LDRSB reg-offset: 0101 011 Rm Rb Rd
{.LDRSB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}},
// T32 LDRSB imm12 / reg
@@ -1080,10 +1080,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.LDRSH = {
{.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}, {}},
{.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x015000F0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {}},
{.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x011000F0, 0x0F700FF0, .BASE, .A32, {}, {}},
// T16 Format 7 LDRSH reg-offset: 0101 111 Rm Rb Rd
{.LDRSH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}},
// T32 LDRSH imm12 / reg
@@ -1092,18 +1092,18 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
},
.LDRD = {
// LDRD imm offset (ARMv5TE+): cond 000 P U 1 W 0 Rn Rt imm4H 1101 imm4L
{.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}, {}},
{.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {}},
// T32 LDRD imm8: high=11101001 X101 Rn low=Rt Rt2 imm8
{.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.STRD = {
{.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}, {}},
{.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {}},
{.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {}},
// T32 STRD imm8: high=11101001 X100 Rn low=Rt Rt2 imm8
{.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
@@ -1389,8 +1389,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// MVE FP vector + scalar
{.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
{.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
{.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}},
},
.VFMS = {
@@ -1403,8 +1403,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
// MVE FP vector
{.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
{.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
},
.VFNMS = {
{.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}},
@@ -1757,8 +1757,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
{.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
// FP .F32 D-form / Q-form (F=1, size=10)
{.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
},
// ---- VMLA / VMLS (integer + F32) ----
.VMLA = {
@@ -1783,8 +1783,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
{.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
// FP .F32 (F=1)
{.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
},
.VMLS = {
{.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}},
@@ -1806,8 +1806,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
{.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
// FP .F32
{.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
},
// ---- VAND / VBIC / VORR / VORN / VEOR (bitwise, no size variants) ----
.VAND = {
@@ -2103,8 +2103,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
// unsigned
{.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
// MVE imm form (imm6 at bits 21:16)
{.VSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}},
},
@@ -2112,8 +2112,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
.VSRA = {
{.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
// MVE (imm6 at bits 21:16)
{.VSRA, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}},
},
@@ -2144,19 +2144,19 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
.VRSHR = {
{.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
// MVE
{.VRSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}},
},
// VSLI / VSRI (shift left/right and insert)
.VSLI = {
{.VSLI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSLI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSLI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800510, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSLI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800550, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
},
.VSRI = {
{.VSRI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSRI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSRI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800410, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VSRI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800450, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
},
// ---- VABS / VNEG / VMVN / VCNT / VCLZ / VCLS (NEON unary) ----
@@ -2549,7 +2549,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// VSHLL.S<sz> Q, D, #imm: 1111 0010 1 D imm6 Vd 1010 0 0 M 1 Vm
// imm6 encodes sh + size: 001sss for sh<8, 01sss for sh<16, 1sss for sh<32
{.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
{.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // U=1
{.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // U=1
// VSHLL by max (#size) variant: 1111 0011 1 D 11 size 10 Vd 0011 0 0 M 0 Vm
{.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
{.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
@@ -2566,12 +2566,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
.VQSHRN = {
// signed: 1111 0010 1 D imm6 Vd 1001 0 0 M 1 Vm; unsigned: U=1
{.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
{.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
{.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
},
.VQRSHRN = {
// 1111 0010 1 D imm6 Vd 1001 0 1 M 1 Vm
{.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
{.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
{.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
},
.VQSHRUN = {
// signed input, unsigned saturating shift right narrow:
@@ -3573,14 +3573,14 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// Unprivileged (translate) post-indexed loads/stores: the post-index form
// with the W bit (21) set. Word/byte use imm12, half/signed use imm8 split.
.LDRT = { {.LDRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {}} },
.LDRBT = { {.LDRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {}} },
.STRT = { {.STRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {}} },
.STRBT = { {.STRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {}} },
.LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {}} },
.STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {}} },
.LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {}} },
.LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {}} },
.LDRT = { {.LDRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {}} },
.LDRBT = { {.LDRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {}} },
.STRT = { {.STRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {}} },
.STRBT = { {.STRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {}} },
.LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {}} },
.STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {}} },
.LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {}} },
.LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {}} },
// NEON rounding shift-right-accumulate (imm); FP reciprocal/rsqrt estimate;
// FP pairwise add; VFP convert-to-integer using the FPSCR rounding mode.

504
core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin
View File

@@ -22,13 +22,23 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .UMAAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}, {.NONE,.NONE} },
{ .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} },
@@ -44,25 +54,15 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} },
@@ -72,12 +72,18 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} },
{ .CRC32B, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
{ .CRC32CB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SMLABB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SMLABT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SMLATB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SMLATT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000D0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000F0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .TST, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} },
@@ -103,8 +109,14 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .SMLALBT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SMLALTB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SMLALTT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .CMP, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true}, {.NONE,.NONE} },
{ .SMC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} },
{ .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {}, {.NONE,.NONE} },
@@ -113,22 +125,22 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .SMULTB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .SMULTT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .CMN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STL, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} },
{ .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} },
{ .STLEX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDA, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} },
{ .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} },
{ .LDAEX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .RRX, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}, {.NONE,.NONE} },
@@ -151,17 +163,11 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .STLB, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} },
{ .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} },
{ .STLEXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDAB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} },
{ .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} },
{ .LDAEXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .STLH, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} },
@@ -169,25 +175,19 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .STLEXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} },
{ .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {}, {.NONE,.NONE} },
{ .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .LDAH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} },
{ .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} },
{ .LDAEXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} },
{ .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} },
{ .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} },
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
@@ -203,8 +203,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
@@ -244,8 +244,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} },
{ .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} },
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} },
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} },
{ .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
@@ -314,8 +314,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
@@ -337,8 +337,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} },
{ .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} },
@@ -387,37 +387,50 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} },
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} },
{ .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
{ .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VQSHL, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VQSHL, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} },
@@ -438,10 +451,10 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} },
@@ -454,24 +467,24 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} },
@@ -506,8 +519,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} },
{ .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} },
{ .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} },
{ .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} },
{ .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} },
{ .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VACLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
@@ -585,8 +598,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} },
{ .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} },
{ .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} },
{ .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} },
{ .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} },
{ .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} },
{ .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} },
{ .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
@@ -599,8 +612,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} },
{ .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} },
{ .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} },
{ .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} },
@@ -641,19 +654,6 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} },
{ .VQSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQRSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {}, {.U16,.NONE} },
{ .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {}, {.U16,.NONE} },
@@ -686,13 +686,13 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} },
{ .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} },
{ .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} },
{ .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} },
{ .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} },
@@ -713,8 +713,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
@@ -723,17 +723,17 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
{ .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} },
{ .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} },
{ .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} },
@@ -741,9 +741,9 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} },
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} },
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} },
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} },
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} },
{ .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} },
{ .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} },
{ .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
@@ -754,16 +754,16 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
@@ -855,6 +855,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
@@ -866,6 +868,13 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF450F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} },
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} },
@@ -881,8 +890,6 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} },
{ .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
@@ -902,28 +909,21 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} },
{ .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} },
{ .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {}, {.NONE,.NONE} },
{ .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} },
{ .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} },
{ .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {}, {.NONE,.NONE} },
{ .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} },
@@ -991,27 +991,27 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
{ .SMLADX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMLSD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMLSDX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07000000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07100000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {}, {.NONE,.NONE} },
{ .SMLALD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMLALDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMLSLD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMLSLDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07400000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SMMUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMMULR, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMMLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMMLAR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMMLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SMMLSR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07500000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .USAD8, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .USADA8, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} },
{ .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD,.BFI_LSB,.BFI_MSB,.NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}, {.NONE,.NONE} },
{ .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} },
{ .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} },
@@ -1693,69 +1693,69 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{
@(rodata)
DECODE_FORM_IDX := [1680]u16{
0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 5,
4, 0, 2, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1,
5, 4, 0, 2, 2, 2, 2, 1, 1, 2, 2, 2, 5, 4, 0, 0,
2, 1, 1, 0, 0, 0, 5, 4, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1,
0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 3, 3, 3,
2, 1, 0, 0, 0, 3, 3, 3, 5, 4, 0, 1, 1, 1, 1, 0,
0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 0, 0,
0, 2, 1, 0, 0, 0, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1,
1, 1, 1, 0, 0, 0, 5, 4, 1, 1, 1, 1, 1, 1, 14, 9,
8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3,
0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3,
0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2,
2, 1, 2, 2, 2, 5, 4, 0, 0, 2, 1, 0, 0, 0, 5, 4,
0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1,
5, 4, 0, 2, 1, 1, 5, 4, 0, 0, 0, 0, 0, 0, 0, 3,
3, 3, 0, 0, 0, 0, 0, 0, 3, 3, 3, 2, 1, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 1, 0, 0, 0, 2,
1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5,
4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14,
8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3,
0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3,
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4,
0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4,
4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4,
2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8,
1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10,
8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4,
5, 9, 5, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2,
1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0,
5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2,
1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0,
7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10,
3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 22, 23, 25, 0, 0,
0, 0, 11, 10, 11, 17, 13, 19, 20, 15, 18, 16, 14, 12, 10, 6,
0, 0, 0, 7, 5, 6, 8, 9, 4, 2, 3, 0, 0, 0, 0, 0,
1, 1, 1, 1, 5, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1,
1, 1, 18, 12, 11, 1, 7, 1, 6, 1, 6, 2, 0, 0, 2, 0,
2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 22, 19, 13,
16, 12, 15, 7, 6, 2, 8, 2, 7, 2, 7, 3, 1, 1, 3, 1,
3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7,
1, 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9,
7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11,
3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4,
3, 3, 3, 6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, 2,
2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1,
10, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11,
13, 11, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 10, 12,
1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0,
15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 0, 0, 1, 1, 1, 3, 3, 3, 1, 1,
2, 2, 2, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20,
0, 0, 11, 10, 11, 17, 13, 19, 20, 15, 16, 14, 18, 12, 10, 6,
0, 0, 0, 3, 5, 9, 7, 4, 6, 2, 8, 1, 0, 1, 0, 0,
0, 0, 1, 1, 3, 1, 3, 3, 1, 1, 1, 1, 5, 2, 0, 0,
2, 0, 2, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18,
12, 11, 1, 7, 1, 6, 1, 6, 2, 0, 2, 0, 2, 0, 4, 4,
4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 22, 19, 13, 16, 12, 15,
7, 6, 2, 8, 2, 7, 7, 2, 1, 3, 3, 1, 1, 3, 6, 6,
5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, 9, 9,
12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, 12, 6,
6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, 3, 6, 6,
8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, 3, 3, 3,
6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4,
11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 13, 1,
13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, 12,
0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1,
11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20,
14, 13, 4, 9, 4, 8, 8, 4, 6, 6, 3, 5, 5, 7, 7, 5,
5, 5, 5, 5, 21, 23, 15, 17, 16, 14, 8, 7, 5, 10, 5, 9,
9, 5, 7, 7, 0, 10, 3, 2, 1, 0, 3, 0, 1, 2, 0, 1,
0, 1, 0, 0, 0, 9, 8, 3, 5, 4, 7, 6, 2, 8, 9, 4,
2, 5, 6, 3, 7, 1, 0, 1, 0, 2, 3, 1, 5, 2, 0, 4,
2, 1, 0, 13, 11, 10, 12, 13, 12, 15, 14, 15, 14, 13, 12, 15,
17, 14, 16, 14, 17, 16, 15, 5, 0, 3, 2, 4, 1, 2, 0, 1,
1, 0, 0, 0, 0, 9, 8, 3, 5, 4, 6, 7, 2, 8, 9, 6,
4, 5, 2, 7, 3, 1, 0, 1, 0, 2, 3, 1, 2, 0, 5, 4,
2, 1, 0, 13, 11, 10, 12, 13, 12, 14, 15, 15, 14, 13, 12, 16,
15, 17, 14, 14, 17, 16, 15, 5, 0, 3, 2, 4, 1, 2, 0, 1,
3, 2, 4, 3, 5, 1, 3, 0, 2, 4, 2, 1, 4, 5, 0, 3,
0, 1, 1, 0, 3, 1, 2, 0, 5, 0, 3, 1, 4, 2, 5, 0,
4, 3, 1, 2, 3, 1, 0, 2, 4, 2, 1, 3, 0, 4, 0, 1,
0, 0, 0, 0, 3, 1, 0, 2, 3, 0, 2, 1, 2, 3, 3, 0,
3, 0, 3, 3, 1, 0, 2, 1, 2, 0, 0, 1, 0, 1, 0, 3,
2, 1, 1, 0, 2, 0, 1, 1, 0, 4, 6, 5, 0, 2, 1, 2,
1, 0, 2, 1, 0, 0, 2, 1, 2, 2, 0, 0, 0, 7, 6, 5,
4, 2, 1, 0, 2, 1, 0, 0, 1, 2, 0, 2, 1, 0, 0, 2,
0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0,
0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3, 0, 3, 3, 1, 0, 2, 1, 2, 0, 0, 1, 0, 1, 2, 2,
0, 3, 2, 1, 1, 0, 2, 0, 1, 1, 0, 0, 0, 2, 0, 2,
0, 0, 4, 6, 5, 0, 2, 1, 2, 1, 0, 2, 1, 0, 0, 2,
1, 0, 0, 0, 7, 6, 5, 4, 2, 1, 0, 2, 1, 0, 0, 1,
2, 0, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 3, 3, 0, 0, 0, 3, 3, 0, 0, 3, 0, 3,
0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 3, 0,
0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 3, 0, 3,
0, 0, 0, 1, 0, 1, 4, 4, 0, 2, 2, 1, 0, 0, 1, 0,
0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 9,
9, 7, 0, 0, 6, 8, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0,
@@ -1803,20 +1803,20 @@ DECODE_FORM_IDX := [1680]u16{
@(rodata)
DECODE_BUCKET_LIST := [5553]u16{
0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7,
11, 8, 12, 35, 36, 37, 13, 14, 41, 42, 43, 15, 13, 16, 14, 17,
47, 18, 19, 51, 52, 53, 20, 21, 18, 19, 22, 23, 24, 25, 22, 26,
23, 27, 24, 28, 29, 30, 31, 28, 32, 33, 29, 30, 34, 35, 36, 37,
38, 39, 40, 34, 41, 42, 43, 44, 38, 45, 39, 46, 47, 48, 49, 50,
46, 51, 52, 53, 54, 48, 55, 49, 56, 57, 58, 59, 60, 61, 62, 109,
110, 111, 63, 64, 65, 66, 67, 68, 117, 118, 119, 69, 70, 71, 72, 73,
74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 57, 85, 86, 87, 88,
89, 90, 91, 92, 93, 142, 143, 144, 94, 95, 150, 151, 152, 96, 97, 98,
74, 99, 100, 101, 102, 103, 160, 161, 162, 104, 105, 168, 169, 170, 106, 107,
108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 112, 113,
122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137,
133, 138, 134, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151,
152, 153, 145, 154, 146, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165,
166, 158, 167, 159, 168, 169, 170, 171, 172, 173, 175, 174, 176, 177, 178, 179,
11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23,
24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36,
37, 33, 34, 38, 39, 40, 41, 38, 42, 43, 39, 40, 44, 13, 14, 15,
45, 46, 47, 44, 18, 19, 20, 48, 49, 45, 46, 50, 24, 51, 52, 53,
50, 27, 28, 29, 54, 51, 55, 52, 56, 57, 58, 59, 60, 61, 62, 63,
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 57, 91, 92, 93, 94,
95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,
80, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125,
126, 63, 64, 65, 127, 128, 129, 130, 131, 72, 73, 74, 132, 127, 133, 128,
134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
150, 145, 146, 151, 152, 153, 100, 101, 102, 154, 155, 156, 157, 158, 105, 106,
107, 159, 160, 154, 155, 161, 162, 163, 164, 165, 116, 117, 118, 166, 167, 168,
169, 170, 164, 165, 121, 122, 123, 171, 172, 173, 175, 174, 176, 177, 178, 179,
180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195,
196, 197, 198, 199, 200, 201, 202, 204, 203, 205, 206, 207, 208, 209, 210, 211,
212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227,
@@ -1839,108 +1839,108 @@ DECODE_BUCKET_LIST := [5553]u16{
298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313,
314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328,
330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345,
346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 362, 361, 363, 365,
364, 366, 367, 368, 369, 370, 371, 379, 380, 373, 375, 381, 377, 378, 382, 374,
376, 372, 384, 383, 385, 386, 391, 388, 394, 392, 389, 390, 387, 393, 395, 632,
396, 633, 397, 398, 399, 634, 635, 400, 401, 636, 637, 402, 403, 638, 639, 404,
405, 640, 406, 641, 642, 407, 408, 643, 644, 409, 410, 411, 412, 413, 414, 415,
416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 430, 429, 432,
431, 433, 434, 435, 436, 395, 632, 396, 633, 397, 398, 634, 399, 400, 635, 401,
636, 637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644,
409, 437, 410, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 450, 449,
451, 452, 453, 454, 456, 455, 458, 457, 459, 460, 462, 461, 464, 463, 465, 466,
467, 468, 395, 632, 396, 633, 397, 398, 399, 634, 635, 400, 636, 401, 637, 402,
403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 469, 395,
632, 396, 633, 397, 398, 634, 399, 400, 635, 401, 636, 402, 637, 403, 638, 639,
404, 640, 405, 406, 641, 407, 642, 408, 643, 644, 409, 470, 471, 472, 469, 358,
346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 362, 361, 365, 363,
364, 366, 367, 368, 369, 370, 371, 373, 372, 376, 379, 375, 377, 381, 374, 380,
382, 378, 383, 384, 385, 386, 389, 387, 390, 393, 391, 388, 394, 392, 395, 396,
398, 397, 399, 400, 402, 401, 404, 403, 405, 406, 407, 408, 409, 410, 411, 412,
413, 414, 416, 415, 418, 417, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428,
429, 430, 431, 432, 433, 434, 435, 437, 436, 438, 439, 440, 441, 443, 442, 445,
444, 446, 447, 448, 449, 396, 395, 397, 398, 399, 400, 401, 402, 404, 403, 405,
406, 407, 408, 409, 410, 411, 412, 414, 413, 415, 416, 417, 418, 419, 420, 421,
422, 450, 423, 451, 452, 453, 454, 455, 456, 457, 458, 459, 461, 460, 463, 462,
464, 465, 466, 467, 469, 468, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479,
480, 481, 396, 395, 398, 397, 399, 400, 402, 401, 403, 404, 405, 406, 407, 408,
409, 410, 411, 412, 413, 414, 416, 415, 418, 417, 419, 420, 421, 422, 482, 396,
395, 397, 398, 399, 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411,
412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 483, 484, 485, 482, 358,
359, 360, 365, 364, 363, 362, 361, 366, 367, 368, 369, 370, 371, 382, 381, 380,
379, 378, 377, 376, 374, 373, 372, 375, 383, 384, 385, 386, 394, 393, 392, 391,
389, 390, 388, 387, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636,
637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, 409,
473, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 422, 421, 424, 423, 426,
425, 428, 427, 429, 430, 432, 431, 433, 434, 435, 436, 395, 632, 396, 633, 397,
398, 634, 399, 400, 635, 636, 401, 637, 402, 403, 638, 639, 404, 640, 405, 641,
406, 407, 642, 408, 643, 644, 409, 474, 473, 438, 439, 440, 441, 442, 443, 444,
445, 446, 447, 448, 449, 450, 451, 452, 454, 453, 455, 456, 458, 457, 459, 460,
462, 461, 463, 464, 465, 466, 467, 468, 395, 632, 396, 633, 397, 398, 634, 399,
400, 635, 636, 401, 637, 402, 403, 638, 639, 404, 640, 405, 406, 641, 407, 642,
408, 643, 644, 409, 475, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 636,
401, 402, 637, 403, 638, 639, 404, 640, 405, 406, 641, 407, 642, 408, 643, 644,
409, 470, 471, 476, 475, 478, 477, 479, 480, 481, 482, 484, 483, 485, 486, 487,
488, 489, 490, 491, 492, 493, 494, 495, 496, 498, 497, 499, 500, 501, 502, 503,
504, 505, 506, 507, 508, 509, 511, 510, 512, 513, 514, 515, 516, 517, 518, 519,
520, 521, 522, 523, 524, 525, 526, 528, 527, 529, 530, 531, 532, 533, 534, 535,
536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551,
552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567,
568, 569, 570, 571, 572, 573, 574, 575, 577, 576, 578, 579, 580, 581, 582, 583,
584, 585, 586, 587, 588, 589, 591, 590, 592, 593, 594, 595, 596, 597, 598, 599,
600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615,
616, 477, 478, 479, 480, 481, 482, 484, 483, 485, 486, 487, 488, 489, 490, 491,
492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507,
508, 509, 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523,
524, 525, 526, 528, 527, 529, 530, 531, 532, 533, 534, 617, 536, 537, 538, 539,
540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555,
556, 557, 558, 559, 560, 561, 618, 575, 576, 577, 578, 579, 580, 581, 582, 583,
584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599,
600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615,
619, 620, 621, 622, 365, 364, 363, 361, 362, 623, 624, 625, 626, 370, 371, 382,
380, 379, 381, 378, 375, 376, 377, 374, 373, 372, 627, 628, 629, 394, 393, 390,
391, 392, 389, 388, 387, 630, 631, 632, 395, 633, 396, 397, 398, 399, 634, 635,
400, 636, 401, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408,
643, 644, 409, 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657,
658, 659, 661, 660, 662, 663, 664, 665, 630, 631, 632, 395, 633, 396, 397, 398,
399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641,
642, 407, 408, 643, 644, 409, 666, 645, 667, 668, 669, 670, 671, 672, 673, 674,
675, 676, 677, 678, 679, 680, 681, 682, 683, 684, 685, 686, 687, 688, 689, 690,
691, 630, 631, 395, 632, 633, 396, 397, 398, 634, 399, 400, 635, 636, 401, 402,
637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 692,
693, 696, 694, 695, 697, 698, 700, 699, 701, 702, 703, 705, 704, 706, 707, 708,
716, 709, 711, 713, 714, 710, 712, 715, 719, 722, 723, 717, 721, 718, 724, 720,
726, 725, 729, 727, 728, 733, 731, 735, 730, 734, 732, 738, 736, 737, 739, 741,
742, 740, 745, 746, 743, 744, 748, 750, 749, 747, 754, 753, 752, 751, 758, 755,
756, 757, 761, 762, 759, 763, 760, 764, 766, 768, 767, 765, 769, 771, 770, 774,
776, 777, 775, 772, 773, 783, 779, 782, 778, 781, 780, 785, 784, 787, 786, 790,
789, 791, 788, 796, 793, 792, 794, 795, 797, 801, 800, 799, 803, 798, 802, 807,
804, 806, 805, 808, 810, 809, 812, 811, 813, 815, 814, 816, 817, 818, 819, 823,
821, 822, 820, 827, 825, 824, 826, 829, 828, 630, 631, 395, 632, 396, 633, 397,
398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406,
641, 407, 642, 408, 643, 644, 409, 830, 692, 620, 621, 622, 365, 364, 363, 361,
362, 623, 624, 625, 626, 371, 370, 382, 380, 379, 378, 376, 375, 374, 372, 373,
377, 381, 627, 628, 629, 394, 392, 393, 391, 390, 387, 388, 389, 630, 631, 395,
632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639,
404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 831, 646, 647, 648, 649,
389, 390, 388, 387, 396, 395, 398, 397, 399, 400, 402, 401, 403, 404, 406, 405,
408, 407, 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422,
486, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 435, 434, 436, 437, 438,
439, 441, 440, 442, 443, 445, 444, 446, 447, 448, 449, 396, 395, 398, 397, 399,
400, 402, 401, 403, 404, 405, 406, 408, 407, 409, 410, 411, 412, 413, 414, 416,
415, 417, 418, 419, 420, 421, 422, 487, 486, 451, 452, 453, 454, 455, 456, 457,
458, 459, 460, 461, 463, 462, 464, 465, 466, 467, 469, 468, 470, 471, 473, 472,
475, 474, 477, 476, 478, 479, 480, 481, 396, 395, 398, 397, 399, 400, 402, 401,
404, 403, 406, 405, 407, 408, 409, 410, 411, 412, 413, 414, 416, 415, 418, 417,
419, 420, 421, 422, 488, 396, 395, 398, 397, 399, 400, 402, 401, 404, 403, 406,
405, 407, 408, 409, 410, 411, 412, 414, 413, 415, 416, 417, 418, 419, 420, 421,
422, 483, 484, 489, 488, 491, 490, 492, 493, 494, 495, 497, 496, 498, 499, 500,
501, 502, 503, 504, 505, 506, 508, 507, 509, 510, 511, 512, 513, 514, 515, 516,
517, 518, 519, 520, 521, 522, 524, 523, 525, 526, 527, 528, 529, 530, 531, 532,
533, 534, 535, 536, 537, 538, 539, 541, 540, 542, 543, 544, 545, 546, 547, 548,
549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564,
565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 580,
581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596,
597, 598, 599, 600, 601, 602, 604, 603, 605, 606, 607, 608, 609, 610, 611, 612,
613, 614, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628,
629, 490, 491, 492, 493, 494, 495, 497, 496, 498, 499, 500, 501, 502, 503, 504,
505, 506, 508, 507, 509, 511, 510, 512, 513, 514, 515, 516, 517, 518, 519, 520,
521, 522, 524, 523, 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536,
537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 630, 549, 550, 551, 552,
553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568,
569, 570, 571, 572, 573, 574, 631, 588, 590, 589, 591, 592, 593, 594, 595, 596,
597, 598, 599, 600, 601, 602, 604, 603, 605, 606, 607, 608, 609, 610, 611, 612,
613, 614, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628,
632, 633, 634, 635, 365, 364, 363, 361, 362, 636, 637, 638, 639, 370, 371, 382,
380, 379, 381, 378, 375, 376, 377, 374, 373, 372, 640, 641, 642, 394, 393, 390,
391, 392, 389, 388, 387, 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 404,
403, 406, 405, 408, 407, 409, 410, 411, 412, 413, 414, 416, 415, 418, 417, 419,
420, 421, 422, 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657,
659, 658, 660, 661, 663, 662, 664, 665, 643, 644, 395, 396, 398, 397, 399, 400,
402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, 412, 414, 413, 416, 415,
418, 417, 419, 420, 421, 422, 666, 645, 667, 668, 669, 670, 671, 672, 673, 674,
675, 677, 676, 678, 679, 680, 681, 682, 683, 684, 685, 687, 686, 688, 689, 690,
691, 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, 405, 408,
407, 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 692,
693, 696, 694, 695, 697, 698, 701, 700, 699, 703, 702, 705, 704, 706, 707, 708,
709, 710, 716, 714, 713, 715, 711, 712, 721, 720, 722, 719, 723, 718, 717, 724,
725, 726, 729, 728, 727, 731, 734, 733, 732, 735, 730, 738, 737, 736, 742, 739,
740, 741, 745, 746, 743, 744, 748, 749, 750, 747, 752, 754, 751, 753, 756, 758,
757, 755, 760, 759, 761, 762, 763, 764, 767, 766, 768, 765, 771, 770, 769, 776,
773, 774, 772, 777, 775, 783, 780, 779, 782, 778, 781, 784, 785, 786, 787, 789,
790, 791, 788, 796, 793, 794, 795, 792, 797, 801, 798, 802, 800, 803, 799, 805,
804, 807, 808, 806, 809, 810, 812, 811, 813, 815, 814, 816, 817, 818, 819, 820,
821, 822, 823, 827, 825, 824, 826, 828, 829, 643, 644, 396, 395, 398, 397, 399,
400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, 412, 414, 413, 416,
415, 417, 418, 419, 420, 421, 422, 830, 692, 633, 634, 635, 365, 364, 363, 361,
362, 636, 637, 638, 639, 371, 370, 382, 380, 379, 378, 376, 375, 374, 372, 373,
377, 381, 640, 641, 642, 394, 392, 393, 391, 390, 387, 388, 389, 643, 644, 396,
395, 398, 397, 399, 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411,
412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 831, 646, 647, 648, 649,
650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 663, 662, 664, 665,
630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637,
403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 832, 831,
643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, 405, 408, 407,
409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 832, 831,
667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 679, 678, 680, 681, 682,
683, 685, 684, 687, 686, 688, 689, 690, 691, 630, 631, 395, 632, 396, 633, 397,
398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406,
641, 407, 642, 408, 643, 644, 409, 833, 693, 695, 696, 697, 694, 701, 700, 698,
683, 685, 684, 687, 686, 688, 689, 690, 691, 643, 644, 396, 395, 398, 397, 399,
400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, 412, 414, 413, 416,
415, 418, 417, 419, 420, 421, 422, 833, 693, 695, 696, 697, 694, 701, 700, 698,
699, 703, 702, 704, 705, 706, 707, 708, 716, 713, 714, 712, 711, 709, 710, 715,
724, 722, 721, 719, 717, 718, 720, 723, 726, 725, 729, 727, 728, 733, 734, 735,
731, 732, 730, 737, 738, 736, 742, 740, 739, 741, 746, 745, 743, 744, 750, 747,
748, 749, 754, 752, 753, 751, 758, 755, 756, 757, 762, 763, 764, 760, 761, 759,
768, 765, 766, 767, 770, 769, 771, 777, 776, 774, 772, 773, 775, 781, 782, 780,
779, 778, 783, 785, 784, 786, 787, 788, 789, 790, 791, 796, 797, 794, 795, 793,
792, 799, 800, 801, 802, 803, 798, 805, 806, 804, 808, 807, 813, 811, 810, 812,
809, 814, 815, 816, 817, 818, 819, 822, 821, 820, 823, 825, 824, 826, 827, 828,
829, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402,
637, 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, 409, 834,
833, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845, 872, 873, 846, 847,
849, 848, 851, 850, 852, 854, 853, 855, 856, 893, 894, 895, 896, 897, 898, 899,
858, 857, 859, 860, 862, 861, 864, 863, 865, 868, 867, 866, 869, 871, 870, 872,
873, 874, 875, 876, 878, 880, 879, 877, 883, 882, 881, 886, 884, 885, 887, 888,
889, 892, 890, 891, 893, 894, 858, 857, 859, 860, 861, 862, 865, 863, 864, 868,
866, 867, 870, 871, 869, 895, 896, 897, 874, 875, 876, 879, 878, 877, 880, 883,
882, 881, 886, 884, 885, 888, 889, 887, 890, 891, 892, 898, 899, 905, 906, 907,
908, 909, 912, 913, 900, 901, 902, 903, 904, 914, 905, 906, 907, 908, 909, 910,
911, 912, 913, 914, 915, 916, 917, 918, 919, 920, 921, 922, 923, 924, 925, 926,
792, 799, 800, 801, 802, 803, 798, 804, 805, 806, 808, 807, 811, 813, 812, 810,
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407, 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 834,
833, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845, 846, 847, 851, 848,
850, 849, 854, 853, 852, 855, 856, 857, 858, 859, 860, 861, 862, 863, 864, 865,
866, 868, 867, 871, 870, 869, 874, 872, 873, 875, 876, 877, 879, 880, 878, 846,
847, 881, 882, 883, 884, 885, 886, 887, 890, 889, 888, 891, 892, 893, 896, 894,
895, 899, 898, 897, 859, 860, 868, 866, 867, 870, 871, 869, 872, 873, 874, 876,
875, 877, 879, 878, 880, 861, 862, 863, 881, 882, 883, 884, 885, 887, 886, 890,
888, 889, 891, 892, 893, 896, 894, 895, 898, 897, 899, 864, 865, 900, 901, 902,
903, 904, 905, 906, 907, 908, 909, 910, 911, 912, 900, 901, 902, 903, 904, 913,
914, 905, 906, 912, 915, 916, 917, 918, 919, 920, 921, 922, 923, 924, 925, 926,
927, 928, 929, 930, 931, 932, 933, 934, 935, 936, 937, 938, 939, 940, 941, 942,
943, 944, 945, 946, 947, 948, 949, 950, 951, 952, 953, 954, 955, 956, 957, 958,
959, 960, 961, 962, 963, 959, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973,
969, 974, 975, 976, 977, 978, 979, 980, 981, 996, 982, 997, 983, 984, 985, 986,
987, 1001, 988, 989, 990, 991, 992, 993, 1002, 994, 995, 996, 997, 998, 998, 999,
1000, 1001, 999, 1000, 1002, 1003, 1004, 1003, 1005, 1006, 1007, 1005, 1006, 1007, 1008, 1006,
969, 974, 975, 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988,
989, 990, 991, 992, 993, 994, 995, 996, 997, 998, 999, 982, 984, 1000, 1000, 1001,
1002, 990, 1001, 1002, 997, 1003, 1004, 1003, 1005, 1006, 1007, 1005, 1006, 1007, 1008, 1006,
1008, 1006, 1009, 1011, 1006, 1010, 1013, 1011, 1009, 1006, 1012, 1013, 1010, 1008, 1006, 1008,
1006, 1014, 1006, 1015, 1016, 1014, 1006, 1015, 1008, 1006, 1008, 1006, 1017, 1006, 1018, 1017,
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144
core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin
View File

@@ -600,7 +600,7 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {}, {.NONE,.NONE} },
{ .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true}, {.NONE,.NONE} },
// .PLI
{ .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} },
{ .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF450F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} },
{ .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true}, {.NONE,.NONE} },
// .HLT
{ .HLT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {}, {.NONE,.NONE} },
@@ -645,10 +645,10 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .LDR
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07100000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_LITERAL,.NONE,.NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
@@ -657,95 +657,95 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_LITERAL,.NONE,.NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .STR
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07000000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .LDRB
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07500000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .STRB
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07400000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8800000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8000000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .LDRH
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00008800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .STRH
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
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{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8A00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .LDRSB
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000D0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF9900000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .LDRSH
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
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{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000F0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF9B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF9300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .LDRD
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .STRD
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .LDRT
{ .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
// .STRT
{ .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
// .LDRBT
{ .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
// .STRBT
{ .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
// .LDRHT
{ .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
// .STRHT
{ .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
// .LDRSBT
{ .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
// .LDRSHT
{ .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} },
// .LDA
{ .LDA, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} },
// .STL
@@ -933,8 +933,8 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
// .VDIV
{ .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} },
{ .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} },
@@ -956,8 +956,8 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
// .VMLS
{ .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} },
{ .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} },
@@ -974,8 +974,8 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} },
{ .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} },
// .VNMUL
{ .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} },
{ .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} },
@@ -993,8 +993,8 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
{ .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
{ .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} },
// .VFMS
{ .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} },
@@ -1003,8 +1003,8 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
{ .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
// .VFNMA
{ .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} },
{ .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} },
@@ -1644,14 +1644,14 @@ ENCODE_FORMS := [1680]lib.Encoding{
// .VSHR
{ .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} },
// .VSRA
{ .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRA, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} },
// .VRSHL
{ .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
@@ -1662,18 +1662,18 @@ ENCODE_FORMS := [1680]lib.Encoding{
// .VRSHR
{ .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} },
// .VRSRA
{ .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VRSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
// .VSLI
{ .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
// .VSRI
{ .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} },
// .VQSHL
{ .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} },
{ .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
@@ -1684,7 +1684,7 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} },
// .VQSHRN
{ .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
// .VQSHRUN
{ .VQSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} },
// .VQRSHL
@@ -1706,7 +1706,7 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {}, {.U64,.NONE} },
// .VQRSHRN
{ .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
// .VQRSHRUN
{ .VQRSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} },
// .VSHRN
@@ -1715,7 +1715,7 @@ ENCODE_FORMS := [1680]lib.Encoding{
{ .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
// .VSHLL
{ .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} },
{ .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} },
{ .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} },

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core/rexcode/isa/arm32/tables/arm32.bucket_list.bin
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core/rexcode/isa/arm32/tables/arm32.encode_forms.bin
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core/rexcode/isa/arm32/tables/arm32.entries.bin
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core/rexcode/isa/arm32/tables/arm32.form_idx.bin
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20
core/rexcode/isa/arm32/tests/smoke.odin
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@@ -94,14 +94,14 @@ run_smoke :: proc() {
check("CLREX (A32)", .CLREX, 0, 0xF57FF01F, 0xFFFFFFFF)
// ---- Load/Store ----
check("LDR imm", .LDR, 0, 0x05900000, 0x0F700000)
check("LDR pre", .LDR, 1, 0x05B00000, 0x0F700000)
check("LDR post", .LDR, 2, 0x04900000, 0x0F700000)
check("STR imm", .STR, 0, 0x05800000, 0x0F700000)
check("LDRB imm", .LDRB, 0, 0x05D00000, 0x0F700000)
check("STRH imm", .STRH, 0, 0x01C000B0, 0x0F7000F0)
check("LDRSB imm", .LDRSB, 0, 0x01D000D0, 0x0F7000F0)
check("LDRD", .LDRD, 0, 0x01C000D0, 0x0F7000F0)
check("LDR imm", .LDR, 0, 0x05100000, 0x0F700000)
check("LDR pre", .LDR, 1, 0x05300000, 0x0F700000)
check("LDR post", .LDR, 2, 0x04100000, 0x0F700000)
check("STR imm", .STR, 0, 0x05000000, 0x0F700000)
check("LDRB imm", .LDRB, 0, 0x05500000, 0x0F700000)
check("STRH imm", .STRH, 0, 0x014000B0, 0x0F7000F0)
check("LDRSB imm", .LDRSB, 0, 0x015000D0, 0x0F7000F0)
check("LDRD", .LDRD, 0, 0x014000D0, 0x0F7000F0)
check("LDM", .LDM, 0, 0x08900000, 0x0FD00000)
check("STM DB", .STM, 4, 0x09000000, 0x0FD00000)
check("PUSH", .PUSH, 0, 0x092D0000, 0x0FFF0000)
@@ -513,8 +513,8 @@ run_smoke :: proc() {
check("VQDMULL lane .S16",.VQDMULL, 2, 0xF2900B40, 0xFFB00F50)
check("VQDMLAL lane .S32",.VQDMLAL, 3, 0xF2A00340, 0xFFB00F50)
check("VQDMLSL lane", .VQDMLSL, 2, 0xF2900740, 0xFFB00F50)
check("VFMA lane D", .VFMA, 7, 0xF2A000C0, 0xFFB00F50)
check("VFMS lane Q", .VFMS, 7, 0xF3A004C0, 0xFFB00F50)
check("VFMA lane D", .VFMA, 7, 0xF2A00040, 0xFFB00F50)
check("VFMS lane Q", .VFMS, 7, 0xF3A00440, 0xFFB00F50)
check("VQRDMLAH lane", .VQRDMLAH, 4, 0xF2900E40, 0xFFB00F50)
check("VQRDMLSH lane", .VQRDMLSH, 4, 0xF2900F40, 0xFFB00F50)
check("VCMLA lane D", .VCMLA, 2, 0xFE000800, 0xFFB00F10)