Merge pull request #5940 from connnnal/d3d12-tight-alignment

Update d3d12 bindings for D3D12_FEATURE_D3D12_TIGHT_ALIGNMENT

vendor/directx/d3d12/d3d12.odin

@@ -850,6 +850,15 @@ FEATURE :: enum i32 {
 	OPTIONS17                             = 46,
 	OPTIONS18                             = 47,
 	OPTIONS19                             = 48,
+	OPTIONS20                             = 49,
+	PREDICATION                           = 50,
+	PLACED_RESOURCE_SUPPORT_INFO	      = 51,
+	HARDWARE_COPY	                      = 52,
+	OPTIONS21	                          = 53,
+	TIGHT_ALIGNMENT	                      = 54,
+	APPLICATION_SPECIFIC_DRIVER_STATE	  = 56,
+	BYTECODE_BYPASS_HASH_SUPPORTED	      = 57,
+	SHADER_CACHE_ABI_SUPPORT	          = 61,
 }
 
 SHADER_MIN_PRECISION_SUPPORT :: distinct bit_set[SHADER_MIN_PRECISION_SUPPORT_FLAG; u32]
@@ -962,6 +971,11 @@ VIEW_INSTANCING_TIER :: enum i32 {
 	_3            = 3,
 }
 
+WORK_GRAPHS_TIER :: enum i32 {
+	NOT_SUPPORTED = 0,
+	_1_0          = 10,
+}
+
 FEATURE_DATA_OPTIONS :: struct {
 	DoublePrecisionFloatShaderOps:                                              BOOL,
 	OutputMergerLogicOp:                                                        BOOL,
@@ -1276,6 +1290,53 @@ FEATURE_DATA_OPTIONS19 :: struct {
 	ComputeOnlyCustomHeapSupported:                 BOOL,
 }
 
+RECREATE_AT_TIER :: enum i32 {
+	NOT_SUPPORTED = 0,
+	_1            = 1,
+}
+
+FEATURE_DATA_OPTIONS20 :: struct {
+	ComputeOnlyWriteWatchSupported: BOOL,
+	RecreateAtTier:                 RECREATE_AT_TIER,
+}
+
+EXECUTE_INDIRECT_TIER :: enum i32 {
+	_1_0 = 10,
+	_1_1 = 11,
+}
+
+FEATURE_DATA_OPTIONS21 :: struct {
+	WorkGraphsTier:                    WORK_GRAPHS_TIER,
+	ExecuteIndirectTier:               EXECUTE_INDIRECT_TIER,
+	SampleCmpGradientAndBiasSupported: BOOL,
+	ExtendedCommandInfoSupported:      BOOL,
+}
+
+TIGHT_ALIGNMENT_TIER :: enum i32 {
+	NOT_SUPPORTED = 0,
+	_1            = NOT_SUPPORTED + 1,
+}
+
+FEATURE_DATA_TIGHT_ALIGNMENT :: struct {
+	SupportTier: TIGHT_ALIGNMENT_TIER,
+}
+
+FEATURE_DATA_PREDICATION :: struct {
+	Supported: BOOL,
+}
+
+FEATURE_DATA_HARDWARE_COPY :: struct {
+	Supported: BOOL,
+}
+
+FEATURE_DATA_APPLICATION_SPECIFIC_DRIVER_STATE :: struct {
+	Supported: BOOL,
+}
+
+FEATURE_DATA_BYTECODE_BYPASS_HASH_SUPPORTED :: struct {
+	Supported: BOOL,
+}
+
 WAVE_MMA_INPUT_DATATYPE :: enum i32 {
 	INVALID = 0,
 	BYTE    = 1,
@@ -1391,14 +1452,16 @@ TEXTURE_LAYOUT :: enum i32 {
 
 RESOURCE_FLAGS :: distinct bit_set[RESOURCE_FLAG; u32]
 RESOURCE_FLAG :: enum u32 {
-	ALLOW_RENDER_TARGET         = 0,
-	ALLOW_DEPTH_STENCIL         = 1,
-	ALLOW_UNORDERED_ACCESS      = 2,
-	DENY_SHADER_RESOURCE        = 3,
-	ALLOW_CROSS_ADAPTER         = 4,
-	ALLOW_SIMULTANEOUS_ACCESS   = 5,
-	VIDEO_DECODE_REFERENCE_ONLY = 6,
-	VIDEO_ENCODE_REFERENCE_ONLY = 7,
+	ALLOW_RENDER_TARGET               = 0,
+	ALLOW_DEPTH_STENCIL               = 1,
+	ALLOW_UNORDERED_ACCESS            = 2,
+	DENY_SHADER_RESOURCE              = 3,
+	ALLOW_CROSS_ADAPTER               = 4,
+	ALLOW_SIMULTANEOUS_ACCESS         = 5,
+	VIDEO_DECODE_REFERENCE_ONLY       = 6,
+	VIDEO_ENCODE_REFERENCE_ONLY       = 7,
+	RAYTRACING_ACCELERATION_STRUCTURE = 8,
+	USE_TIGHT_ALIGNMENT               = 10,
 }
 
 MIP_REGION :: struct {
@@ -3266,7 +3329,8 @@ SERIALIZED_DATA_DRIVER_MATCHING_IDENTIFIER :: struct {
 }
 
 SERIALIZED_DATA_TYPE :: enum i32 {
-	SERIALIZED_DATA_RAYTRACING_ACCELERATION_STRUCTURE = 0,
+	RAYTRACING_ACCELERATION_STRUCTURE = 0,
+	APPLICATION_SPECIFIC_DRIVER_STATE = 1,
 }
 
 DRIVER_MATCHING_IDENTIFIER_STATUS :: enum i32 {

vendor/directx/d3d12/d3d12_constants.odin

@@ -461,6 +461,9 @@ TEXEL_ADDRESS_RANGE_BIT_COUNT :: 16
 TEXTURE_DATA_PITCH_ALIGNMENT :: 256
 TEXTURE_DATA_PLACEMENT_ALIGNMENT :: 512
 
+TIGHT_ALIGNMENT_MIN_COMMITTED_RESOURCE_ALIGNMENT :: 4096
+TIGHT_ALIGNMENT_MIN_PLACED_RESOURCE_ALIGNMENT :: 8
+
 TILED_RESOURCE_TILE_SIZE_IN_BYTES :: 65536
 
 TRACKED_WORKLOAD_MAX_INSTANCES :: 32