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Update the binary tables

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This commit is contained in:
gingerBill
2026-06-15 23:02:19 +01:00
parent 29594d1ed4
commit 0e90e5babf
7 changed files with 159 additions and 159 deletions
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4
core/rexcode/x86/encoding_types.odin
View File

@@ -259,10 +259,10 @@ Encoding_Flags :: bit_field u32 {
modrm_reg_ext: bool | 1, // ModR/M reg field is opcode extension (use ext field)
mode_32_only: bool | 1, // only valid in Mode._32 (e.g. short-form INC/DEC at 0x40-0x4F)
explicit_count: u8 | 2, // 0..<4 non-implicit operands
explicit_count: u8 | 3, // 0..<4 non-implicit operands
has_implicit: bool | 1, // any implicit operand
op_count: u8 | 2, // total operands including implicit (0..<4)
op_count: u8 | 3, // total operands including implicit (0..<4)
needs_modrm: bool | 1, // any enc is .MR/.REG/.VVVV
}

8
core/rexcode/x86/tablegen/gen.odin
View File

@@ -385,11 +385,11 @@ write_flags :: proc(sb: ^strings.Builder, enc: union{lib.Encoding, Collected_Ent
switch e in enc {
case lib.Encoding:
encoding_operand_count: u8 = 0
has_implict := false
has_implicit := false
for op_type in e.ops {
if op_type == .NONE { break }
if lib.is_implicit_op_inline(op_type) {
has_implict = true
has_implicit = true
} else {
encoding_operand_count += 1
}
@@ -397,8 +397,8 @@ write_flags :: proc(sb: ^strings.Builder, enc: union{lib.Encoding, Collected_Ent
if encoding_operand_count > 0 {
append(&parts, fmt.tprintf("explicit_count=%d", encoding_operand_count))
}
if has_implict {
append(&parts, "has_implict=true")
if has_implicit {
append(&parts, "has_implicit=true")
}
case Collected_Entry:

306
core/rexcode/x86/tablegen/generated/encode_tables.odin
View File

@@ -26,14 +26,14 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true, explicit_count=2}},
{.MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true, explicit_count=2}},
{.MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}},
{.MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implict=true}},
{.MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}},
{.MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}},
{.MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implict=true}},
{.MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}},
{.MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}},
{.MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implicit=true}},
{.MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implicit=true}},
{.MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implicit=true}},
{.MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implicit=true}},
{.MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implicit=true}},
{.MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implicit=true}},
{.MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {explicit_count=2}},
{.MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {force_rex_w=true, explicit_count=2}},
{.MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {explicit_count=2}},
@@ -44,14 +44,14 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.MOV, {.DR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F, explicit_count=2}},
// .MOVABS
{.MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true, explicit_count=2}},
{.MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implict=true}},
{.MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}},
{.MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}},
{.MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implict=true}},
{.MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}},
{.MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}},
{.MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implicit=true}},
{.MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implicit=true}},
{.MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implicit=true}},
{.MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implicit=true}},
{.MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implicit=true}},
{.MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implicit=true}},
{.MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
// .MOVZX
{.MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, explicit_count=2}},
{.MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, explicit_count=2}},
@@ -67,9 +67,9 @@ ENCODE_FORMS := [2355]lib.Encoding{
// .MOVSXD
{.MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {force_rex_w=true, explicit_count=2}},
// .XCHG
{.XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implict=true}},
{.XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implict=true}},
{.XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implicit=true}},
{.XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implicit=true}},
{.XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x86, 0, {lock_ok=true, explicit_count=2}},
{.XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true, explicit_count=2}},
{.XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true, explicit_count=2}},
@@ -104,10 +104,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {explicit_count=2}},
{.ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {explicit_count=2}},
{.ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {force_rex_w=true, explicit_count=2}},
{.ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x04, 0, {explicit_count=1, has_implict=true}},
{.ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implict=true}},
{.ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implict=true}},
{.ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x04, 0, {explicit_count=1, has_implicit=true}},
{.ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implicit=true}},
{.ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implicit=true}},
{.ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
@@ -124,10 +124,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {explicit_count=2}},
{.ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {explicit_count=2}},
{.ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {force_rex_w=true, explicit_count=2}},
{.ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x14, 0, {explicit_count=1, has_implict=true}},
{.ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implict=true}},
{.ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implict=true}},
{.ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x14, 0, {explicit_count=1, has_implicit=true}},
{.ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implicit=true}},
{.ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implicit=true}},
{.ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
@@ -144,10 +144,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {explicit_count=2}},
{.SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {explicit_count=2}},
{.SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {force_rex_w=true, explicit_count=2}},
{.SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x2C, 0, {explicit_count=1, has_implict=true}},
{.SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implict=true}},
{.SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implict=true}},
{.SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x2C, 0, {explicit_count=1, has_implicit=true}},
{.SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implicit=true}},
{.SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implicit=true}},
{.SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.SUB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
@@ -164,10 +164,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {explicit_count=2}},
{.SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {explicit_count=2}},
{.SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {force_rex_w=true, explicit_count=2}},
{.SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x1C, 0, {explicit_count=1, has_implict=true}},
{.SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implict=true}},
{.SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implict=true}},
{.SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x1C, 0, {explicit_count=1, has_implicit=true}},
{.SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implicit=true}},
{.SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implicit=true}},
{.SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.SBB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
@@ -232,10 +232,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {explicit_count=2}},
{.CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {explicit_count=2}},
{.CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {force_rex_w=true, explicit_count=2}},
{.CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x3C, 0, {explicit_count=1, has_implict=true}},
{.CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implict=true}},
{.CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implict=true}},
{.CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x3C, 0, {explicit_count=1, has_implicit=true}},
{.CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implicit=true}},
{.CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implicit=true}},
{.CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 7, {modrm_reg_ext=true, explicit_count=2}},
{.CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true, explicit_count=2}},
{.CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true, explicit_count=2}},
@@ -252,10 +252,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {explicit_count=2}},
{.AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {explicit_count=2}},
{.AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {force_rex_w=true, explicit_count=2}},
{.AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x24, 0, {explicit_count=1, has_implict=true}},
{.AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implict=true}},
{.AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implict=true}},
{.AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x24, 0, {explicit_count=1, has_implicit=true}},
{.AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implicit=true}},
{.AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implicit=true}},
{.AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.AND, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
@@ -272,10 +272,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {explicit_count=2}},
{.OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {explicit_count=2}},
{.OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {force_rex_w=true, explicit_count=2}},
{.OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x0C, 0, {explicit_count=1, has_implict=true}},
{.OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implict=true}},
{.OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implict=true}},
{.OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x0C, 0, {explicit_count=1, has_implicit=true}},
{.OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implicit=true}},
{.OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implicit=true}},
{.OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
@@ -292,10 +292,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {explicit_count=2}},
{.XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {explicit_count=2}},
{.XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {force_rex_w=true, explicit_count=2}},
{.XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x34, 0, {explicit_count=1, has_implict=true}},
{.XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implict=true}},
{.XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implict=true}},
{.XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x34, 0, {explicit_count=1, has_implicit=true}},
{.XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implicit=true}},
{.XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implicit=true}},
{.XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
{.XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}},
@@ -313,119 +313,119 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {explicit_count=2}},
{.TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {explicit_count=2}},
{.TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {force_rex_w=true, explicit_count=2}},
{.TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0xA8, 0, {explicit_count=1, has_implict=true}},
{.TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implict=true}},
{.TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implict=true}},
{.TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {force_rex_w=true, explicit_count=1, has_implict=true}},
{.TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0xA8, 0, {explicit_count=1, has_implicit=true}},
{.TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implicit=true}},
{.TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implicit=true}},
{.TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}},
{.TEST, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xF6, 0, {modrm_reg_ext=true, explicit_count=2}},
{.TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true, explicit_count=2}},
{.TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true, explicit_count=2}},
{.TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}},
// .SHL
{.SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 4, {modrm_reg_ext=true, explicit_count=2}},
{.SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true, explicit_count=2}},
{.SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true, explicit_count=2}},
{.SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}},
// .SHR
{.SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 5, {modrm_reg_ext=true, explicit_count=2}},
{.SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true, explicit_count=2}},
{.SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true, explicit_count=2}},
{.SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}},
// .SAR
{.SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 7, {modrm_reg_ext=true, explicit_count=2}},
{.SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true, explicit_count=2}},
{.SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true, explicit_count=2}},
{.SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}},
// .ROL
{.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 0, {modrm_reg_ext=true, explicit_count=2}},
{.ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true, explicit_count=2}},
{.ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true, explicit_count=2}},
{.ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}},
// .ROR
{.ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 1, {modrm_reg_ext=true, explicit_count=2}},
{.ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true, explicit_count=2}},
{.ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true, explicit_count=2}},
{.ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}},
// .RCL
{.RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 2, {modrm_reg_ext=true, explicit_count=2}},
{.RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true, explicit_count=2}},
{.RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true, explicit_count=2}},
{.RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}},
// .RCR
{.RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 3, {modrm_reg_ext=true, explicit_count=2}},
{.RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true, explicit_count=2}},
{.RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true, explicit_count=2}},
{.RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}},
{.RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}},
{.RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}},
// .SHLD
{.SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, explicit_count=3}},
{.SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, explicit_count=3}},
{.SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, force_rex_w=true, explicit_count=3}},
{.SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implict=true}},
{.SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implict=true}},
{.SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implict=true}},
{.SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implicit=true}},
{.SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implicit=true}},
{.SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implicit=true}},
// .SHRD
{.SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, explicit_count=3}},
{.SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, explicit_count=3}},
{.SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, force_rex_w=true, explicit_count=3}},
{.SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implict=true}},
{.SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implict=true}},
{.SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implict=true}},
{.SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implicit=true}},
{.SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implicit=true}},
{.SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implicit=true}},
// .BT
{.BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, explicit_count=2}},
{.BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, explicit_count=2}},
@@ -1378,13 +1378,13 @@ ENCODE_FORMS := [2355]lib.Encoding{
// .BLENDPD
{.BLENDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0D, 0, {esc=._0F3A, prefix=1, explicit_count=3}},
// .BLENDVPS
{.BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implict=true}},
{.BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implicit=true}},
// .BLENDVPD
{.BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implict=true}},
{.BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implicit=true}},
// .PBLENDW
{.PBLENDW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0E, 0, {esc=._0F3A, prefix=1, explicit_count=3}},
// .PBLENDVB
{.PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implict=true}},
{.PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implicit=true}},
// .DPPS
{.DPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x40, 0, {esc=._0F3A, prefix=1, explicit_count=3}},
// .DPPD
@@ -1510,7 +1510,7 @@ ENCODE_FORMS := [2355]lib.Encoding{
// .SHA256MSG2
{.SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCD, 0, {esc=._0F38, explicit_count=2}},
// .SHA256RNDS2
{.SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0xCB, 0, {esc=._0F38, explicit_count=2, has_implict=true}},
{.SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0xCB, 0, {esc=._0F38, explicit_count=2, has_implicit=true}},
// .VADDPS
{.VADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}},
{.VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}},
@@ -3080,10 +3080,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
// .FADD
{.FADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 0, {explicit_count=1}},
{.FADD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 0, {explicit_count=1}},
{.FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 192, {explicit_count=1, has_implict=true}},
{.FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 192, {explicit_count=1, has_implict=true}},
{.FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 192, {explicit_count=1, has_implicit=true}},
{.FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 192, {explicit_count=1, has_implicit=true}},
// .FADDP
{.FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 192, {explicit_count=1, has_implict=true}},
{.FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 192, {explicit_count=1, has_implicit=true}},
{.FADDP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 193, {}},
// .FIADD
{.FIADD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 0, {explicit_count=1}},
@@ -3091,10 +3091,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
// .FSUB
{.FSUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 4, {modrm_reg_ext=true, explicit_count=1}},
{.FSUB, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 4, {modrm_reg_ext=true, explicit_count=1}},
{.FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 224, {explicit_count=1, has_implict=true}},
{.FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 232, {explicit_count=1, has_implict=true}},
{.FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 224, {explicit_count=1, has_implicit=true}},
{.FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 232, {explicit_count=1, has_implicit=true}},
// .FSUBP
{.FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 232, {explicit_count=1, has_implict=true}},
{.FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 232, {explicit_count=1, has_implicit=true}},
{.FSUBP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 233, {}},
// .FISUB
{.FISUB, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 4, {modrm_reg_ext=true, explicit_count=1}},
@@ -3102,10 +3102,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
// .FSUBR
{.FSUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 5, {modrm_reg_ext=true, explicit_count=1}},
{.FSUBR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 5, {modrm_reg_ext=true, explicit_count=1}},
{.FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 232, {explicit_count=1, has_implict=true}},
{.FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 224, {explicit_count=1, has_implict=true}},
{.FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 232, {explicit_count=1, has_implicit=true}},
{.FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 224, {explicit_count=1, has_implicit=true}},
// .FSUBRP
{.FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 224, {explicit_count=1, has_implict=true}},
{.FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 224, {explicit_count=1, has_implicit=true}},
{.FSUBRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 225, {}},
// .FISUBR
{.FISUBR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 5, {modrm_reg_ext=true, explicit_count=1}},
@@ -3113,10 +3113,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
// .FMUL
{.FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 1, {modrm_reg_ext=true, explicit_count=1}},
{.FMUL, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 1, {modrm_reg_ext=true, explicit_count=1}},
{.FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 200, {explicit_count=1, has_implict=true}},
{.FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 200, {explicit_count=1, has_implict=true}},
{.FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 200, {explicit_count=1, has_implicit=true}},
{.FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 200, {explicit_count=1, has_implicit=true}},
// .FMULP
{.FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 200, {explicit_count=1, has_implict=true}},
{.FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 200, {explicit_count=1, has_implicit=true}},
{.FMULP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 201, {}},
// .FIMUL
{.FIMUL, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 1, {modrm_reg_ext=true, explicit_count=1}},
@@ -3124,10 +3124,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
// .FDIV
{.FDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 6, {modrm_reg_ext=true, explicit_count=1}},
{.FDIV, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 6, {modrm_reg_ext=true, explicit_count=1}},
{.FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 240, {explicit_count=1, has_implict=true}},
{.FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 248, {explicit_count=1, has_implict=true}},
{.FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 240, {explicit_count=1, has_implicit=true}},
{.FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 248, {explicit_count=1, has_implicit=true}},
// .FDIVP
{.FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 248, {explicit_count=1, has_implict=true}},
{.FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 248, {explicit_count=1, has_implicit=true}},
{.FDIVP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 249, {}},
// .FIDIV
{.FIDIV, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 6, {modrm_reg_ext=true, explicit_count=1}},
@@ -3135,10 +3135,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
// .FDIVR
{.FDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 7, {modrm_reg_ext=true, explicit_count=1}},
{.FDIVR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 7, {modrm_reg_ext=true, explicit_count=1}},
{.FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 248, {explicit_count=1, has_implict=true}},
{.FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 240, {explicit_count=1, has_implict=true}},
{.FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 248, {explicit_count=1, has_implicit=true}},
{.FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 240, {explicit_count=1, has_implicit=true}},
// .FDIVRP
{.FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 240, {explicit_count=1, has_implict=true}},
{.FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 240, {explicit_count=1, has_implicit=true}},
{.FDIVRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 241, {}},
// .FIDIVR
{.FIDIVR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 7, {modrm_reg_ext=true, explicit_count=1}},
@@ -3198,21 +3198,21 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 200, {explicit_count=1}},
{.FXCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 201, {}},
// .FCMOVB
{.FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 192, {explicit_count=1, has_implict=true}},
{.FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 192, {explicit_count=1, has_implicit=true}},
// .FCMOVE
{.FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 200, {explicit_count=1, has_implict=true}},
{.FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 200, {explicit_count=1, has_implicit=true}},
// .FCMOVBE
{.FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 208, {explicit_count=1, has_implict=true}},
{.FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 208, {explicit_count=1, has_implicit=true}},
// .FCMOVU
{.FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 216, {explicit_count=1, has_implict=true}},
{.FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 216, {explicit_count=1, has_implicit=true}},
// .FCMOVNB
{.FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 192, {explicit_count=1, has_implict=true}},
{.FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 192, {explicit_count=1, has_implicit=true}},
// .FCMOVNE
{.FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 200, {explicit_count=1, has_implict=true}},
{.FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 200, {explicit_count=1, has_implicit=true}},
// .FCMOVNBE
{.FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 208, {explicit_count=1, has_implict=true}},
{.FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 208, {explicit_count=1, has_implicit=true}},
// .FCMOVNU
{.FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 216, {explicit_count=1, has_implict=true}},
{.FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 216, {explicit_count=1, has_implicit=true}},
// .FCOM
{.FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 2, {modrm_reg_ext=true, explicit_count=1}},
{.FCOM, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 2, {modrm_reg_ext=true, explicit_count=1}},
@@ -3232,13 +3232,13 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.FICOMP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 3, {modrm_reg_ext=true, explicit_count=1}},
{.FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 3, {modrm_reg_ext=true, explicit_count=1}},
// .FCOMI
{.FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 240, {explicit_count=1, has_implict=true}},
{.FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 240, {explicit_count=1, has_implicit=true}},
// .FCOMIP
{.FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 240, {explicit_count=1, has_implict=true}},
{.FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 240, {explicit_count=1, has_implicit=true}},
// .FUCOMI
{.FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 232, {explicit_count=1, has_implict=true}},
{.FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 232, {explicit_count=1, has_implicit=true}},
// .FUCOMIP
{.FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 232, {explicit_count=1, has_implict=true}},
{.FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 232, {explicit_count=1, has_implicit=true}},
// .FUCOM
{.FUCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 224, {explicit_count=1}},
{.FUCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDD, 225, {}},
@@ -3319,10 +3319,10 @@ ENCODE_FORMS := [2355]lib.Encoding{
{.FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 4, {modrm_reg_ext=true, explicit_count=1}},
// .FSTSW
{.FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true, explicit_count=1}},
{.FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implict=true}},
{.FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implicit=true}},
// .FNSTSW
{.FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true, explicit_count=1}},
{.FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implict=true}},
{.FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implicit=true}},
// .FXSAVE
{.FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}},
// .FXSAVE64

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core/rexcode/x86/tables/x86.encode_forms.bin
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core/rexcode/x86/tables/x86.evex.bin
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core/rexcode/x86/tables/x86.legacy.bin
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core/rexcode/x86/tables/x86.vex.bin
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