Merge pull request #4175 from laytan/riscv-compiler

Support RISC-V for the compiler itself

src/bug_report.cpp

@@ -155,7 +155,7 @@ gb_internal void report_windows_product_type(DWORD ProductType) {
 #endif
 
 gb_internal void odin_cpuid(int leaf, int result[]) {
-	#if defined(GB_CPU_ARM)
+	#if defined(GB_CPU_ARM) || defined(GB_CPU_RISCV)
 		return;
 
 	#elif defined(GB_CPU_X86)
@@ -225,6 +225,12 @@ gb_internal void report_cpu_info() {
 				gb_printf("ARM\n");
 			#endif
 		}
+	#elif defined(GB_CPU_RISCV)
+		#if defined(GB_ARCH_64_BIT)
+			gb_printf("RISCV64\n");
+		#else
+			gb_printf("RISCV32\n");
+		#endif
 	#else
 		gb_printf("Unknown\n");
 	#endif

src/build_settings.cpp

@@ -1525,6 +1525,8 @@ gb_internal void init_build_context(TargetMetrics *cross_target, Subtarget subta
 			metrics = &target_haiku_amd64;
 		#elif defined(GB_CPU_ARM)
 			metrics = &target_linux_arm64;
+		#elif defined(GB_CPU_RISCV)
+			metrics = &target_linux_riscv64;
 		#else
 			metrics = &target_linux_amd64;
 		#endif
@@ -1647,7 +1649,7 @@ gb_internal void init_build_context(TargetMetrics *cross_target, Subtarget subta
 
 		// Disallow on wasm
 		bc->use_separate_modules = false;
-	} if(bc->metrics.arch == TargetArch_riscv64) {
+	} if(bc->metrics.arch == TargetArch_riscv64 && bc->cross_compiling) {
 		bc->link_flags = str_lit("-target riscv64 ");
 	} else {
 		// NOTE: for targets other than darwin, we don't specify a `-target` link flag.

src/gb/gb.h

@@ -39,7 +39,7 @@ extern "C" {
 	#endif
 #endif
 
-#if defined(_WIN64) || defined(__x86_64__) || defined(_M_X64) || defined(__64BIT__) || defined(__powerpc64__) || defined(__ppc64__) || defined(__aarch64__)
+#if defined(_WIN64) || defined(__x86_64__) || defined(_M_X64) || defined(__64BIT__) || defined(__powerpc64__) || defined(__ppc64__) || defined(__aarch64__) || (defined(__riscv) && __riscv_xlen == 64)
 	#ifndef GB_ARCH_64_BIT
 	#define GB_ARCH_64_BIT 1
 	#endif
@@ -144,6 +144,13 @@ extern "C" {
 	#define GB_CACHE_LINE_SIZE 64
 	#endif
 
+#elif defined(__riscv)
+	#ifndef GB_CPU_RISCV
+	#define GB_CPU_RISCV 1
+	#endif
+	#ifndef GB_CACHE_LINE_SIZE
+	#define GB_CACHE_LINE_SIZE 64
+	#endif
 #else
 	#error Unknown CPU Type
 #endif
@@ -2562,7 +2569,7 @@ gb_inline void *gb_memcopy(void *dest, void const *source, isize n) {
 
 	void *dest_copy = dest;
 	__asm__ __volatile__("rep movsb" : "+D"(dest_copy), "+S"(source), "+c"(n) : : "memory");
-#elif defined(GB_CPU_ARM)
+#elif defined(GB_CPU_ARM) || defined(GB_CPU_RISCV)
 	u8 *s = cast(u8 *)source;
 	u8 *d = cast(u8 *)dest;
 	for (isize i = 0; i < n; i++) {
@@ -6267,6 +6274,12 @@ gb_no_inline isize gb_snprintf_va(char *text, isize max_len, char const *fmt, va
 		asm volatile("mrs %0, cntvct_el0" : "=r"(virtual_timer_value));
 		return virtual_timer_value;
 	}
+#elif defined(__riscv)
+	gb_inline u64 gb_rdtsc(void) {
+		u64 result = 0;
+		__asm__ volatile("rdcycle %0" : "=r"(result));
+		return result;
+	}
 #else
 #warning "gb_rdtsc not supported"
 	gb_inline u64 gb_rdtsc(void) { return 0; }

src/main.cpp

@@ -3252,6 +3252,12 @@ int main(int arg_count, char const **arg_ptr) {
 			gb_printf_err("missing required target feature: \"%.*s\", enable it by setting a different -microarch or explicitly adding it through -target-features\n", LIT(disabled));
 			gb_exit(1);
 		}
+
+		// NOTE(laytan): some weird errors on LLVM 14 that LLVM 17 fixes.
+		if (LLVM_VERSION_MAJOR < 17) {
+			gb_printf_err("Invalid LLVM version %s, RISC-V targets require at least LLVM 17\n", LLVM_VERSION_STRING);
+			gb_exit(1);
+		} 
 	}
 
 	if (build_context.show_debug_messages) {

src/threading.cpp

@@ -529,6 +529,9 @@ gb_internal gb_inline void yield_thread(void) {
 	_mm_pause();
 #elif defined(GB_CPU_ARM)
 	__asm__ volatile ("yield" : : : "memory");
+#elif defined(GB_CPU_RISCV)
+	// I guess?
+	__asm__ volatile ("nop" : : : "memory");
 #else
 #error Unknown architecture
 #endif