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rexcode/arm32: every VFP and NEON register list disassembled wrong

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`vpush {d8, d9}` came out as `vpush {r2}`. VFP list operands kept only
the 8-bit count from the encoding and stored it in a REG_LIST operand,
whose immediate the printer reads as a GPR bitmask -- so the register
bank was wrong, the start register was gone entirely, and the count was
read as a bitmask. `vldm r0, {d1, d2, d3}` printed `{r1-r2}`.

A list is now a register plus a shape: how many, and what the run steps
by. VLDM/VSTM/VPUSH/VPOP recover their start register from Vd and their
count from imm8. A GPR list stays a bitmask, since `{r4, lr}` is not a
run at all.

The NEON structure loads were wrong in a second way. VLD1-4/ST1-4 encode
their register count in the type field at bits 11:8, not in imm8, so
writing a count into the low byte overwrote size, alignment and Rm. Rm
was left at 0, which is a register post-increment, where the plain form
needs 0b1111; every one of those 23 forms encoded a writeback nobody
asked for. The count now comes from the form, the encoding writes only
Vd, and Rm is fixed in the pattern.

Deriving those counts from llvm-mc rather than by hand turned up a
dimension that was not modelled at all: the spaced forms step two
registers at a time (`vld2.8 {d2, d4}`), and VLD1 has a to-all-lanes
form written `{d2[]}`.

All 31 A32 list forms are now byte-exact against llvm-mc, from 8. The
arm32 sweep holds at 1656/1656.

Still open here: those forms only exist for .8 data, because the size
field at bits 7:6 is unencoded, and the writeback variants
(`[r0]!`, `[r0], r1`) are not modelled.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA
This commit is contained in:
Brendan Punsky
2026-08-28 00:08:07 -04:00
committed by Flāvius
parent bba65df7ee
commit 201dfdb454
13 changed files with 181 additions and 98 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
core/rexcode/isa/arm32/decoder.odin
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@@ -421,11 +421,40 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
case .VFP_IMM8:
a := ((word >> 16) & 0xF) << 4 | (word & 0xF)
return op_imm(i64(decode_vfp_imm8_f32(a)))
case .VFP_S_LIST, .VFP_D_LIST:
// Register count is encoded in bits 7..0 (count, not bitmask). Wrap
// as a REG_LIST so the encoder's shape_match for SPR_LIST/DPR_LIST
// accepts it; the encoder packs the same 8-bit count back out.
return op_reg_list(u16(word & 0xFF))
case .NEON_D_LIST_1:
n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
return op_reg_run(Register(REG_DPR | u16(n)), 1, 1, false)
case .NEON_D_LIST_2:
n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
return op_reg_run(Register(REG_DPR | u16(n)), 2, 1, false)
case .NEON_D_LIST_3:
n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
return op_reg_run(Register(REG_DPR | u16(n)), 3, 1, false)
case .NEON_D_LIST_4:
n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
return op_reg_run(Register(REG_DPR | u16(n)), 4, 1, false)
case .NEON_D_LIST_2X:
n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
return op_reg_run(Register(REG_DPR | u16(n)), 2, 2, false)
case .NEON_D_LIST_3X:
n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
return op_reg_run(Register(REG_DPR | u16(n)), 3, 2, false)
case .NEON_D_LIST_4X:
n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
return op_reg_run(Register(REG_DPR | u16(n)), 4, 2, false)
case .NEON_D_LIST_ALL:
n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
return op_reg_run(Register(REG_DPR | u16(n)), 1, 1, true)
case .VFP_S_LIST:
// {S<Vd>, ...} -- imm8 counts the registers, and the run starts at Vd.
// Both halves matter: keeping only the count printed the wrong bank
// and the wrong registers.
n := ((word >> 12) & 0xF) << 1 | ((word >> 22) & 1)
return op_reg_run(Register(REG_SPR | u16(n)), u8(word & 0xFF))
case .VFP_D_LIST:
// {D<Vd>, ...} -- imm8 counts half-words here, two per D register.
n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
return op_reg_run(Register(REG_DPR | u16(n)), u8((word & 0xFF) / 2))
// ---- Branch fields (decoded into RELATIVE) ----
case .BRANCH_24:

18
core/rexcode/isa/arm32/encoder.odin
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@@ -287,8 +287,10 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op
case .DPR_ELEM: return op.kind == .REGISTER && is_dpr(op.reg)
case .QPR_ELEM: return op.kind == .REGISTER && is_qpr(op.reg)
case .SPR_ELEM: return op.kind == .REGISTER && is_spr(op.reg)
case .SPR_LIST, .DPR_LIST:
return op.kind == .REG_LIST || (op.kind == .REGISTER && (is_spr(op.reg) || is_dpr(op.reg)))
case .SPR_LIST:
return op.kind == .REGISTER && is_spr(op.reg)
case .DPR_LIST:
return op.kind == .REGISTER && is_dpr(op.reg)
case .IMM, .IMM_MOD, .IMM_T32_MOD, .IMM12, .IMM5, .IMM5_W,
.IMM4, .IMM4_SAT, .IMM8, .IMM3, .IMM_HINT, .IMM_BARRIER,
.IMM_ENDIAN, .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM,
@@ -495,8 +497,16 @@ pack_operand_inline :: #force_inline proc(
case .NEON_OP_BIT: return (u32(op.immediate) & 1) << 5
// ---- VFP/NEON register lists (LDM/STM/PUSH/POP for FP regs) ------------
case .VFP_S_LIST, .VFP_D_LIST:
return u32(op.immediate) & 0xFF
case .NEON_D_LIST_1, .NEON_D_LIST_2, .NEON_D_LIST_3, .NEON_D_LIST_4, .NEON_D_LIST_2X, .NEON_D_LIST_3X, .NEON_D_LIST_4X, .NEON_D_LIST_ALL:
// Only Vd; the count lives in the form's type field.
n := u32(reg_hw(op.reg)) & 0x1F
return ((n >> 4) & 1) << 22 | (n & 0xF) << 12
case .VFP_S_LIST:
n := u32(reg_hw(op.reg)) & 0x1F
return ((n >> 1) & 0xF) << 12 | (n & 1) << 22 | (u32(op.list.count) & 0xFF)
case .VFP_D_LIST:
n := u32(reg_hw(op.reg)) & 0x1F
return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | ((u32(op.list.count) * 2) & 0xFF)
// ---- Memory addressing composites --------------------------------------
case .MEM_IMM12_OFFSET:

12
core/rexcode/isa/arm32/encoding_types.odin
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@@ -329,6 +329,18 @@ Operand_Encoding :: enum u8 {
// ---- VFP / NEON list ----
VFP_S_LIST, // VLDM/VSTM single-prec list (8-bit count, start in Vd_S)
VFP_D_LIST, // VLDM/VSTM double-prec list (8-bit count, start in Vd_D)
// NEON structure load/store lists (VLD1-4 / VST1-4). Unlike VLDM's list,
// the register count is part of the form's type field at bits 11:8, so the
// encoding writes only Vd; how many registers -- and whether the run steps
// by one or by two -- comes from the form. Verified against llvm-mc.
NEON_D_LIST_1, // {d2}
NEON_D_LIST_2, // {d2, d3}
NEON_D_LIST_3, // {d2, d3, d4}
NEON_D_LIST_4, // {d2, d3, d4, d5}
NEON_D_LIST_2X, // {d2, d4} -- spaced
NEON_D_LIST_3X, // {d2, d4, d6} -- spaced
NEON_D_LIST_4X, // {d2, d4, d6, d8} -- spaced
NEON_D_LIST_ALL, // {d2[]} -- to all lanes
// ---- Memory addressing composites ----
MEM_IMM12_OFFSET, // [Rn, #±imm12]

6
core/rexcode/isa/arm32/instructions.odin
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@@ -25,7 +25,7 @@ Instruction_Flags :: bit_field u8 {
// decode, because decode writes whole Instructions and unaligned stores are
// expensive enough to outweigh writing more bytes.
Instruction :: struct #align(64) {
ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 10 = 40
ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 11 = 44
mnemonic: Mnemonic, // 2
// cond, operand_count, mode, length and the two flag bits share one
// 16-bit word -- together they need 13 bits, and spending six bytes on
@@ -53,9 +53,9 @@ Instruction :: struct #align(64) {
// every instruction did before this field existed. Set it and the encoder
// picks the encoding for that type.
dt: Data_Types,
// Spare, and free: a 48-byte struct straddles a cache line, so these 16
// Spare, and free: a 48-byte struct straddles a cache line, so these
// bytes cost nothing. New fields land here without changing the layout.
_: [16]u8,
_: [12]u8,
}
#assert(size_of(Instruction) == 64)
#assert(align_of(Instruction) == 64)

21
core/rexcode/isa/arm32/operands.odin
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@@ -122,8 +122,20 @@ Operand :: struct #packed {
},
kind: Operand_Kind,
size: u8,
// How the syntax writes this register as a list. `count` 0 means a plain
// register. NEON structure loads also come in a spaced form that steps two
// registers at a time -- `{d2, d4}` -- and a to-all-lanes form written
// `{d2[]}`. A GPR list (`{r4, lr}`) is not a run at all and stays a
// bitmask under REG_LIST.
list: List_Shape,
}
#assert(size_of(Operand) == 10)
List_Shape :: bit_field u8 {
count: u8 | 3, // 0 = not a list, else 1..4
stride: u8 | 3, // 1 for {d2, d3}, 2 for {d2, d4}
all_lanes: bool | 1, // `{d2[]}` -- loaded to every lane
}
#assert(size_of(Operand) == 11)
// ---- Operand builders ------------------------------------------------------
@@ -157,6 +169,13 @@ op_rel_offset :: #force_inline proc "contextless" (off: i64) -> Operand {
op_reg_list :: #force_inline proc "contextless" (mask: u16) -> Operand {
return Operand{immediate = i64(mask), kind = .REG_LIST, size = 2}
}
// The head of a register list, written `{d1, d2, d3}` (stride 1) or
// `{d2, d4}` (stride 2).
@(require_results)
op_reg_run :: #force_inline proc "contextless" (first: Register, count: u8, stride: u8 = 1, all_lanes := false) -> Operand {
return Operand{reg = first, kind = .REGISTER, list = {count = count, stride = stride, all_lanes = all_lanes}}
}
@(require_results)
op_dpr_lane :: #force_inline proc "contextless" (d: Register, idx: u8) -> Operand {
return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx}

13
core/rexcode/isa/arm32/printer.odin
View File

@@ -527,6 +527,19 @@ write_operand :: proc(
case .NONE:
return
case .REGISTER:
// A VFP/NEON list is a contiguous run written in braces, and every
// register is named -- `{d1, d2, d3}`, not a range.
if op.list.count > 0 {
strings.write_string(sb, "{")
step := u16(max(op.list.stride, 1))
for n in 0 ..< u16(op.list.count) {
if n > 0 { strings.write_string(sb, ", ") }
write_register(sb, Register(reg_class(op.reg) | ((reg_hw(op.reg) + n * step) & 0x1F)))
if op.list.all_lanes { strings.write_string(sb, "[]") }
}
strings.write_string(sb, "}")
return
}
write_register(sb, op.reg)
write_shift(sb, op.shift_type, op.shift_amt)
if op.lane != 0 {

46
core/rexcode/isa/arm32/tablegen/encoding_table.odin
View File

@@ -2307,16 +2307,16 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// have distinct opcode bits; included as separate entries.
.VLD1 = {
// VLD1 multiple (1-reg list, type=0111, size=00/01/10/11, D form)
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_1, .RN_A32, .NONE, .NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
// VLD1 multiple (2-reg list, type=1010)
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
// VLD1 multiple (3-reg list, type=0110)
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
// VLD1 multiple (4-reg list, type=0010)
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
// VLD1 single lane to all lanes (VLD1R): 1111 0100 1 D 10 Rn Vd 1100 size T a Rm
// size 00 .8 / 01 .16 / 10 .32; T=0 single, T=1 pair
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_ALL, .RN_A32, .NONE, .NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
// VLD1 single lane: 1111 0100 1 D 10 Rn Vd 0X00 size idx_align Rm (X = 8/16/32 size selector)
{.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8
{.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16
@@ -2324,10 +2324,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
},
.VST1 = {
// VST1 multiple (1-reg list)
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_1, .RN_A32, .NONE, .NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
// VST1 single lane: 1111 0100 1 D 00 Rn Vd 0X00 size idx_align Rm
{.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8
{.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16
@@ -2335,30 +2335,30 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
},
// VLD2 / VST2 / VLD3 / VST3 / VLD4 / VST4 - similar pattern with different "type" bits
.VLD2 = {
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
},
.VST2 = {
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
},
.VLD3 = {
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
},
.VST3 = {
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
},
.VLD4 = {
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
},
.VST4 = {
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
},
// ---- VMULL / VMLAL / VMLSL (widening multiplies) ----

78
core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin
View File

@@ -186,8 +186,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
@@ -212,8 +212,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{
{ .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} },
{ .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} },
{ .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} },
{ .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} },
@@ -262,8 +262,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{
{ .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
{ .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
{ .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} },
{ .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
@@ -283,8 +283,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{
{ .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
{ .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} },
{ .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} },
{ .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
{ .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} },
{ .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
{ .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} },
{ .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} },
{ .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} },
@@ -695,8 +695,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{
{ .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} },
{ .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
@@ -820,30 +820,30 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{
{ .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} },
@@ -866,13 +866,13 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{
{ .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL,.RN_A32,.NONE,.NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} },
{ .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} },
@@ -1680,13 +1680,13 @@ DECODE_FORM_IDX := [1656]u16{
1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5,
4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14,
8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3,
0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3,
8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3,
0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 9, 3,
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0,
0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4,
4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4,
4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 4, 11, 4,
2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8,
1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10,
1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10,
8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4,
5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2,
1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0,
@@ -1711,7 +1711,7 @@ DECODE_FORM_IDX := [1656]u16{
3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4,
20, 14, 13, 9, 4, 4, 8, 4, 8, 6, 6, 3, 5, 5, 7, 7,
5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7,
0, 10, 0, 3, 1, 2, 0, 1, 3, 2, 0, 0, 0, 9, 4, 7,
0, 10, 0, 3, 1, 2, 0, 1, 3, 2, 0, 0, 0, 9, 7, 4,
5, 8, 2, 6, 3, 3, 7, 6, 5, 4, 2, 8, 9, 0, 1, 2,
0, 1, 5, 3, 0, 2, 1, 4, 0, 1, 2, 13, 11, 12, 10, 14,
13, 15, 12, 14, 15, 13, 12, 17, 15, 16, 14, 15, 16, 17, 14, 4,
@@ -1722,7 +1722,7 @@ DECODE_FORM_IDX := [1656]u16{
3, 2, 0, 1, 2, 3, 3, 0, 3, 0, 3, 3, 2, 0, 1, 0,
2, 1, 1, 0, 0, 1, 2, 2, 3, 0, 2, 1, 0, 1, 2, 0,
1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 5, 4, 6, 0, 2, 1,
0, 1, 2, 2, 1, 0, 1, 0, 2, 0, 0, 0, 6, 7, 4, 5,
0, 1, 2, 2, 1, 0, 1, 0, 2, 4, 0, 0, 0, 6, 5, 7,
1, 0, 2, 2, 1, 0, 0, 1, 2, 0, 2, 1, 0, 0, 1, 1,
0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -1892,10 +1892,10 @@ DECODE_BUCKET_LIST := [5379]u16{
397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412,
413, 810, 809, 811, 812, 813, 814, 815, 816, 817, 818, 819, 820, 821, 822, 823,
824, 827, 825, 826, 830, 829, 828, 831, 832, 834, 833, 835, 836, 837, 838, 839,
840, 841, 844, 843, 842, 845, 846, 847, 848, 849, 850, 851, 852, 853, 856, 854,
855, 822, 823, 857, 858, 859, 862, 861, 860, 863, 865, 866, 864, 867, 868, 869,
870, 871, 872, 874, 875, 873, 835, 836, 843, 844, 842, 845, 846, 847, 849, 850,
848, 851, 852, 853, 854, 855, 856, 837, 838, 839, 857, 858, 859, 862, 860, 861,
840, 841, 844, 843, 842, 845, 847, 846, 848, 850, 849, 852, 853, 851, 856, 855,
854, 822, 823, 857, 858, 859, 860, 862, 861, 863, 865, 866, 864, 867, 869, 868,
871, 870, 872, 874, 873, 875, 835, 836, 843, 844, 842, 845, 846, 847, 849, 850,
848, 851, 852, 853, 854, 855, 856, 837, 838, 839, 857, 858, 859, 860, 862, 861,
863, 866, 865, 864, 867, 868, 869, 871, 870, 872, 874, 873, 875, 840, 841, 876,
877, 878, 879, 880, 881, 882, 883, 884, 885, 886, 887, 888, 876, 877, 878, 879,
880, 889, 890, 881, 882, 888, 891, 892, 893, 894, 895, 896, 897, 898, 899, 900,

46
core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin
View File

@@ -1785,42 +1785,42 @@ ENCODE_FORMS := [1656]lib.Encoding{
{ .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} },
{ .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} },
// .VLD1
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL,.RN_A32,.NONE,.NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} },
// .VLD2
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
// .VLD3
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
// .VLD4
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
// .VST1
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} },
// .VST2
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
// .VST3
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
// .VST4
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
// .AESE
{ .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
// .AESD

BIN
core/rexcode/isa/arm32/tables/arm32.bucket_list.bin
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core/rexcode/isa/arm32/tables/arm32.encode_forms.bin
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core/rexcode/isa/arm32/tables/arm32.entries.bin
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core/rexcode/isa/arm32/tables/arm32.form_idx.bin
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