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Basic support for matrix*vector, vector*matrix operations

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This commit is contained in:
gingerBill
2021-10-19 11:24:26 +01:00
parent 35111b39b8
commit 243e2e2b8a
7 changed files with 207 additions and 130 deletions
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57
src/llvm_backend.cpp
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@@ -1135,13 +1135,46 @@ void lb_generate_code(lbGenerator *gen) {
auto *min_dep_set = &info->minimum_dependency_set;
LLVMInitializeAllTargetInfos();
LLVMInitializeAllTargets();
LLVMInitializeAllTargetMCs();
LLVMInitializeAllAsmPrinters();
LLVMInitializeAllAsmParsers();
LLVMInitializeAllDisassemblers();
LLVMInitializeNativeTarget();
switch (build_context.metrics.arch) {
case TargetArch_amd64:
case TargetArch_386:
LLVMInitializeX86TargetInfo();
LLVMInitializeX86Target();
LLVMInitializeX86TargetMC();
LLVMInitializeX86AsmPrinter();
LLVMInitializeX86AsmParser();
LLVMInitializeX86Disassembler();
break;
case TargetArch_arm64:
LLVMInitializeAArch64TargetInfo();
LLVMInitializeAArch64Target();
LLVMInitializeAArch64TargetMC();
LLVMInitializeAArch64AsmPrinter();
LLVMInitializeAArch64AsmParser();
LLVMInitializeAArch64Disassembler();
break;
case TargetArch_wasm32:
LLVMInitializeWebAssemblyTargetInfo();
LLVMInitializeWebAssemblyTarget();
LLVMInitializeWebAssemblyTargetMC();
LLVMInitializeWebAssemblyAsmPrinter();
LLVMInitializeWebAssemblyAsmParser();
LLVMInitializeWebAssemblyDisassembler();
break;
default:
LLVMInitializeAllTargetInfos();
LLVMInitializeAllTargets();
LLVMInitializeAllTargetMCs();
LLVMInitializeAllAsmPrinters();
LLVMInitializeAllAsmParsers();
LLVMInitializeAllDisassemblers();
break;
}
if (build_context.microarch == "native") {
LLVMInitializeNativeTarget();
}
char const *target_triple = alloc_cstring(permanent_allocator(), build_context.metrics.target_triplet);
for_array(i, gen->modules.entries) {
@@ -1174,6 +1207,14 @@ void lb_generate_code(lbGenerator *gen) {
if (gb_strcmp(llvm_cpu, host_cpu_name) == 0) {
llvm_features = LLVMGetHostCPUFeatures();
}
} else if (build_context.metrics.arch == TargetArch_amd64) {
// NOTE(bill): x86-64-v2 is more than enough for everyone
//
// x86-64: CMOV, CMPXCHG8B, FPU, FXSR, MMX, FXSR, SCE, SSE, SSE2
// x86-64-v2: (close to Nehalem) CMPXCHG16B, LAHF-SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3
// x86-64-v3: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE
// x86-64-v4: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL
llvm_cpu = "x86-64-v2";
}
// GB_ASSERT_MSG(LLVMTargetHasAsmBackend(target));
@@ -1640,6 +1681,7 @@ void lb_generate_code(lbGenerator *gen) {
code_gen_file_type = LLVMAssemblyFile;
}
for_array(j, gen->modules.entries) {
lbModule *m = gen->modules.entries[j].value;
if (LLVMVerifyModule(m->mod, LLVMReturnStatusAction, &llvm_error)) {
@@ -1684,7 +1726,6 @@ void lb_generate_code(lbGenerator *gen) {
}
}
TIME_SECTION("LLVM Add Foreign Library Paths");
for_array(j, gen->modules.entries) {