mirror of
https://github.com/odin-lang/Odin.git
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Update ENCODING_TABLE to support arity count and tail-call instructions
This commit is contained in:
gingerBill
@@ -20,479 +20,482 @@ package rexcode_wasm
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@(rodata)
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ENCODING_TABLE := [Mnemonic]Encoding{
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.INVALID = {},
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.INVALID = {inputs = 0, outputs = 0},
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// ------------------------------------------------------------------ control
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.UNREACHABLE = {prefix = PREFIX_NONE, opcode = 0x00, flags = CTRL},
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.NOP = {prefix = PREFIX_NONE, opcode = 0x01},
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.BLOCK = {prefix = PREFIX_NONE, opcode = 0x02, imm = {.BLOCKTYPE, .NONE}, flags = CTRL},
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.LOOP = {prefix = PREFIX_NONE, opcode = 0x03, imm = {.BLOCKTYPE, .NONE}, flags = CTRL},
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.IF = {prefix = PREFIX_NONE, opcode = 0x04, imm = {.BLOCKTYPE, .NONE}, flags = CTRL},
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.ELSE = {prefix = PREFIX_NONE, opcode = 0x05, flags = CTRL},
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.END = {prefix = PREFIX_NONE, opcode = 0x0B, flags = CTRL},
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.BR = {prefix = PREFIX_NONE, opcode = 0x0C, imm = {.IDX, .NONE}, flags = CTRL},
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.BR_IF = {prefix = PREFIX_NONE, opcode = 0x0D, imm = {.IDX, .NONE}, flags = CTRL},
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.BR_TABLE = {prefix = PREFIX_NONE, opcode = 0x0E, imm = {.BR_TABLE, .NONE}, flags = CTRL},
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.RETURN = {prefix = PREFIX_NONE, opcode = 0x0F, flags = CTRL},
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.CALL = {prefix = PREFIX_NONE, opcode = 0x10, imm = {.IDX, .NONE}, flags = CTRL},
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.CALL_INDIRECT = {prefix = PREFIX_NONE, opcode = 0x11, imm = {.IDX, .IDX}, flags = CTRL},
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.UNREACHABLE = {prefix = PREFIX_NONE, opcode = 0x00, flags = CTRL, inputs = 0, outputs = 0},
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.NOP = {prefix = PREFIX_NONE, opcode = 0x01, inputs = 0, outputs = 0},
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.BLOCK = {prefix = PREFIX_NONE, opcode = 0x02, imm = {.BLOCKTYPE, .NONE}, flags = CTRL, inputs = -1, outputs = -1},
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.LOOP = {prefix = PREFIX_NONE, opcode = 0x03, imm = {.BLOCKTYPE, .NONE}, flags = CTRL, inputs = -1, outputs = -1},
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.IF = {prefix = PREFIX_NONE, opcode = 0x04, imm = {.BLOCKTYPE, .NONE}, flags = CTRL, inputs = -1, outputs = -1},
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.ELSE = {prefix = PREFIX_NONE, opcode = 0x05, flags = CTRL, inputs = -1, outputs = -1},
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.END = {prefix = PREFIX_NONE, opcode = 0x0B, flags = CTRL, inputs = -1, outputs = -1},
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.BR = {prefix = PREFIX_NONE, opcode = 0x0C, imm = {.IDX, .NONE}, flags = CTRL, inputs = 0, outputs = 0},
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.BR_IF = {prefix = PREFIX_NONE, opcode = 0x0D, imm = {.IDX, .NONE}, flags = CTRL, inputs = 1, outputs = 0},
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.BR_TABLE = {prefix = PREFIX_NONE, opcode = 0x0E, imm = {.BR_TABLE, .NONE}, flags = CTRL, inputs = 1, outputs = 0},
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.RETURN = {prefix = PREFIX_NONE, opcode = 0x0F, flags = CTRL, inputs = -1, outputs = -1},
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.CALL = {prefix = PREFIX_NONE, opcode = 0x10, imm = {.IDX, .NONE}, flags = CTRL, inputs = -1, outputs = -1},
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.CALL_INDIRECT = {prefix = PREFIX_NONE, opcode = 0x11, imm = {.IDX, .NONE}, flags = CTRL, inputs = -1, outputs = -1},
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.RETURN_CALL = {prefix = PREFIX_NONE, opcode = 0x12, imm = {.IDX, .NONE}, flags = CTRL, inputs = -1, outputs = -1},
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.RETURN_CALL_INDIRECT = {prefix = PREFIX_NONE, opcode = 0x13, imm = {.IDX, .NONE}, flags = CTRL, inputs = -1, outputs = -1},
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// -------------------------------------------------------------- parametric
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.DROP = {prefix = PREFIX_NONE, opcode = 0x1A},
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.SELECT = {prefix = PREFIX_NONE, opcode = 0x1B},
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.DROP = {prefix = PREFIX_NONE, opcode = 0x1A, inputs = 1, outputs = 0},
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.SELECT = {prefix = PREFIX_NONE, opcode = 0x1B, inputs = 3, outputs = 1},
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// ---------------------------------------------------------------- variable
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.LOCAL_GET = {prefix = PREFIX_NONE, opcode = 0x20, imm = {.IDX, .NONE}},
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.LOCAL_SET = {prefix = PREFIX_NONE, opcode = 0x21, imm = {.IDX, .NONE}},
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.LOCAL_TEE = {prefix = PREFIX_NONE, opcode = 0x22, imm = {.IDX, .NONE}},
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.GLOBAL_GET = {prefix = PREFIX_NONE, opcode = 0x23, imm = {.IDX, .NONE}},
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.GLOBAL_SET = {prefix = PREFIX_NONE, opcode = 0x24, imm = {.IDX, .NONE}},
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.LOCAL_GET = {prefix = PREFIX_NONE, opcode = 0x20, imm = {.IDX, .NONE}, inputs = 0, outputs = 1},
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.LOCAL_SET = {prefix = PREFIX_NONE, opcode = 0x21, imm = {.IDX, .NONE}, inputs = 1, outputs = 0},
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.LOCAL_TEE = {prefix = PREFIX_NONE, opcode = 0x22, imm = {.IDX, .NONE}, inputs = 1, outputs = 1},
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.GLOBAL_GET = {prefix = PREFIX_NONE, opcode = 0x23, imm = {.IDX, .NONE}, inputs = 0, outputs = 1},
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.GLOBAL_SET = {prefix = PREFIX_NONE, opcode = 0x24, imm = {.IDX, .NONE}, inputs = 1, outputs = 0},
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// ------------------------------------------------------------------- memory
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.I32_LOAD = {prefix = PREFIX_NONE, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_LOAD = {prefix = PREFIX_NONE, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM},
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.F32_LOAD = {prefix = PREFIX_NONE, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM},
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.F64_LOAD = {prefix = PREFIX_NONE, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM},
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.I32_LOAD8_S = {prefix = PREFIX_NONE, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM},
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.I32_LOAD8_U = {prefix = PREFIX_NONE, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM},
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.I32_LOAD16_S = {prefix = PREFIX_NONE, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM},
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.I32_LOAD16_U = {prefix = PREFIX_NONE, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_LOAD8_S = {prefix = PREFIX_NONE, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_LOAD8_U = {prefix = PREFIX_NONE, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_LOAD16_S = {prefix = PREFIX_NONE, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_LOAD16_U = {prefix = PREFIX_NONE, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_LOAD32_S = {prefix = PREFIX_NONE, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_LOAD32_U = {prefix = PREFIX_NONE, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM},
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.I32_STORE = {prefix = PREFIX_NONE, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_STORE = {prefix = PREFIX_NONE, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM},
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.F32_STORE = {prefix = PREFIX_NONE, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM},
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.F64_STORE = {prefix = PREFIX_NONE, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM},
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.I32_STORE8 = {prefix = PREFIX_NONE, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM},
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.I32_STORE16 = {prefix = PREFIX_NONE, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_STORE8 = {prefix = PREFIX_NONE, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_STORE16 = {prefix = PREFIX_NONE, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM},
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.I64_STORE32 = {prefix = PREFIX_NONE, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM},
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.MEMORY_SIZE = {prefix = PREFIX_NONE, opcode = 0x3F, imm = {.ZERO_BYTE, .NONE}, flags = MEM},
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.MEMORY_GROW = {prefix = PREFIX_NONE, opcode = 0x40, imm = {.ZERO_BYTE, .NONE}, flags = MEM},
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.I32_LOAD = {prefix = PREFIX_NONE, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I64_LOAD = {prefix = PREFIX_NONE, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.F32_LOAD = {prefix = PREFIX_NONE, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.F64_LOAD = {prefix = PREFIX_NONE, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I32_LOAD8_S = {prefix = PREFIX_NONE, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I32_LOAD8_U = {prefix = PREFIX_NONE, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I32_LOAD16_S = {prefix = PREFIX_NONE, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I32_LOAD16_U = {prefix = PREFIX_NONE, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I64_LOAD8_S = {prefix = PREFIX_NONE, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I64_LOAD8_U = {prefix = PREFIX_NONE, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I64_LOAD16_S = {prefix = PREFIX_NONE, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I64_LOAD16_U = {prefix = PREFIX_NONE, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I64_LOAD32_S = {prefix = PREFIX_NONE, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I64_LOAD32_U = {prefix = PREFIX_NONE, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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.I32_STORE = {prefix = PREFIX_NONE, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
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.I64_STORE = {prefix = PREFIX_NONE, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
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.F32_STORE = {prefix = PREFIX_NONE, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
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.F64_STORE = {prefix = PREFIX_NONE, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
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.I32_STORE8 = {prefix = PREFIX_NONE, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
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.I32_STORE16 = {prefix = PREFIX_NONE, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
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.I64_STORE8 = {prefix = PREFIX_NONE, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
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.I64_STORE16 = {prefix = PREFIX_NONE, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
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.I64_STORE32 = {prefix = PREFIX_NONE, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
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.MEMORY_SIZE = {prefix = PREFIX_NONE, opcode = 0x3F, imm = {.ZERO_BYTE, .NONE}, flags = MEM, inputs = 0, outputs = 1},
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.MEMORY_GROW = {prefix = PREFIX_NONE, opcode = 0x40, imm = {.ZERO_BYTE, .NONE}, flags = MEM, inputs = 1, outputs = 1},
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// ----------------------------------------------------------------- numeric
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.I32_CONST = {prefix = PREFIX_NONE, opcode = 0x41, imm = {.I32, .NONE}},
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.I64_CONST = {prefix = PREFIX_NONE, opcode = 0x42, imm = {.I64, .NONE}},
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.F32_CONST = {prefix = PREFIX_NONE, opcode = 0x43, imm = {.F32, .NONE}},
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.F64_CONST = {prefix = PREFIX_NONE, opcode = 0x44, imm = {.F64, .NONE}},
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.I32_CONST = {prefix = PREFIX_NONE, opcode = 0x41, imm = {.I32, .NONE}, inputs = 0, outputs = 1},
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.I64_CONST = {prefix = PREFIX_NONE, opcode = 0x42, imm = {.I64, .NONE}, inputs = 0, outputs = 1},
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.F32_CONST = {prefix = PREFIX_NONE, opcode = 0x43, imm = {.F32, .NONE}, inputs = 0, outputs = 1},
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.F64_CONST = {prefix = PREFIX_NONE, opcode = 0x44, imm = {.F64, .NONE}, inputs = 0, outputs = 1},
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.I32_EQZ = {prefix = PREFIX_NONE, opcode = 0x45}, .I32_EQ = {prefix = PREFIX_NONE, opcode = 0x46}, .I32_NE = {prefix = PREFIX_NONE, opcode = 0x47},
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.I32_LT_S = {prefix = PREFIX_NONE, opcode = 0x48}, .I32_LT_U = {prefix = PREFIX_NONE, opcode = 0x49},
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.I32_GT_S = {prefix = PREFIX_NONE, opcode = 0x4A}, .I32_GT_U = {prefix = PREFIX_NONE, opcode = 0x4B},
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.I32_LE_S = {prefix = PREFIX_NONE, opcode = 0x4C}, .I32_LE_U = {prefix = PREFIX_NONE, opcode = 0x4D},
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.I32_GE_S = {prefix = PREFIX_NONE, opcode = 0x4E}, .I32_GE_U = {prefix = PREFIX_NONE, opcode = 0x4F},
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.I32_EQZ = {prefix = PREFIX_NONE, opcode = 0x45, inputs = 1, outputs = 1}, .I32_EQ = {prefix = PREFIX_NONE, opcode = 0x46, inputs = 2, outputs = 1}, .I32_NE = {prefix = PREFIX_NONE, opcode = 0x47, inputs = 2, outputs = 1},
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.I32_LT_S = {prefix = PREFIX_NONE, opcode = 0x48, inputs = 2, outputs = 1}, .I32_LT_U = {prefix = PREFIX_NONE, opcode = 0x49, inputs = 2, outputs = 1},
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.I32_GT_S = {prefix = PREFIX_NONE, opcode = 0x4A, inputs = 2, outputs = 1}, .I32_GT_U = {prefix = PREFIX_NONE, opcode = 0x4B, inputs = 2, outputs = 1},
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.I32_LE_S = {prefix = PREFIX_NONE, opcode = 0x4C, inputs = 2, outputs = 1}, .I32_LE_U = {prefix = PREFIX_NONE, opcode = 0x4D, inputs = 2, outputs = 1},
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.I32_GE_S = {prefix = PREFIX_NONE, opcode = 0x4E, inputs = 2, outputs = 1}, .I32_GE_U = {prefix = PREFIX_NONE, opcode = 0x4F, inputs = 2, outputs = 1},
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.I64_EQZ = {prefix = PREFIX_NONE, opcode = 0x50}, .I64_EQ = {prefix = PREFIX_NONE, opcode = 0x51}, .I64_NE = {prefix = PREFIX_NONE, opcode = 0x52},
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.I64_LT_S = {prefix = PREFIX_NONE, opcode = 0x53}, .I64_LT_U = {prefix = PREFIX_NONE, opcode = 0x54},
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.I64_GT_S = {prefix = PREFIX_NONE, opcode = 0x55}, .I64_GT_U = {prefix = PREFIX_NONE, opcode = 0x56},
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.I64_LE_S = {prefix = PREFIX_NONE, opcode = 0x57}, .I64_LE_U = {prefix = PREFIX_NONE, opcode = 0x58},
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.I64_GE_S = {prefix = PREFIX_NONE, opcode = 0x59}, .I64_GE_U = {prefix = PREFIX_NONE, opcode = 0x5A},
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.I64_EQZ = {prefix = PREFIX_NONE, opcode = 0x50, inputs = 1, outputs = 1}, .I64_EQ = {prefix = PREFIX_NONE, opcode = 0x51, inputs = 2, outputs = 1}, .I64_NE = {prefix = PREFIX_NONE, opcode = 0x52, inputs = 2, outputs = 1},
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.I64_LT_S = {prefix = PREFIX_NONE, opcode = 0x53, inputs = 2, outputs = 1}, .I64_LT_U = {prefix = PREFIX_NONE, opcode = 0x54, inputs = 2, outputs = 1},
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.I64_GT_S = {prefix = PREFIX_NONE, opcode = 0x55, inputs = 2, outputs = 1}, .I64_GT_U = {prefix = PREFIX_NONE, opcode = 0x56, inputs = 2, outputs = 1},
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.I64_LE_S = {prefix = PREFIX_NONE, opcode = 0x57, inputs = 2, outputs = 1}, .I64_LE_U = {prefix = PREFIX_NONE, opcode = 0x58, inputs = 2, outputs = 1},
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.I64_GE_S = {prefix = PREFIX_NONE, opcode = 0x59, inputs = 2, outputs = 1}, .I64_GE_U = {prefix = PREFIX_NONE, opcode = 0x5A, inputs = 2, outputs = 1},
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.F32_EQ = {prefix = PREFIX_NONE, opcode = 0x5B}, .F32_NE = {prefix = PREFIX_NONE, opcode = 0x5C},
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.F32_LT = {prefix = PREFIX_NONE, opcode = 0x5D}, .F32_GT = {prefix = PREFIX_NONE, opcode = 0x5E},
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.F32_LE = {prefix = PREFIX_NONE, opcode = 0x5F}, .F32_GE = {prefix = PREFIX_NONE, opcode = 0x60},
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.F32_EQ = {prefix = PREFIX_NONE, opcode = 0x5B, inputs = 2, outputs = 1}, .F32_NE = {prefix = PREFIX_NONE, opcode = 0x5C, inputs = 2, outputs = 1},
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.F32_LT = {prefix = PREFIX_NONE, opcode = 0x5D, inputs = 2, outputs = 1}, .F32_GT = {prefix = PREFIX_NONE, opcode = 0x5E, inputs = 2, outputs = 1},
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.F32_LE = {prefix = PREFIX_NONE, opcode = 0x5F, inputs = 2, outputs = 1}, .F32_GE = {prefix = PREFIX_NONE, opcode = 0x60, inputs = 2, outputs = 1},
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.F64_EQ = {prefix = PREFIX_NONE, opcode = 0x61}, .F64_NE = {prefix = PREFIX_NONE, opcode = 0x62},
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.F64_LT = {prefix = PREFIX_NONE, opcode = 0x63}, .F64_GT = {prefix = PREFIX_NONE, opcode = 0x64},
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.F64_LE = {prefix = PREFIX_NONE, opcode = 0x65}, .F64_GE = {prefix = PREFIX_NONE, opcode = 0x66},
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.F64_EQ = {prefix = PREFIX_NONE, opcode = 0x61, inputs = 2, outputs = 1}, .F64_NE = {prefix = PREFIX_NONE, opcode = 0x62, inputs = 2, outputs = 1},
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.F64_LT = {prefix = PREFIX_NONE, opcode = 0x63, inputs = 2, outputs = 1}, .F64_GT = {prefix = PREFIX_NONE, opcode = 0x64, inputs = 2, outputs = 1},
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.F64_LE = {prefix = PREFIX_NONE, opcode = 0x65, inputs = 2, outputs = 1}, .F64_GE = {prefix = PREFIX_NONE, opcode = 0x66, inputs = 2, outputs = 1},
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.I32_CLZ = {prefix = PREFIX_NONE, opcode = 0x67}, .I32_CTZ = {prefix = PREFIX_NONE, opcode = 0x68}, .I32_POPCNT = {prefix = PREFIX_NONE, opcode = 0x69},
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.I32_ADD = {prefix = PREFIX_NONE, opcode = 0x6A}, .I32_SUB = {prefix = PREFIX_NONE, opcode = 0x6B}, .I32_MUL = {prefix = PREFIX_NONE, opcode = 0x6C},
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.I32_DIV_S = {prefix = PREFIX_NONE, opcode = 0x6D}, .I32_DIV_U = {prefix = PREFIX_NONE, opcode = 0x6E},
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.I32_REM_S = {prefix = PREFIX_NONE, opcode = 0x6F}, .I32_REM_U = {prefix = PREFIX_NONE, opcode = 0x70},
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.I32_AND = {prefix = PREFIX_NONE, opcode = 0x71}, .I32_OR = {prefix = PREFIX_NONE, opcode = 0x72}, .I32_XOR = {prefix = PREFIX_NONE, opcode = 0x73},
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.I32_SHL = {prefix = PREFIX_NONE, opcode = 0x74}, .I32_SHR_S = {prefix = PREFIX_NONE, opcode = 0x75}, .I32_SHR_U = {prefix = PREFIX_NONE, opcode = 0x76},
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.I32_ROTL = {prefix = PREFIX_NONE, opcode = 0x77}, .I32_ROTR = {prefix = PREFIX_NONE, opcode = 0x78},
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.I32_CLZ = {prefix = PREFIX_NONE, opcode = 0x67, inputs = 1, outputs = 1}, .I32_CTZ = {prefix = PREFIX_NONE, opcode = 0x68, inputs = 1, outputs = 1}, .I32_POPCNT = {prefix = PREFIX_NONE, opcode = 0x69, inputs = 1, outputs = 1},
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.I32_ADD = {prefix = PREFIX_NONE, opcode = 0x6A, inputs = 2, outputs = 1}, .I32_SUB = {prefix = PREFIX_NONE, opcode = 0x6B, inputs = 2, outputs = 1}, .I32_MUL = {prefix = PREFIX_NONE, opcode = 0x6C, inputs = 2, outputs = 1},
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.I32_DIV_S = {prefix = PREFIX_NONE, opcode = 0x6D, inputs = 2, outputs = 1}, .I32_DIV_U = {prefix = PREFIX_NONE, opcode = 0x6E, inputs = 2, outputs = 1},
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.I32_REM_S = {prefix = PREFIX_NONE, opcode = 0x6F, inputs = 2, outputs = 1}, .I32_REM_U = {prefix = PREFIX_NONE, opcode = 0x70, inputs = 2, outputs = 1},
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.I32_AND = {prefix = PREFIX_NONE, opcode = 0x71, inputs = 2, outputs = 1}, .I32_OR = {prefix = PREFIX_NONE, opcode = 0x72, inputs = 2, outputs = 1}, .I32_XOR = {prefix = PREFIX_NONE, opcode = 0x73, inputs = 2, outputs = 1},
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.I32_SHL = {prefix = PREFIX_NONE, opcode = 0x74, inputs = 2, outputs = 1}, .I32_SHR_S = {prefix = PREFIX_NONE, opcode = 0x75, inputs = 2, outputs = 1}, .I32_SHR_U = {prefix = PREFIX_NONE, opcode = 0x76, inputs = 2, outputs = 1},
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.I32_ROTL = {prefix = PREFIX_NONE, opcode = 0x77, inputs = 2, outputs = 1}, .I32_ROTR = {prefix = PREFIX_NONE, opcode = 0x78, inputs = 2, outputs = 1},
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|
||||
.I64_CLZ = {prefix = PREFIX_NONE, opcode = 0x79}, .I64_CTZ = {prefix = PREFIX_NONE, opcode = 0x7A}, .I64_POPCNT = {prefix = PREFIX_NONE, opcode = 0x7B},
|
||||
.I64_ADD = {prefix = PREFIX_NONE, opcode = 0x7C}, .I64_SUB = {prefix = PREFIX_NONE, opcode = 0x7D}, .I64_MUL = {prefix = PREFIX_NONE, opcode = 0x7E},
|
||||
.I64_DIV_S = {prefix = PREFIX_NONE, opcode = 0x7F}, .I64_DIV_U = {prefix = PREFIX_NONE, opcode = 0x80},
|
||||
.I64_REM_S = {prefix = PREFIX_NONE, opcode = 0x81}, .I64_REM_U = {prefix = PREFIX_NONE, opcode = 0x82},
|
||||
.I64_AND = {prefix = PREFIX_NONE, opcode = 0x83}, .I64_OR = {prefix = PREFIX_NONE, opcode = 0x84}, .I64_XOR = {prefix = PREFIX_NONE, opcode = 0x85},
|
||||
.I64_SHL = {prefix = PREFIX_NONE, opcode = 0x86}, .I64_SHR_S = {prefix = PREFIX_NONE, opcode = 0x87}, .I64_SHR_U = {prefix = PREFIX_NONE, opcode = 0x88},
|
||||
.I64_ROTL = {prefix = PREFIX_NONE, opcode = 0x89}, .I64_ROTR = {prefix = PREFIX_NONE, opcode = 0x8A},
|
||||
.I64_CLZ = {prefix = PREFIX_NONE, opcode = 0x79, inputs = 1, outputs = 1}, .I64_CTZ = {prefix = PREFIX_NONE, opcode = 0x7A, inputs = 1, outputs = 1}, .I64_POPCNT = {prefix = PREFIX_NONE, opcode = 0x7B, inputs = 1, outputs = 1},
|
||||
.I64_ADD = {prefix = PREFIX_NONE, opcode = 0x7C, inputs = 2, outputs = 1}, .I64_SUB = {prefix = PREFIX_NONE, opcode = 0x7D, inputs = 2, outputs = 1}, .I64_MUL = {prefix = PREFIX_NONE, opcode = 0x7E, inputs = 2, outputs = 1},
|
||||
.I64_DIV_S = {prefix = PREFIX_NONE, opcode = 0x7F, inputs = 2, outputs = 1}, .I64_DIV_U = {prefix = PREFIX_NONE, opcode = 0x80, inputs = 2, outputs = 1},
|
||||
.I64_REM_S = {prefix = PREFIX_NONE, opcode = 0x81, inputs = 2, outputs = 1}, .I64_REM_U = {prefix = PREFIX_NONE, opcode = 0x82, inputs = 2, outputs = 1},
|
||||
.I64_AND = {prefix = PREFIX_NONE, opcode = 0x83, inputs = 2, outputs = 1}, .I64_OR = {prefix = PREFIX_NONE, opcode = 0x84, inputs = 2, outputs = 1}, .I64_XOR = {prefix = PREFIX_NONE, opcode = 0x85, inputs = 2, outputs = 1},
|
||||
.I64_SHL = {prefix = PREFIX_NONE, opcode = 0x86, inputs = 2, outputs = 1}, .I64_SHR_S = {prefix = PREFIX_NONE, opcode = 0x87, inputs = 2, outputs = 1}, .I64_SHR_U = {prefix = PREFIX_NONE, opcode = 0x88, inputs = 2, outputs = 1},
|
||||
.I64_ROTL = {prefix = PREFIX_NONE, opcode = 0x89, inputs = 2, outputs = 1}, .I64_ROTR = {prefix = PREFIX_NONE, opcode = 0x8A, inputs = 2, outputs = 1},
|
||||
|
||||
.F32_ABS = {prefix = PREFIX_NONE, opcode = 0x8B}, .F32_NEG = {prefix = PREFIX_NONE, opcode = 0x8C}, .F32_CEIL = {prefix = PREFIX_NONE, opcode = 0x8D},
|
||||
.F32_FLOOR = {prefix = PREFIX_NONE, opcode = 0x8E}, .F32_TRUNC = {prefix = PREFIX_NONE, opcode = 0x8F}, .F32_NEAREST = {prefix = PREFIX_NONE, opcode = 0x90},
|
||||
.F32_SQRT = {prefix = PREFIX_NONE, opcode = 0x91}, .F32_ADD = {prefix = PREFIX_NONE, opcode = 0x92}, .F32_SUB = {prefix = PREFIX_NONE, opcode = 0x93},
|
||||
.F32_MUL = {prefix = PREFIX_NONE, opcode = 0x94}, .F32_DIV = {prefix = PREFIX_NONE, opcode = 0x95}, .F32_MIN = {prefix = PREFIX_NONE, opcode = 0x96},
|
||||
.F32_MAX = {prefix = PREFIX_NONE, opcode = 0x97}, .F32_COPYSIGN = {prefix = PREFIX_NONE, opcode = 0x98},
|
||||
.F32_ABS = {prefix = PREFIX_NONE, opcode = 0x8B, inputs = 1, outputs = 1}, .F32_NEG = {prefix = PREFIX_NONE, opcode = 0x8C, inputs = 1, outputs = 1}, .F32_CEIL = {prefix = PREFIX_NONE, opcode = 0x8D, inputs = 1, outputs = 1},
|
||||
.F32_FLOOR = {prefix = PREFIX_NONE, opcode = 0x8E, inputs = 1, outputs = 1}, .F32_TRUNC = {prefix = PREFIX_NONE, opcode = 0x8F, inputs = 1, outputs = 1}, .F32_NEAREST = {prefix = PREFIX_NONE, opcode = 0x90, inputs = 1, outputs = 1},
|
||||
.F32_SQRT = {prefix = PREFIX_NONE, opcode = 0x91, inputs = 1, outputs = 1}, .F32_ADD = {prefix = PREFIX_NONE, opcode = 0x92, inputs = 2, outputs = 1}, .F32_SUB = {prefix = PREFIX_NONE, opcode = 0x93, inputs = 2, outputs = 1},
|
||||
.F32_MUL = {prefix = PREFIX_NONE, opcode = 0x94, inputs = 2, outputs = 1}, .F32_DIV = {prefix = PREFIX_NONE, opcode = 0x95, inputs = 2, outputs = 1}, .F32_MIN = {prefix = PREFIX_NONE, opcode = 0x96, inputs = 2, outputs = 1},
|
||||
.F32_MAX = {prefix = PREFIX_NONE, opcode = 0x97, inputs = 2, outputs = 1}, .F32_COPYSIGN = {prefix = PREFIX_NONE, opcode = 0x98, inputs = 2, outputs = 1},
|
||||
|
||||
.F64_ABS = {prefix = PREFIX_NONE, opcode = 0x99}, .F64_NEG = {prefix = PREFIX_NONE, opcode = 0x9A}, .F64_CEIL = {prefix = PREFIX_NONE, opcode = 0x9B},
|
||||
.F64_FLOOR = {prefix = PREFIX_NONE, opcode = 0x9C}, .F64_TRUNC = {prefix = PREFIX_NONE, opcode = 0x9D}, .F64_NEAREST = {prefix = PREFIX_NONE, opcode = 0x9E},
|
||||
.F64_SQRT = {prefix = PREFIX_NONE, opcode = 0x9F}, .F64_ADD = {prefix = PREFIX_NONE, opcode = 0xA0}, .F64_SUB = {prefix = PREFIX_NONE, opcode = 0xA1},
|
||||
.F64_MUL = {prefix = PREFIX_NONE, opcode = 0xA2}, .F64_DIV = {prefix = PREFIX_NONE, opcode = 0xA3}, .F64_MIN = {prefix = PREFIX_NONE, opcode = 0xA4},
|
||||
.F64_MAX = {prefix = PREFIX_NONE, opcode = 0xA5}, .F64_COPYSIGN = {prefix = PREFIX_NONE, opcode = 0xA6},
|
||||
.F64_ABS = {prefix = PREFIX_NONE, opcode = 0x99, inputs = 1, outputs = 1}, .F64_NEG = {prefix = PREFIX_NONE, opcode = 0x9A, inputs = 1, outputs = 1}, .F64_CEIL = {prefix = PREFIX_NONE, opcode = 0x9B, inputs = 1, outputs = 1},
|
||||
.F64_FLOOR = {prefix = PREFIX_NONE, opcode = 0x9C, inputs = 1, outputs = 1}, .F64_TRUNC = {prefix = PREFIX_NONE, opcode = 0x9D, inputs = 1, outputs = 1}, .F64_NEAREST = {prefix = PREFIX_NONE, opcode = 0x9E, inputs = 1, outputs = 1},
|
||||
.F64_SQRT = {prefix = PREFIX_NONE, opcode = 0x9F, inputs = 1, outputs = 1}, .F64_ADD = {prefix = PREFIX_NONE, opcode = 0xA0, inputs = 2, outputs = 1}, .F64_SUB = {prefix = PREFIX_NONE, opcode = 0xA1, inputs = 2, outputs = 1},
|
||||
.F64_MUL = {prefix = PREFIX_NONE, opcode = 0xA2, inputs = 2, outputs = 1}, .F64_DIV = {prefix = PREFIX_NONE, opcode = 0xA3, inputs = 2, outputs = 1}, .F64_MIN = {prefix = PREFIX_NONE, opcode = 0xA4, inputs = 2, outputs = 1},
|
||||
.F64_MAX = {prefix = PREFIX_NONE, opcode = 0xA5, inputs = 2, outputs = 1}, .F64_COPYSIGN = {prefix = PREFIX_NONE, opcode = 0xA6, inputs = 2, outputs = 1},
|
||||
|
||||
.I32_WRAP_I64 = {prefix = PREFIX_NONE, opcode = 0xA7},
|
||||
.I32_TRUNC_F32_S = {prefix = PREFIX_NONE, opcode = 0xA8}, .I32_TRUNC_F32_U = {prefix = PREFIX_NONE, opcode = 0xA9},
|
||||
.I32_TRUNC_F64_S = {prefix = PREFIX_NONE, opcode = 0xAA}, .I32_TRUNC_F64_U = {prefix = PREFIX_NONE, opcode = 0xAB},
|
||||
.I64_EXTEND_I32_S = {prefix = PREFIX_NONE, opcode = 0xAC}, .I64_EXTEND_I32_U = {prefix = PREFIX_NONE, opcode = 0xAD},
|
||||
.I64_TRUNC_F32_S = {prefix = PREFIX_NONE, opcode = 0xAE}, .I64_TRUNC_F32_U = {prefix = PREFIX_NONE, opcode = 0xAF},
|
||||
.I64_TRUNC_F64_S = {prefix = PREFIX_NONE, opcode = 0xB0}, .I64_TRUNC_F64_U = {prefix = PREFIX_NONE, opcode = 0xB1},
|
||||
.F32_CONVERT_I32_S = {prefix = PREFIX_NONE, opcode = 0xB2}, .F32_CONVERT_I32_U = {prefix = PREFIX_NONE, opcode = 0xB3},
|
||||
.F32_CONVERT_I64_S = {prefix = PREFIX_NONE, opcode = 0xB4}, .F32_CONVERT_I64_U = {prefix = PREFIX_NONE, opcode = 0xB5},
|
||||
.F32_DEMOTE_F64 = {prefix = PREFIX_NONE, opcode = 0xB6},
|
||||
.F64_CONVERT_I32_S = {prefix = PREFIX_NONE, opcode = 0xB7}, .F64_CONVERT_I32_U = {prefix = PREFIX_NONE, opcode = 0xB8},
|
||||
.F64_CONVERT_I64_S = {prefix = PREFIX_NONE, opcode = 0xB9}, .F64_CONVERT_I64_U = {prefix = PREFIX_NONE, opcode = 0xBA},
|
||||
.F64_PROMOTE_F32 = {prefix = PREFIX_NONE, opcode = 0xBB},
|
||||
.I32_REINTERPRET_F32 = {prefix = PREFIX_NONE, opcode = 0xBC}, .I64_REINTERPRET_F64 = {prefix = PREFIX_NONE, opcode = 0xBD},
|
||||
.F32_REINTERPRET_I32 = {prefix = PREFIX_NONE, opcode = 0xBE}, .F64_REINTERPRET_I64 = {prefix = PREFIX_NONE, opcode = 0xBF},
|
||||
.I32_WRAP_I64 = {prefix = PREFIX_NONE, opcode = 0xA7, inputs = 1, outputs = 1},
|
||||
.I32_TRUNC_F32_S = {prefix = PREFIX_NONE, opcode = 0xA8, inputs = 1, outputs = 1}, .I32_TRUNC_F32_U = {prefix = PREFIX_NONE, opcode = 0xA9, inputs = 1, outputs = 1},
|
||||
.I32_TRUNC_F64_S = {prefix = PREFIX_NONE, opcode = 0xAA, inputs = 1, outputs = 1}, .I32_TRUNC_F64_U = {prefix = PREFIX_NONE, opcode = 0xAB, inputs = 1, outputs = 1},
|
||||
.I64_EXTEND_I32_S = {prefix = PREFIX_NONE, opcode = 0xAC, inputs = 1, outputs = 1}, .I64_EXTEND_I32_U = {prefix = PREFIX_NONE, opcode = 0xAD, inputs = 1, outputs = 1},
|
||||
.I64_TRUNC_F32_S = {prefix = PREFIX_NONE, opcode = 0xAE, inputs = 1, outputs = 1}, .I64_TRUNC_F32_U = {prefix = PREFIX_NONE, opcode = 0xAF, inputs = 1, outputs = 1},
|
||||
.I64_TRUNC_F64_S = {prefix = PREFIX_NONE, opcode = 0xB0, inputs = 1, outputs = 1}, .I64_TRUNC_F64_U = {prefix = PREFIX_NONE, opcode = 0xB1, inputs = 1, outputs = 1},
|
||||
.F32_CONVERT_I32_S = {prefix = PREFIX_NONE, opcode = 0xB2, inputs = 1, outputs = 1}, .F32_CONVERT_I32_U = {prefix = PREFIX_NONE, opcode = 0xB3, inputs = 1, outputs = 1},
|
||||
.F32_CONVERT_I64_S = {prefix = PREFIX_NONE, opcode = 0xB4, inputs = 1, outputs = 1}, .F32_CONVERT_I64_U = {prefix = PREFIX_NONE, opcode = 0xB5, inputs = 1, outputs = 1},
|
||||
.F32_DEMOTE_F64 = {prefix = PREFIX_NONE, opcode = 0xB6, inputs = 1, outputs = 1},
|
||||
.F64_CONVERT_I32_S = {prefix = PREFIX_NONE, opcode = 0xB7, inputs = 1, outputs = 1}, .F64_CONVERT_I32_U = {prefix = PREFIX_NONE, opcode = 0xB8, inputs = 1, outputs = 1},
|
||||
.F64_CONVERT_I64_S = {prefix = PREFIX_NONE, opcode = 0xB9, inputs = 1, outputs = 1}, .F64_CONVERT_I64_U = {prefix = PREFIX_NONE, opcode = 0xBA, inputs = 1, outputs = 1},
|
||||
.F64_PROMOTE_F32 = {prefix = PREFIX_NONE, opcode = 0xBB, inputs = 1, outputs = 1},
|
||||
.I32_REINTERPRET_F32 = {prefix = PREFIX_NONE, opcode = 0xBC, inputs = 1, outputs = 1}, .I64_REINTERPRET_F64 = {prefix = PREFIX_NONE, opcode = 0xBD, inputs = 1, outputs = 1},
|
||||
.F32_REINTERPRET_I32 = {prefix = PREFIX_NONE, opcode = 0xBE, inputs = 1, outputs = 1}, .F64_REINTERPRET_I64 = {prefix = PREFIX_NONE, opcode = 0xBF, inputs = 1, outputs = 1},
|
||||
|
||||
.I32_EXTEND8_S = {prefix = PREFIX_NONE, opcode = 0xC0}, .I32_EXTEND16_S = {prefix = PREFIX_NONE, opcode = 0xC1},
|
||||
.I64_EXTEND8_S = {prefix = PREFIX_NONE, opcode = 0xC2}, .I64_EXTEND16_S = {prefix = PREFIX_NONE, opcode = 0xC3}, .I64_EXTEND32_S = {prefix = PREFIX_NONE, opcode = 0xC4},
|
||||
.I32_EXTEND8_S = {prefix = PREFIX_NONE, opcode = 0xC0, inputs = 1, outputs = 1}, .I32_EXTEND16_S = {prefix = PREFIX_NONE, opcode = 0xC1, inputs = 1, outputs = 1},
|
||||
.I64_EXTEND8_S = {prefix = PREFIX_NONE, opcode = 0xC2, inputs = 1, outputs = 1}, .I64_EXTEND16_S = {prefix = PREFIX_NONE, opcode = 0xC3, inputs = 1, outputs = 1}, .I64_EXTEND32_S = {prefix = PREFIX_NONE, opcode = 0xC4, inputs = 1, outputs = 1},
|
||||
|
||||
.REF_NULL = {prefix = PREFIX_NONE, opcode = 0xD0, imm = {.REFTYPE, .NONE}},
|
||||
.REF_IS_NULL = {prefix = PREFIX_NONE, opcode = 0xD1},
|
||||
.REF_FUNC = {prefix = PREFIX_NONE, opcode = 0xD2, imm = {.IDX, .NONE}},
|
||||
.REF_NULL = {prefix = PREFIX_NONE, opcode = 0xD0, imm = {.REFTYPE, .NONE}, inputs = 0, outputs = 1},
|
||||
.REF_IS_NULL = {prefix = PREFIX_NONE, opcode = 0xD1, inputs = 1, outputs = 1},
|
||||
.REF_FUNC = {prefix = PREFIX_NONE, opcode = 0xD2, imm = {.IDX, .NONE}, inputs = 0, outputs = 1},
|
||||
|
||||
// ------------------------------------------------------- 0xFC misc prefix
|
||||
.I32_TRUNC_SAT_F32_S = {prefix = PREFIX_MISC, opcode = 0}, .I32_TRUNC_SAT_F32_U = {prefix = PREFIX_MISC, opcode = 1},
|
||||
.I32_TRUNC_SAT_F64_S = {prefix = PREFIX_MISC, opcode = 2}, .I32_TRUNC_SAT_F64_U = {prefix = PREFIX_MISC, opcode = 3},
|
||||
.I64_TRUNC_SAT_F32_S = {prefix = PREFIX_MISC, opcode = 4}, .I64_TRUNC_SAT_F32_U = {prefix = PREFIX_MISC, opcode = 5},
|
||||
.I64_TRUNC_SAT_F64_S = {prefix = PREFIX_MISC, opcode = 6}, .I64_TRUNC_SAT_F64_U = {prefix = PREFIX_MISC, opcode = 7},
|
||||
.MEMORY_INIT = {prefix = PREFIX_MISC, opcode = 8, imm = {.IDX, .ZERO_BYTE}, flags = MEM},
|
||||
.DATA_DROP = {prefix = PREFIX_MISC, opcode = 9, imm = {.IDX, .NONE}},
|
||||
.MEMORY_COPY = {prefix = PREFIX_MISC, opcode = 10, imm = {.ZERO_BYTE, .ZERO_BYTE}, flags = MEM},
|
||||
.MEMORY_FILL = {prefix = PREFIX_MISC, opcode = 11, imm = {.ZERO_BYTE, .NONE}, flags = MEM},
|
||||
.TABLE_INIT = {prefix = PREFIX_MISC, opcode = 12, imm = {.IDX, .IDX}},
|
||||
.ELEM_DROP = {prefix = PREFIX_MISC, opcode = 13, imm = {.IDX, .NONE}},
|
||||
.TABLE_COPY = {prefix = PREFIX_MISC, opcode = 14, imm = {.IDX, .IDX}},
|
||||
.TABLE_GROW = {prefix = PREFIX_MISC, opcode = 15, imm = {.IDX, .NONE}},
|
||||
.TABLE_SIZE = {prefix = PREFIX_MISC, opcode = 16, imm = {.IDX, .NONE}},
|
||||
.TABLE_FILL = {prefix = PREFIX_MISC, opcode = 17, imm = {.IDX, .NONE}},
|
||||
.I32_TRUNC_SAT_F32_S = {prefix = PREFIX_MISC, opcode = 0, inputs = 1, outputs = 1}, .I32_TRUNC_SAT_F32_U = {prefix = PREFIX_MISC, opcode = 1, inputs = 1, outputs = 1},
|
||||
.I32_TRUNC_SAT_F64_S = {prefix = PREFIX_MISC, opcode = 2, inputs = 1, outputs = 1}, .I32_TRUNC_SAT_F64_U = {prefix = PREFIX_MISC, opcode = 3, inputs = 1, outputs = 1},
|
||||
.I64_TRUNC_SAT_F32_S = {prefix = PREFIX_MISC, opcode = 4, inputs = 1, outputs = 1}, .I64_TRUNC_SAT_F32_U = {prefix = PREFIX_MISC, opcode = 5, inputs = 1, outputs = 1},
|
||||
.I64_TRUNC_SAT_F64_S = {prefix = PREFIX_MISC, opcode = 6, inputs = 1, outputs = 1}, .I64_TRUNC_SAT_F64_U = {prefix = PREFIX_MISC, opcode = 7, inputs = 1, outputs = 1},
|
||||
.MEMORY_INIT = {prefix = PREFIX_MISC, opcode = 8, imm = {.IDX, .ZERO_BYTE}, flags = MEM, inputs = 3, outputs = 0},
|
||||
.DATA_DROP = {prefix = PREFIX_MISC, opcode = 9, imm = {.IDX, .NONE}, inputs = 0, outputs = 0},
|
||||
.MEMORY_COPY = {prefix = PREFIX_MISC, opcode = 10, imm = {.ZERO_BYTE, .ZERO_BYTE}, flags = MEM, inputs = 3, outputs = 0},
|
||||
.MEMORY_FILL = {prefix = PREFIX_MISC, opcode = 11, imm = {.ZERO_BYTE, .NONE}, flags = MEM, inputs = 3, outputs = 0},
|
||||
.TABLE_INIT = {prefix = PREFIX_MISC, opcode = 12, imm = {.IDX, .IDX}, inputs = 3, outputs = 0},
|
||||
.ELEM_DROP = {prefix = PREFIX_MISC, opcode = 13, imm = {.IDX, .NONE}, inputs = 0, outputs = 0},
|
||||
.TABLE_COPY = {prefix = PREFIX_MISC, opcode = 14, imm = {.IDX, .IDX}, inputs = 3, outputs = 0},
|
||||
.TABLE_GROW = {prefix = PREFIX_MISC, opcode = 15, imm = {.IDX, .NONE}, inputs = 2, outputs = 1},
|
||||
.TABLE_SIZE = {prefix = PREFIX_MISC, opcode = 16, imm = {.IDX, .NONE}, inputs = 0, outputs = 1},
|
||||
.TABLE_FILL = {prefix = PREFIX_MISC, opcode = 17, imm = {.IDX, .NONE}, inputs = 3, outputs = 0},
|
||||
|
||||
// ----------------------------------------------- 0xFD SIMD (v128) prefix
|
||||
.V128_LOAD = {prefix = PREFIX_SIMD, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD8X8_S = {prefix = PREFIX_SIMD, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD8X8_U = {prefix = PREFIX_SIMD, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD16X4_S = {prefix = PREFIX_SIMD, opcode = 0x03, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD16X4_U = {prefix = PREFIX_SIMD, opcode = 0x04, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD32X2_S = {prefix = PREFIX_SIMD, opcode = 0x05, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD32X2_U = {prefix = PREFIX_SIMD, opcode = 0x06, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD8_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x07, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD16_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x08, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD32_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x09, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD64_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x0A, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_STORE = {prefix = PREFIX_SIMD, opcode = 0x0B, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_CONST = {prefix = PREFIX_SIMD, opcode = 0x0C, imm = {.LANES16, .NONE}},
|
||||
.I8X16_SHUFFLE = {prefix = PREFIX_SIMD, opcode = 0x0D, imm = {.LANES16, .NONE}},
|
||||
.I8X16_SWIZZLE = {prefix = PREFIX_SIMD, opcode = 0x0E},
|
||||
.I8X16_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x0F},
|
||||
.I16X8_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x10},
|
||||
.I32X4_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x11},
|
||||
.I64X2_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x12},
|
||||
.F32X4_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x13},
|
||||
.F64X2_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x14},
|
||||
.I8X16_EXTRACT_LANE_S = {prefix = PREFIX_SIMD, opcode = 0x15, imm = {.LANE, .NONE}},
|
||||
.I8X16_EXTRACT_LANE_U = {prefix = PREFIX_SIMD, opcode = 0x16, imm = {.LANE, .NONE}},
|
||||
.I8X16_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x17, imm = {.LANE, .NONE}},
|
||||
.I16X8_EXTRACT_LANE_S = {prefix = PREFIX_SIMD, opcode = 0x18, imm = {.LANE, .NONE}},
|
||||
.I16X8_EXTRACT_LANE_U = {prefix = PREFIX_SIMD, opcode = 0x19, imm = {.LANE, .NONE}},
|
||||
.I16X8_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x1A, imm = {.LANE, .NONE}},
|
||||
.I32X4_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x1B, imm = {.LANE, .NONE}},
|
||||
.I32X4_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x1C, imm = {.LANE, .NONE}},
|
||||
.I64X2_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x1D, imm = {.LANE, .NONE}},
|
||||
.I64X2_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x1E, imm = {.LANE, .NONE}},
|
||||
.F32X4_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x1F, imm = {.LANE, .NONE}},
|
||||
.F32X4_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x20, imm = {.LANE, .NONE}},
|
||||
.F64X2_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x21, imm = {.LANE, .NONE}},
|
||||
.F64X2_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x22, imm = {.LANE, .NONE}},
|
||||
.I8X16_EQ = {prefix = PREFIX_SIMD, opcode = 0x23},
|
||||
.I8X16_NE = {prefix = PREFIX_SIMD, opcode = 0x24},
|
||||
.I8X16_LT_S = {prefix = PREFIX_SIMD, opcode = 0x25},
|
||||
.I8X16_LT_U = {prefix = PREFIX_SIMD, opcode = 0x26},
|
||||
.I8X16_GT_S = {prefix = PREFIX_SIMD, opcode = 0x27},
|
||||
.I8X16_GT_U = {prefix = PREFIX_SIMD, opcode = 0x28},
|
||||
.I8X16_LE_S = {prefix = PREFIX_SIMD, opcode = 0x29},
|
||||
.I8X16_LE_U = {prefix = PREFIX_SIMD, opcode = 0x2A},
|
||||
.I8X16_GE_S = {prefix = PREFIX_SIMD, opcode = 0x2B},
|
||||
.I8X16_GE_U = {prefix = PREFIX_SIMD, opcode = 0x2C},
|
||||
.I16X8_EQ = {prefix = PREFIX_SIMD, opcode = 0x2D},
|
||||
.I16X8_NE = {prefix = PREFIX_SIMD, opcode = 0x2E},
|
||||
.I16X8_LT_S = {prefix = PREFIX_SIMD, opcode = 0x2F},
|
||||
.I16X8_LT_U = {prefix = PREFIX_SIMD, opcode = 0x30},
|
||||
.I16X8_GT_S = {prefix = PREFIX_SIMD, opcode = 0x31},
|
||||
.I16X8_GT_U = {prefix = PREFIX_SIMD, opcode = 0x32},
|
||||
.I16X8_LE_S = {prefix = PREFIX_SIMD, opcode = 0x33},
|
||||
.I16X8_LE_U = {prefix = PREFIX_SIMD, opcode = 0x34},
|
||||
.I16X8_GE_S = {prefix = PREFIX_SIMD, opcode = 0x35},
|
||||
.I16X8_GE_U = {prefix = PREFIX_SIMD, opcode = 0x36},
|
||||
.I32X4_EQ = {prefix = PREFIX_SIMD, opcode = 0x37},
|
||||
.I32X4_NE = {prefix = PREFIX_SIMD, opcode = 0x38},
|
||||
.I32X4_LT_S = {prefix = PREFIX_SIMD, opcode = 0x39},
|
||||
.I32X4_LT_U = {prefix = PREFIX_SIMD, opcode = 0x3A},
|
||||
.I32X4_GT_S = {prefix = PREFIX_SIMD, opcode = 0x3B},
|
||||
.I32X4_GT_U = {prefix = PREFIX_SIMD, opcode = 0x3C},
|
||||
.I32X4_LE_S = {prefix = PREFIX_SIMD, opcode = 0x3D},
|
||||
.I32X4_LE_U = {prefix = PREFIX_SIMD, opcode = 0x3E},
|
||||
.I32X4_GE_S = {prefix = PREFIX_SIMD, opcode = 0x3F},
|
||||
.I32X4_GE_U = {prefix = PREFIX_SIMD, opcode = 0x40},
|
||||
.F32X4_EQ = {prefix = PREFIX_SIMD, opcode = 0x41},
|
||||
.F32X4_NE = {prefix = PREFIX_SIMD, opcode = 0x42},
|
||||
.F32X4_LT = {prefix = PREFIX_SIMD, opcode = 0x43},
|
||||
.F32X4_GT = {prefix = PREFIX_SIMD, opcode = 0x44},
|
||||
.F32X4_LE = {prefix = PREFIX_SIMD, opcode = 0x45},
|
||||
.F32X4_GE = {prefix = PREFIX_SIMD, opcode = 0x46},
|
||||
.F64X2_EQ = {prefix = PREFIX_SIMD, opcode = 0x47},
|
||||
.F64X2_NE = {prefix = PREFIX_SIMD, opcode = 0x48},
|
||||
.F64X2_LT = {prefix = PREFIX_SIMD, opcode = 0x49},
|
||||
.F64X2_GT = {prefix = PREFIX_SIMD, opcode = 0x4A},
|
||||
.F64X2_LE = {prefix = PREFIX_SIMD, opcode = 0x4B},
|
||||
.F64X2_GE = {prefix = PREFIX_SIMD, opcode = 0x4C},
|
||||
.V128_NOT = {prefix = PREFIX_SIMD, opcode = 0x4D},
|
||||
.V128_AND = {prefix = PREFIX_SIMD, opcode = 0x4E},
|
||||
.V128_ANDNOT = {prefix = PREFIX_SIMD, opcode = 0x4F},
|
||||
.V128_OR = {prefix = PREFIX_SIMD, opcode = 0x50},
|
||||
.V128_XOR = {prefix = PREFIX_SIMD, opcode = 0x51},
|
||||
.V128_BITSELECT = {prefix = PREFIX_SIMD, opcode = 0x52},
|
||||
.V128_ANY_TRUE = {prefix = PREFIX_SIMD, opcode = 0x53},
|
||||
.V128_LOAD8_LANE = {prefix = PREFIX_SIMD, opcode = 0x54, imm = {.MEMARG, .LANE}, flags = MEM},
|
||||
.V128_LOAD16_LANE = {prefix = PREFIX_SIMD, opcode = 0x55, imm = {.MEMARG, .LANE}, flags = MEM},
|
||||
.V128_LOAD32_LANE = {prefix = PREFIX_SIMD, opcode = 0x56, imm = {.MEMARG, .LANE}, flags = MEM},
|
||||
.V128_LOAD64_LANE = {prefix = PREFIX_SIMD, opcode = 0x57, imm = {.MEMARG, .LANE}, flags = MEM},
|
||||
.V128_STORE8_LANE = {prefix = PREFIX_SIMD, opcode = 0x58, imm = {.MEMARG, .LANE}, flags = MEM},
|
||||
.V128_STORE16_LANE = {prefix = PREFIX_SIMD, opcode = 0x59, imm = {.MEMARG, .LANE}, flags = MEM},
|
||||
.V128_STORE32_LANE = {prefix = PREFIX_SIMD, opcode = 0x5A, imm = {.MEMARG, .LANE}, flags = MEM},
|
||||
.V128_STORE64_LANE = {prefix = PREFIX_SIMD, opcode = 0x5B, imm = {.MEMARG, .LANE}, flags = MEM},
|
||||
.V128_LOAD32_ZERO = {prefix = PREFIX_SIMD, opcode = 0x5C, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.V128_LOAD64_ZERO = {prefix = PREFIX_SIMD, opcode = 0x5D, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.F32X4_DEMOTE_F64X2_ZERO = {prefix = PREFIX_SIMD, opcode = 0x5E},
|
||||
.F64X2_PROMOTE_LOW_F32X4 = {prefix = PREFIX_SIMD, opcode = 0x5F},
|
||||
.I8X16_ABS = {prefix = PREFIX_SIMD, opcode = 0x60},
|
||||
.I8X16_NEG = {prefix = PREFIX_SIMD, opcode = 0x61},
|
||||
.I8X16_POPCNT = {prefix = PREFIX_SIMD, opcode = 0x62},
|
||||
.I8X16_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0x63},
|
||||
.I8X16_BITMASK = {prefix = PREFIX_SIMD, opcode = 0x64},
|
||||
.I8X16_NARROW_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0x65},
|
||||
.I8X16_NARROW_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0x66},
|
||||
.F32X4_CEIL = {prefix = PREFIX_SIMD, opcode = 0x67},
|
||||
.F32X4_FLOOR = {prefix = PREFIX_SIMD, opcode = 0x68},
|
||||
.F32X4_TRUNC = {prefix = PREFIX_SIMD, opcode = 0x69},
|
||||
.F32X4_NEAREST = {prefix = PREFIX_SIMD, opcode = 0x6A},
|
||||
.I8X16_SHL = {prefix = PREFIX_SIMD, opcode = 0x6B},
|
||||
.I8X16_SHR_S = {prefix = PREFIX_SIMD, opcode = 0x6C},
|
||||
.I8X16_SHR_U = {prefix = PREFIX_SIMD, opcode = 0x6D},
|
||||
.I8X16_ADD = {prefix = PREFIX_SIMD, opcode = 0x6E},
|
||||
.I8X16_ADD_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x6F},
|
||||
.I8X16_ADD_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x70},
|
||||
.I8X16_SUB = {prefix = PREFIX_SIMD, opcode = 0x71},
|
||||
.I8X16_SUB_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x72},
|
||||
.I8X16_SUB_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x73},
|
||||
.F64X2_CEIL = {prefix = PREFIX_SIMD, opcode = 0x74},
|
||||
.F64X2_FLOOR = {prefix = PREFIX_SIMD, opcode = 0x75},
|
||||
.I8X16_MIN_S = {prefix = PREFIX_SIMD, opcode = 0x76},
|
||||
.I8X16_MIN_U = {prefix = PREFIX_SIMD, opcode = 0x77},
|
||||
.I8X16_MAX_S = {prefix = PREFIX_SIMD, opcode = 0x78},
|
||||
.I8X16_MAX_U = {prefix = PREFIX_SIMD, opcode = 0x79},
|
||||
.F64X2_TRUNC = {prefix = PREFIX_SIMD, opcode = 0x7A},
|
||||
.I8X16_AVGR_U = {prefix = PREFIX_SIMD, opcode = 0x7B},
|
||||
.I16X8_EXTADD_PAIRWISE_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x7C},
|
||||
.I16X8_EXTADD_PAIRWISE_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x7D},
|
||||
.I32X4_EXTADD_PAIRWISE_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0x7E},
|
||||
.I32X4_EXTADD_PAIRWISE_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0x7F},
|
||||
.I16X8_ABS = {prefix = PREFIX_SIMD, opcode = 0x80},
|
||||
.I16X8_NEG = {prefix = PREFIX_SIMD, opcode = 0x81},
|
||||
.I16X8_Q15MULR_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x82},
|
||||
.I16X8_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0x83},
|
||||
.I16X8_BITMASK = {prefix = PREFIX_SIMD, opcode = 0x84},
|
||||
.I16X8_NARROW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0x85},
|
||||
.I16X8_NARROW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0x86},
|
||||
.I16X8_EXTEND_LOW_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x87},
|
||||
.I16X8_EXTEND_HIGH_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x88},
|
||||
.I16X8_EXTEND_LOW_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x89},
|
||||
.I16X8_EXTEND_HIGH_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x8A},
|
||||
.I16X8_SHL = {prefix = PREFIX_SIMD, opcode = 0x8B},
|
||||
.I16X8_SHR_S = {prefix = PREFIX_SIMD, opcode = 0x8C},
|
||||
.I16X8_SHR_U = {prefix = PREFIX_SIMD, opcode = 0x8D},
|
||||
.I16X8_ADD = {prefix = PREFIX_SIMD, opcode = 0x8E},
|
||||
.I16X8_ADD_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x8F},
|
||||
.I16X8_ADD_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x90},
|
||||
.I16X8_SUB = {prefix = PREFIX_SIMD, opcode = 0x91},
|
||||
.I16X8_SUB_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x92},
|
||||
.I16X8_SUB_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x93},
|
||||
.F64X2_NEAREST = {prefix = PREFIX_SIMD, opcode = 0x94},
|
||||
.I16X8_MUL = {prefix = PREFIX_SIMD, opcode = 0x95},
|
||||
.I16X8_MIN_S = {prefix = PREFIX_SIMD, opcode = 0x96},
|
||||
.I16X8_MIN_U = {prefix = PREFIX_SIMD, opcode = 0x97},
|
||||
.I16X8_MAX_S = {prefix = PREFIX_SIMD, opcode = 0x98},
|
||||
.I16X8_MAX_U = {prefix = PREFIX_SIMD, opcode = 0x99},
|
||||
.I16X8_AVGR_U = {prefix = PREFIX_SIMD, opcode = 0x9B},
|
||||
.I16X8_EXTMUL_LOW_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x9C},
|
||||
.I16X8_EXTMUL_HIGH_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x9D},
|
||||
.I16X8_EXTMUL_LOW_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x9E},
|
||||
.I16X8_EXTMUL_HIGH_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x9F},
|
||||
.I32X4_ABS = {prefix = PREFIX_SIMD, opcode = 0xA0},
|
||||
.I32X4_NEG = {prefix = PREFIX_SIMD, opcode = 0xA1},
|
||||
.I32X4_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0xA3},
|
||||
.I32X4_BITMASK = {prefix = PREFIX_SIMD, opcode = 0xA4},
|
||||
.I32X4_EXTEND_LOW_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xA7},
|
||||
.I32X4_EXTEND_HIGH_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xA8},
|
||||
.I32X4_EXTEND_LOW_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xA9},
|
||||
.I32X4_EXTEND_HIGH_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xAA},
|
||||
.I32X4_SHL = {prefix = PREFIX_SIMD, opcode = 0xAB},
|
||||
.I32X4_SHR_S = {prefix = PREFIX_SIMD, opcode = 0xAC},
|
||||
.I32X4_SHR_U = {prefix = PREFIX_SIMD, opcode = 0xAD},
|
||||
.I32X4_ADD = {prefix = PREFIX_SIMD, opcode = 0xAE},
|
||||
.I32X4_SUB = {prefix = PREFIX_SIMD, opcode = 0xB1},
|
||||
.I32X4_MUL = {prefix = PREFIX_SIMD, opcode = 0xB5},
|
||||
.I32X4_MIN_S = {prefix = PREFIX_SIMD, opcode = 0xB6},
|
||||
.I32X4_MIN_U = {prefix = PREFIX_SIMD, opcode = 0xB7},
|
||||
.I32X4_MAX_S = {prefix = PREFIX_SIMD, opcode = 0xB8},
|
||||
.I32X4_MAX_U = {prefix = PREFIX_SIMD, opcode = 0xB9},
|
||||
.I32X4_DOT_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xBA},
|
||||
.I32X4_EXTMUL_LOW_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xBC},
|
||||
.I32X4_EXTMUL_HIGH_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xBD},
|
||||
.I32X4_EXTMUL_LOW_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xBE},
|
||||
.I32X4_EXTMUL_HIGH_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xBF},
|
||||
.I64X2_ABS = {prefix = PREFIX_SIMD, opcode = 0xC0},
|
||||
.I64X2_NEG = {prefix = PREFIX_SIMD, opcode = 0xC1},
|
||||
.I64X2_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0xC3},
|
||||
.I64X2_BITMASK = {prefix = PREFIX_SIMD, opcode = 0xC4},
|
||||
.I64X2_EXTEND_LOW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xC7},
|
||||
.I64X2_EXTEND_HIGH_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xC8},
|
||||
.I64X2_EXTEND_LOW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xC9},
|
||||
.I64X2_EXTEND_HIGH_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xCA},
|
||||
.I64X2_SHL = {prefix = PREFIX_SIMD, opcode = 0xCB},
|
||||
.I64X2_SHR_S = {prefix = PREFIX_SIMD, opcode = 0xCC},
|
||||
.I64X2_SHR_U = {prefix = PREFIX_SIMD, opcode = 0xCD},
|
||||
.I64X2_ADD = {prefix = PREFIX_SIMD, opcode = 0xCE},
|
||||
.I64X2_SUB = {prefix = PREFIX_SIMD, opcode = 0xD1},
|
||||
.I64X2_MUL = {prefix = PREFIX_SIMD, opcode = 0xD5},
|
||||
.I64X2_EQ = {prefix = PREFIX_SIMD, opcode = 0xD6},
|
||||
.I64X2_NE = {prefix = PREFIX_SIMD, opcode = 0xD7},
|
||||
.I64X2_LT_S = {prefix = PREFIX_SIMD, opcode = 0xD8},
|
||||
.I64X2_GT_S = {prefix = PREFIX_SIMD, opcode = 0xD9},
|
||||
.I64X2_LE_S = {prefix = PREFIX_SIMD, opcode = 0xDA},
|
||||
.I64X2_GE_S = {prefix = PREFIX_SIMD, opcode = 0xDB},
|
||||
.I64X2_EXTMUL_LOW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xDC},
|
||||
.I64X2_EXTMUL_HIGH_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xDD},
|
||||
.I64X2_EXTMUL_LOW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xDE},
|
||||
.I64X2_EXTMUL_HIGH_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xDF},
|
||||
.F32X4_ABS = {prefix = PREFIX_SIMD, opcode = 0xE0},
|
||||
.F32X4_NEG = {prefix = PREFIX_SIMD, opcode = 0xE1},
|
||||
.F32X4_SQRT = {prefix = PREFIX_SIMD, opcode = 0xE3},
|
||||
.F32X4_ADD = {prefix = PREFIX_SIMD, opcode = 0xE4},
|
||||
.F32X4_SUB = {prefix = PREFIX_SIMD, opcode = 0xE5},
|
||||
.F32X4_MUL = {prefix = PREFIX_SIMD, opcode = 0xE6},
|
||||
.F32X4_DIV = {prefix = PREFIX_SIMD, opcode = 0xE7},
|
||||
.F32X4_MIN = {prefix = PREFIX_SIMD, opcode = 0xE8},
|
||||
.F32X4_MAX = {prefix = PREFIX_SIMD, opcode = 0xE9},
|
||||
.F32X4_PMIN = {prefix = PREFIX_SIMD, opcode = 0xEA},
|
||||
.F32X4_PMAX = {prefix = PREFIX_SIMD, opcode = 0xEB},
|
||||
.F64X2_ABS = {prefix = PREFIX_SIMD, opcode = 0xEC},
|
||||
.F64X2_NEG = {prefix = PREFIX_SIMD, opcode = 0xED},
|
||||
.F64X2_SQRT = {prefix = PREFIX_SIMD, opcode = 0xEF},
|
||||
.F64X2_ADD = {prefix = PREFIX_SIMD, opcode = 0xF0},
|
||||
.F64X2_SUB = {prefix = PREFIX_SIMD, opcode = 0xF1},
|
||||
.F64X2_MUL = {prefix = PREFIX_SIMD, opcode = 0xF2},
|
||||
.F64X2_DIV = {prefix = PREFIX_SIMD, opcode = 0xF3},
|
||||
.F64X2_MIN = {prefix = PREFIX_SIMD, opcode = 0xF4},
|
||||
.F64X2_MAX = {prefix = PREFIX_SIMD, opcode = 0xF5},
|
||||
.F64X2_PMIN = {prefix = PREFIX_SIMD, opcode = 0xF6},
|
||||
.F64X2_PMAX = {prefix = PREFIX_SIMD, opcode = 0xF7},
|
||||
.I32X4_TRUNC_SAT_F32X4_S = {prefix = PREFIX_SIMD, opcode = 0xF8},
|
||||
.I32X4_TRUNC_SAT_F32X4_U = {prefix = PREFIX_SIMD, opcode = 0xF9},
|
||||
.F32X4_CONVERT_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xFA},
|
||||
.F32X4_CONVERT_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xFB},
|
||||
.I32X4_TRUNC_SAT_F64X2_S_ZERO = {prefix = PREFIX_SIMD, opcode = 0xFC},
|
||||
.I32X4_TRUNC_SAT_F64X2_U_ZERO = {prefix = PREFIX_SIMD, opcode = 0xFD},
|
||||
.F64X2_CONVERT_LOW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xFE},
|
||||
.F64X2_CONVERT_LOW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xFF},
|
||||
.I8X16_RELAXED_SWIZZLE = {prefix = PREFIX_SIMD, opcode = 0x100},
|
||||
.I32X4_RELAXED_TRUNC_F32X4_S = {prefix = PREFIX_SIMD, opcode = 0x101},
|
||||
.I32X4_RELAXED_TRUNC_F32X4_U = {prefix = PREFIX_SIMD, opcode = 0x102},
|
||||
.I32X4_RELAXED_TRUNC_F64X2_S_ZERO = {prefix = PREFIX_SIMD, opcode = 0x103},
|
||||
.I32X4_RELAXED_TRUNC_F64X2_U_ZERO = {prefix = PREFIX_SIMD, opcode = 0x104},
|
||||
.F32X4_RELAXED_MADD = {prefix = PREFIX_SIMD, opcode = 0x105},
|
||||
.F32X4_RELAXED_NMADD = {prefix = PREFIX_SIMD, opcode = 0x106},
|
||||
.F64X2_RELAXED_MADD = {prefix = PREFIX_SIMD, opcode = 0x107},
|
||||
.F64X2_RELAXED_NMADD = {prefix = PREFIX_SIMD, opcode = 0x108},
|
||||
.I8X16_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x109},
|
||||
.I16X8_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x10A},
|
||||
.I32X4_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x10B},
|
||||
.I64X2_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x10C},
|
||||
.F32X4_RELAXED_MIN = {prefix = PREFIX_SIMD, opcode = 0x10D},
|
||||
.F32X4_RELAXED_MAX = {prefix = PREFIX_SIMD, opcode = 0x10E},
|
||||
.F64X2_RELAXED_MIN = {prefix = PREFIX_SIMD, opcode = 0x10F},
|
||||
.F64X2_RELAXED_MAX = {prefix = PREFIX_SIMD, opcode = 0x110},
|
||||
.I16X8_RELAXED_Q15MULR_S = {prefix = PREFIX_SIMD, opcode = 0x111},
|
||||
.I16X8_RELAXED_DOT_I8X16_I7X16_S = {prefix = PREFIX_SIMD, opcode = 0x112},
|
||||
.I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S = {prefix = PREFIX_SIMD, opcode = 0x113},
|
||||
.V128_LOAD = {prefix = PREFIX_SIMD, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD8X8_S = {prefix = PREFIX_SIMD, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD8X8_U = {prefix = PREFIX_SIMD, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD16X4_S = {prefix = PREFIX_SIMD, opcode = 0x03, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD16X4_U = {prefix = PREFIX_SIMD, opcode = 0x04, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD32X2_S = {prefix = PREFIX_SIMD, opcode = 0x05, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD32X2_U = {prefix = PREFIX_SIMD, opcode = 0x06, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD8_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x07, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD16_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x08, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD32_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x09, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD64_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x0A, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_STORE = {prefix = PREFIX_SIMD, opcode = 0x0B, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.V128_CONST = {prefix = PREFIX_SIMD, opcode = 0x0C, imm = {.LANES16, .NONE}, inputs = 0, outputs = 1},
|
||||
.I8X16_SHUFFLE = {prefix = PREFIX_SIMD, opcode = 0x0D, imm = {.LANES16, .NONE}, inputs = 2, outputs = 1},
|
||||
.I8X16_SWIZZLE = {prefix = PREFIX_SIMD, opcode = 0x0E, inputs = 2, outputs = 1},
|
||||
.I8X16_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x0F, inputs = 1, outputs = 1},
|
||||
.I16X8_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x10, inputs = 1, outputs = 1},
|
||||
.I32X4_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x11, inputs = 1, outputs = 1},
|
||||
.I64X2_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x12, inputs = 1, outputs = 1},
|
||||
.F32X4_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x13, inputs = 1, outputs = 1},
|
||||
.F64X2_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x14, inputs = 1, outputs = 1},
|
||||
.I8X16_EXTRACT_LANE_S = {prefix = PREFIX_SIMD, opcode = 0x15, imm = {.LANE, .NONE}, inputs = 1, outputs = 1},
|
||||
.I8X16_EXTRACT_LANE_U = {prefix = PREFIX_SIMD, opcode = 0x16, imm = {.LANE, .NONE}, inputs = 1, outputs = 1},
|
||||
.I8X16_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x17, imm = {.LANE, .NONE}, inputs = 2, outputs = 1},
|
||||
.I16X8_EXTRACT_LANE_S = {prefix = PREFIX_SIMD, opcode = 0x18, imm = {.LANE, .NONE}, inputs = 1, outputs = 1},
|
||||
.I16X8_EXTRACT_LANE_U = {prefix = PREFIX_SIMD, opcode = 0x19, imm = {.LANE, .NONE}, inputs = 1, outputs = 1},
|
||||
.I16X8_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x1A, imm = {.LANE, .NONE}, inputs = 2, outputs = 1},
|
||||
.I32X4_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x1B, imm = {.LANE, .NONE}, inputs = 1, outputs = 1},
|
||||
.I32X4_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x1C, imm = {.LANE, .NONE}, inputs = 2, outputs = 1},
|
||||
.I64X2_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x1D, imm = {.LANE, .NONE}, inputs = 1, outputs = 1},
|
||||
.I64X2_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x1E, imm = {.LANE, .NONE}, inputs = 2, outputs = 1},
|
||||
.F32X4_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x1F, imm = {.LANE, .NONE}, inputs = 1, outputs = 1},
|
||||
.F32X4_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x20, imm = {.LANE, .NONE}, inputs = 2, outputs = 1},
|
||||
.F64X2_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x21, imm = {.LANE, .NONE}, inputs = 1, outputs = 1},
|
||||
.F64X2_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x22, imm = {.LANE, .NONE}, inputs = 2, outputs = 1},
|
||||
.I8X16_EQ = {prefix = PREFIX_SIMD, opcode = 0x23, inputs = 2, outputs = 1},
|
||||
.I8X16_NE = {prefix = PREFIX_SIMD, opcode = 0x24, inputs = 2, outputs = 1},
|
||||
.I8X16_LT_S = {prefix = PREFIX_SIMD, opcode = 0x25, inputs = 2, outputs = 1},
|
||||
.I8X16_LT_U = {prefix = PREFIX_SIMD, opcode = 0x26, inputs = 2, outputs = 1},
|
||||
.I8X16_GT_S = {prefix = PREFIX_SIMD, opcode = 0x27, inputs = 2, outputs = 1},
|
||||
.I8X16_GT_U = {prefix = PREFIX_SIMD, opcode = 0x28, inputs = 2, outputs = 1},
|
||||
.I8X16_LE_S = {prefix = PREFIX_SIMD, opcode = 0x29, inputs = 2, outputs = 1},
|
||||
.I8X16_LE_U = {prefix = PREFIX_SIMD, opcode = 0x2A, inputs = 2, outputs = 1},
|
||||
.I8X16_GE_S = {prefix = PREFIX_SIMD, opcode = 0x2B, inputs = 2, outputs = 1},
|
||||
.I8X16_GE_U = {prefix = PREFIX_SIMD, opcode = 0x2C, inputs = 2, outputs = 1},
|
||||
.I16X8_EQ = {prefix = PREFIX_SIMD, opcode = 0x2D, inputs = 2, outputs = 1},
|
||||
.I16X8_NE = {prefix = PREFIX_SIMD, opcode = 0x2E, inputs = 2, outputs = 1},
|
||||
.I16X8_LT_S = {prefix = PREFIX_SIMD, opcode = 0x2F, inputs = 2, outputs = 1},
|
||||
.I16X8_LT_U = {prefix = PREFIX_SIMD, opcode = 0x30, inputs = 2, outputs = 1},
|
||||
.I16X8_GT_S = {prefix = PREFIX_SIMD, opcode = 0x31, inputs = 2, outputs = 1},
|
||||
.I16X8_GT_U = {prefix = PREFIX_SIMD, opcode = 0x32, inputs = 2, outputs = 1},
|
||||
.I16X8_LE_S = {prefix = PREFIX_SIMD, opcode = 0x33, inputs = 2, outputs = 1},
|
||||
.I16X8_LE_U = {prefix = PREFIX_SIMD, opcode = 0x34, inputs = 2, outputs = 1},
|
||||
.I16X8_GE_S = {prefix = PREFIX_SIMD, opcode = 0x35, inputs = 2, outputs = 1},
|
||||
.I16X8_GE_U = {prefix = PREFIX_SIMD, opcode = 0x36, inputs = 2, outputs = 1},
|
||||
.I32X4_EQ = {prefix = PREFIX_SIMD, opcode = 0x37, inputs = 2, outputs = 1},
|
||||
.I32X4_NE = {prefix = PREFIX_SIMD, opcode = 0x38, inputs = 2, outputs = 1},
|
||||
.I32X4_LT_S = {prefix = PREFIX_SIMD, opcode = 0x39, inputs = 2, outputs = 1},
|
||||
.I32X4_LT_U = {prefix = PREFIX_SIMD, opcode = 0x3A, inputs = 2, outputs = 1},
|
||||
.I32X4_GT_S = {prefix = PREFIX_SIMD, opcode = 0x3B, inputs = 2, outputs = 1},
|
||||
.I32X4_GT_U = {prefix = PREFIX_SIMD, opcode = 0x3C, inputs = 2, outputs = 1},
|
||||
.I32X4_LE_S = {prefix = PREFIX_SIMD, opcode = 0x3D, inputs = 2, outputs = 1},
|
||||
.I32X4_LE_U = {prefix = PREFIX_SIMD, opcode = 0x3E, inputs = 2, outputs = 1},
|
||||
.I32X4_GE_S = {prefix = PREFIX_SIMD, opcode = 0x3F, inputs = 2, outputs = 1},
|
||||
.I32X4_GE_U = {prefix = PREFIX_SIMD, opcode = 0x40, inputs = 2, outputs = 1},
|
||||
.F32X4_EQ = {prefix = PREFIX_SIMD, opcode = 0x41, inputs = 2, outputs = 1},
|
||||
.F32X4_NE = {prefix = PREFIX_SIMD, opcode = 0x42, inputs = 2, outputs = 1},
|
||||
.F32X4_LT = {prefix = PREFIX_SIMD, opcode = 0x43, inputs = 2, outputs = 1},
|
||||
.F32X4_GT = {prefix = PREFIX_SIMD, opcode = 0x44, inputs = 2, outputs = 1},
|
||||
.F32X4_LE = {prefix = PREFIX_SIMD, opcode = 0x45, inputs = 2, outputs = 1},
|
||||
.F32X4_GE = {prefix = PREFIX_SIMD, opcode = 0x46, inputs = 2, outputs = 1},
|
||||
.F64X2_EQ = {prefix = PREFIX_SIMD, opcode = 0x47, inputs = 2, outputs = 1},
|
||||
.F64X2_NE = {prefix = PREFIX_SIMD, opcode = 0x48, inputs = 2, outputs = 1},
|
||||
.F64X2_LT = {prefix = PREFIX_SIMD, opcode = 0x49, inputs = 2, outputs = 1},
|
||||
.F64X2_GT = {prefix = PREFIX_SIMD, opcode = 0x4A, inputs = 2, outputs = 1},
|
||||
.F64X2_LE = {prefix = PREFIX_SIMD, opcode = 0x4B, inputs = 2, outputs = 1},
|
||||
.F64X2_GE = {prefix = PREFIX_SIMD, opcode = 0x4C, inputs = 2, outputs = 1},
|
||||
.V128_NOT = {prefix = PREFIX_SIMD, opcode = 0x4D, inputs = 1, outputs = 1},
|
||||
.V128_AND = {prefix = PREFIX_SIMD, opcode = 0x4E, inputs = 2, outputs = 1},
|
||||
.V128_ANDNOT = {prefix = PREFIX_SIMD, opcode = 0x4F, inputs = 2, outputs = 1},
|
||||
.V128_OR = {prefix = PREFIX_SIMD, opcode = 0x50, inputs = 2, outputs = 1},
|
||||
.V128_XOR = {prefix = PREFIX_SIMD, opcode = 0x51, inputs = 2, outputs = 1},
|
||||
.V128_BITSELECT = {prefix = PREFIX_SIMD, opcode = 0x52, inputs = 3, outputs = 1},
|
||||
.V128_ANY_TRUE = {prefix = PREFIX_SIMD, opcode = 0x53, inputs = 1, outputs = 1},
|
||||
.V128_LOAD8_LANE = {prefix = PREFIX_SIMD, opcode = 0x54, imm = {.MEMARG, .LANE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.V128_LOAD16_LANE = {prefix = PREFIX_SIMD, opcode = 0x55, imm = {.MEMARG, .LANE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.V128_LOAD32_LANE = {prefix = PREFIX_SIMD, opcode = 0x56, imm = {.MEMARG, .LANE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.V128_LOAD64_LANE = {prefix = PREFIX_SIMD, opcode = 0x57, imm = {.MEMARG, .LANE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.V128_STORE8_LANE = {prefix = PREFIX_SIMD, opcode = 0x58, imm = {.MEMARG, .LANE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.V128_STORE16_LANE = {prefix = PREFIX_SIMD, opcode = 0x59, imm = {.MEMARG, .LANE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.V128_STORE32_LANE = {prefix = PREFIX_SIMD, opcode = 0x5A, imm = {.MEMARG, .LANE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.V128_STORE64_LANE = {prefix = PREFIX_SIMD, opcode = 0x5B, imm = {.MEMARG, .LANE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.V128_LOAD32_ZERO = {prefix = PREFIX_SIMD, opcode = 0x5C, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.V128_LOAD64_ZERO = {prefix = PREFIX_SIMD, opcode = 0x5D, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.F32X4_DEMOTE_F64X2_ZERO = {prefix = PREFIX_SIMD, opcode = 0x5E, inputs = 1, outputs = 1},
|
||||
.F64X2_PROMOTE_LOW_F32X4 = {prefix = PREFIX_SIMD, opcode = 0x5F, inputs = 1, outputs = 1},
|
||||
.I8X16_ABS = {prefix = PREFIX_SIMD, opcode = 0x60, inputs = 1, outputs = 1},
|
||||
.I8X16_NEG = {prefix = PREFIX_SIMD, opcode = 0x61, inputs = 1, outputs = 1},
|
||||
.I8X16_POPCNT = {prefix = PREFIX_SIMD, opcode = 0x62, inputs = 1, outputs = 1},
|
||||
.I8X16_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0x63, inputs = 1, outputs = 1},
|
||||
.I8X16_BITMASK = {prefix = PREFIX_SIMD, opcode = 0x64, inputs = 1, outputs = 1},
|
||||
.I8X16_NARROW_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0x65, inputs = 2, outputs = 1},
|
||||
.I8X16_NARROW_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0x66, inputs = 2, outputs = 1},
|
||||
.F32X4_CEIL = {prefix = PREFIX_SIMD, opcode = 0x67, inputs = 1, outputs = 1},
|
||||
.F32X4_FLOOR = {prefix = PREFIX_SIMD, opcode = 0x68, inputs = 1, outputs = 1},
|
||||
.F32X4_TRUNC = {prefix = PREFIX_SIMD, opcode = 0x69, inputs = 1, outputs = 1},
|
||||
.F32X4_NEAREST = {prefix = PREFIX_SIMD, opcode = 0x6A, inputs = 1, outputs = 1},
|
||||
.I8X16_SHL = {prefix = PREFIX_SIMD, opcode = 0x6B, inputs = 2, outputs = 1},
|
||||
.I8X16_SHR_S = {prefix = PREFIX_SIMD, opcode = 0x6C, inputs = 2, outputs = 1},
|
||||
.I8X16_SHR_U = {prefix = PREFIX_SIMD, opcode = 0x6D, inputs = 2, outputs = 1},
|
||||
.I8X16_ADD = {prefix = PREFIX_SIMD, opcode = 0x6E, inputs = 2, outputs = 1},
|
||||
.I8X16_ADD_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x6F, inputs = 2, outputs = 1},
|
||||
.I8X16_ADD_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x70, inputs = 2, outputs = 1},
|
||||
.I8X16_SUB = {prefix = PREFIX_SIMD, opcode = 0x71, inputs = 2, outputs = 1},
|
||||
.I8X16_SUB_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x72, inputs = 2, outputs = 1},
|
||||
.I8X16_SUB_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x73, inputs = 2, outputs = 1},
|
||||
.F64X2_CEIL = {prefix = PREFIX_SIMD, opcode = 0x74, inputs = 1, outputs = 1},
|
||||
.F64X2_FLOOR = {prefix = PREFIX_SIMD, opcode = 0x75, inputs = 1, outputs = 1},
|
||||
.I8X16_MIN_S = {prefix = PREFIX_SIMD, opcode = 0x76, inputs = 2, outputs = 1},
|
||||
.I8X16_MIN_U = {prefix = PREFIX_SIMD, opcode = 0x77, inputs = 2, outputs = 1},
|
||||
.I8X16_MAX_S = {prefix = PREFIX_SIMD, opcode = 0x78, inputs = 2, outputs = 1},
|
||||
.I8X16_MAX_U = {prefix = PREFIX_SIMD, opcode = 0x79, inputs = 2, outputs = 1},
|
||||
.F64X2_TRUNC = {prefix = PREFIX_SIMD, opcode = 0x7A, inputs = 1, outputs = 1},
|
||||
.I8X16_AVGR_U = {prefix = PREFIX_SIMD, opcode = 0x7B, inputs = 2, outputs = 1},
|
||||
.I16X8_EXTADD_PAIRWISE_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x7C, inputs = 1, outputs = 1},
|
||||
.I16X8_EXTADD_PAIRWISE_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x7D, inputs = 1, outputs = 1},
|
||||
.I32X4_EXTADD_PAIRWISE_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0x7E, inputs = 1, outputs = 1},
|
||||
.I32X4_EXTADD_PAIRWISE_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0x7F, inputs = 1, outputs = 1},
|
||||
.I16X8_ABS = {prefix = PREFIX_SIMD, opcode = 0x80, inputs = 1, outputs = 1},
|
||||
.I16X8_NEG = {prefix = PREFIX_SIMD, opcode = 0x81, inputs = 1, outputs = 1},
|
||||
.I16X8_Q15MULR_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x82, inputs = 2, outputs = 1},
|
||||
.I16X8_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0x83, inputs = 1, outputs = 1},
|
||||
.I16X8_BITMASK = {prefix = PREFIX_SIMD, opcode = 0x84, inputs = 1, outputs = 1},
|
||||
.I16X8_NARROW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0x85, inputs = 2, outputs = 1},
|
||||
.I16X8_NARROW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0x86, inputs = 2, outputs = 1},
|
||||
.I16X8_EXTEND_LOW_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x87, inputs = 1, outputs = 1},
|
||||
.I16X8_EXTEND_HIGH_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x88, inputs = 1, outputs = 1},
|
||||
.I16X8_EXTEND_LOW_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x89, inputs = 1, outputs = 1},
|
||||
.I16X8_EXTEND_HIGH_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x8A, inputs = 1, outputs = 1},
|
||||
.I16X8_SHL = {prefix = PREFIX_SIMD, opcode = 0x8B, inputs = 2, outputs = 1},
|
||||
.I16X8_SHR_S = {prefix = PREFIX_SIMD, opcode = 0x8C, inputs = 2, outputs = 1},
|
||||
.I16X8_SHR_U = {prefix = PREFIX_SIMD, opcode = 0x8D, inputs = 2, outputs = 1},
|
||||
.I16X8_ADD = {prefix = PREFIX_SIMD, opcode = 0x8E, inputs = 2, outputs = 1},
|
||||
.I16X8_ADD_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x8F, inputs = 2, outputs = 1},
|
||||
.I16X8_ADD_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x90, inputs = 2, outputs = 1},
|
||||
.I16X8_SUB = {prefix = PREFIX_SIMD, opcode = 0x91, inputs = 2, outputs = 1},
|
||||
.I16X8_SUB_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x92, inputs = 2, outputs = 1},
|
||||
.I16X8_SUB_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x93, inputs = 2, outputs = 1},
|
||||
.F64X2_NEAREST = {prefix = PREFIX_SIMD, opcode = 0x94, inputs = 1, outputs = 1},
|
||||
.I16X8_MUL = {prefix = PREFIX_SIMD, opcode = 0x95, inputs = 2, outputs = 1},
|
||||
.I16X8_MIN_S = {prefix = PREFIX_SIMD, opcode = 0x96, inputs = 2, outputs = 1},
|
||||
.I16X8_MIN_U = {prefix = PREFIX_SIMD, opcode = 0x97, inputs = 2, outputs = 1},
|
||||
.I16X8_MAX_S = {prefix = PREFIX_SIMD, opcode = 0x98, inputs = 2, outputs = 1},
|
||||
.I16X8_MAX_U = {prefix = PREFIX_SIMD, opcode = 0x99, inputs = 2, outputs = 1},
|
||||
.I16X8_AVGR_U = {prefix = PREFIX_SIMD, opcode = 0x9B, inputs = 2, outputs = 1},
|
||||
.I16X8_EXTMUL_LOW_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x9C, inputs = 2, outputs = 1},
|
||||
.I16X8_EXTMUL_HIGH_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x9D, inputs = 2, outputs = 1},
|
||||
.I16X8_EXTMUL_LOW_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x9E, inputs = 2, outputs = 1},
|
||||
.I16X8_EXTMUL_HIGH_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x9F, inputs = 2, outputs = 1},
|
||||
.I32X4_ABS = {prefix = PREFIX_SIMD, opcode = 0xA0, inputs = 1, outputs = 1},
|
||||
.I32X4_NEG = {prefix = PREFIX_SIMD, opcode = 0xA1, inputs = 1, outputs = 1},
|
||||
.I32X4_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0xA3, inputs = 1, outputs = 1},
|
||||
.I32X4_BITMASK = {prefix = PREFIX_SIMD, opcode = 0xA4, inputs = 1, outputs = 1},
|
||||
.I32X4_EXTEND_LOW_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xA7, inputs = 1, outputs = 1},
|
||||
.I32X4_EXTEND_HIGH_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xA8, inputs = 1, outputs = 1},
|
||||
.I32X4_EXTEND_LOW_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xA9, inputs = 1, outputs = 1},
|
||||
.I32X4_EXTEND_HIGH_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xAA, inputs = 1, outputs = 1},
|
||||
.I32X4_SHL = {prefix = PREFIX_SIMD, opcode = 0xAB, inputs = 2, outputs = 1},
|
||||
.I32X4_SHR_S = {prefix = PREFIX_SIMD, opcode = 0xAC, inputs = 2, outputs = 1},
|
||||
.I32X4_SHR_U = {prefix = PREFIX_SIMD, opcode = 0xAD, inputs = 2, outputs = 1},
|
||||
.I32X4_ADD = {prefix = PREFIX_SIMD, opcode = 0xAE, inputs = 2, outputs = 1},
|
||||
.I32X4_SUB = {prefix = PREFIX_SIMD, opcode = 0xB1, inputs = 2, outputs = 1},
|
||||
.I32X4_MUL = {prefix = PREFIX_SIMD, opcode = 0xB5, inputs = 2, outputs = 1},
|
||||
.I32X4_MIN_S = {prefix = PREFIX_SIMD, opcode = 0xB6, inputs = 2, outputs = 1},
|
||||
.I32X4_MIN_U = {prefix = PREFIX_SIMD, opcode = 0xB7, inputs = 2, outputs = 1},
|
||||
.I32X4_MAX_S = {prefix = PREFIX_SIMD, opcode = 0xB8, inputs = 2, outputs = 1},
|
||||
.I32X4_MAX_U = {prefix = PREFIX_SIMD, opcode = 0xB9, inputs = 2, outputs = 1},
|
||||
.I32X4_DOT_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xBA, inputs = 2, outputs = 1},
|
||||
.I32X4_EXTMUL_LOW_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xBC, inputs = 2, outputs = 1},
|
||||
.I32X4_EXTMUL_HIGH_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xBD, inputs = 2, outputs = 1},
|
||||
.I32X4_EXTMUL_LOW_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xBE, inputs = 2, outputs = 1},
|
||||
.I32X4_EXTMUL_HIGH_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xBF, inputs = 2, outputs = 1},
|
||||
.I64X2_ABS = {prefix = PREFIX_SIMD, opcode = 0xC0, inputs = 1, outputs = 1},
|
||||
.I64X2_NEG = {prefix = PREFIX_SIMD, opcode = 0xC1, inputs = 1, outputs = 1},
|
||||
.I64X2_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0xC3, inputs = 1, outputs = 1},
|
||||
.I64X2_BITMASK = {prefix = PREFIX_SIMD, opcode = 0xC4, inputs = 1, outputs = 1},
|
||||
.I64X2_EXTEND_LOW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xC7, inputs = 1, outputs = 1},
|
||||
.I64X2_EXTEND_HIGH_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xC8, inputs = 1, outputs = 1},
|
||||
.I64X2_EXTEND_LOW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xC9, inputs = 1, outputs = 1},
|
||||
.I64X2_EXTEND_HIGH_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xCA, inputs = 1, outputs = 1},
|
||||
.I64X2_SHL = {prefix = PREFIX_SIMD, opcode = 0xCB, inputs = 2, outputs = 1},
|
||||
.I64X2_SHR_S = {prefix = PREFIX_SIMD, opcode = 0xCC, inputs = 2, outputs = 1},
|
||||
.I64X2_SHR_U = {prefix = PREFIX_SIMD, opcode = 0xCD, inputs = 2, outputs = 1},
|
||||
.I64X2_ADD = {prefix = PREFIX_SIMD, opcode = 0xCE, inputs = 2, outputs = 1},
|
||||
.I64X2_SUB = {prefix = PREFIX_SIMD, opcode = 0xD1, inputs = 2, outputs = 1},
|
||||
.I64X2_MUL = {prefix = PREFIX_SIMD, opcode = 0xD5, inputs = 2, outputs = 1},
|
||||
.I64X2_EQ = {prefix = PREFIX_SIMD, opcode = 0xD6, inputs = 2, outputs = 1},
|
||||
.I64X2_NE = {prefix = PREFIX_SIMD, opcode = 0xD7, inputs = 2, outputs = 1},
|
||||
.I64X2_LT_S = {prefix = PREFIX_SIMD, opcode = 0xD8, inputs = 2, outputs = 1},
|
||||
.I64X2_GT_S = {prefix = PREFIX_SIMD, opcode = 0xD9, inputs = 2, outputs = 1},
|
||||
.I64X2_LE_S = {prefix = PREFIX_SIMD, opcode = 0xDA, inputs = 2, outputs = 1},
|
||||
.I64X2_GE_S = {prefix = PREFIX_SIMD, opcode = 0xDB, inputs = 2, outputs = 1},
|
||||
.I64X2_EXTMUL_LOW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xDC, inputs = 2, outputs = 1},
|
||||
.I64X2_EXTMUL_HIGH_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xDD, inputs = 2, outputs = 1},
|
||||
.I64X2_EXTMUL_LOW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xDE, inputs = 2, outputs = 1},
|
||||
.I64X2_EXTMUL_HIGH_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xDF, inputs = 2, outputs = 1},
|
||||
.F32X4_ABS = {prefix = PREFIX_SIMD, opcode = 0xE0, inputs = 1, outputs = 1},
|
||||
.F32X4_NEG = {prefix = PREFIX_SIMD, opcode = 0xE1, inputs = 1, outputs = 1},
|
||||
.F32X4_SQRT = {prefix = PREFIX_SIMD, opcode = 0xE3, inputs = 1, outputs = 1},
|
||||
.F32X4_ADD = {prefix = PREFIX_SIMD, opcode = 0xE4, inputs = 2, outputs = 1},
|
||||
.F32X4_SUB = {prefix = PREFIX_SIMD, opcode = 0xE5, inputs = 2, outputs = 1},
|
||||
.F32X4_MUL = {prefix = PREFIX_SIMD, opcode = 0xE6, inputs = 2, outputs = 1},
|
||||
.F32X4_DIV = {prefix = PREFIX_SIMD, opcode = 0xE7, inputs = 2, outputs = 1},
|
||||
.F32X4_MIN = {prefix = PREFIX_SIMD, opcode = 0xE8, inputs = 2, outputs = 1},
|
||||
.F32X4_MAX = {prefix = PREFIX_SIMD, opcode = 0xE9, inputs = 2, outputs = 1},
|
||||
.F32X4_PMIN = {prefix = PREFIX_SIMD, opcode = 0xEA, inputs = 2, outputs = 1},
|
||||
.F32X4_PMAX = {prefix = PREFIX_SIMD, opcode = 0xEB, inputs = 2, outputs = 1},
|
||||
.F64X2_ABS = {prefix = PREFIX_SIMD, opcode = 0xEC, inputs = 1, outputs = 1},
|
||||
.F64X2_NEG = {prefix = PREFIX_SIMD, opcode = 0xED, inputs = 1, outputs = 1},
|
||||
.F64X2_SQRT = {prefix = PREFIX_SIMD, opcode = 0xEF, inputs = 1, outputs = 1},
|
||||
.F64X2_ADD = {prefix = PREFIX_SIMD, opcode = 0xF0, inputs = 2, outputs = 1},
|
||||
.F64X2_SUB = {prefix = PREFIX_SIMD, opcode = 0xF1, inputs = 2, outputs = 1},
|
||||
.F64X2_MUL = {prefix = PREFIX_SIMD, opcode = 0xF2, inputs = 2, outputs = 1},
|
||||
.F64X2_DIV = {prefix = PREFIX_SIMD, opcode = 0xF3, inputs = 2, outputs = 1},
|
||||
.F64X2_MIN = {prefix = PREFIX_SIMD, opcode = 0xF4, inputs = 2, outputs = 1},
|
||||
.F64X2_MAX = {prefix = PREFIX_SIMD, opcode = 0xF5, inputs = 2, outputs = 1},
|
||||
.F64X2_PMIN = {prefix = PREFIX_SIMD, opcode = 0xF6, inputs = 2, outputs = 1},
|
||||
.F64X2_PMAX = {prefix = PREFIX_SIMD, opcode = 0xF7, inputs = 2, outputs = 1},
|
||||
.I32X4_TRUNC_SAT_F32X4_S = {prefix = PREFIX_SIMD, opcode = 0xF8, inputs = 1, outputs = 1},
|
||||
.I32X4_TRUNC_SAT_F32X4_U = {prefix = PREFIX_SIMD, opcode = 0xF9, inputs = 1, outputs = 1},
|
||||
.F32X4_CONVERT_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xFA, inputs = 1, outputs = 1},
|
||||
.F32X4_CONVERT_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xFB, inputs = 1, outputs = 1},
|
||||
.I32X4_TRUNC_SAT_F64X2_S_ZERO = {prefix = PREFIX_SIMD, opcode = 0xFC, inputs = 1, outputs = 1},
|
||||
.I32X4_TRUNC_SAT_F64X2_U_ZERO = {prefix = PREFIX_SIMD, opcode = 0xFD, inputs = 1, outputs = 1},
|
||||
.F64X2_CONVERT_LOW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xFE, inputs = 1, outputs = 1},
|
||||
.F64X2_CONVERT_LOW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xFF, inputs = 1, outputs = 1},
|
||||
.I8X16_RELAXED_SWIZZLE = {prefix = PREFIX_SIMD, opcode = 0x100, inputs = 2, outputs = 1},
|
||||
.I32X4_RELAXED_TRUNC_F32X4_S = {prefix = PREFIX_SIMD, opcode = 0x101, inputs = 1, outputs = 1},
|
||||
.I32X4_RELAXED_TRUNC_F32X4_U = {prefix = PREFIX_SIMD, opcode = 0x102, inputs = 1, outputs = 1},
|
||||
.I32X4_RELAXED_TRUNC_F64X2_S_ZERO = {prefix = PREFIX_SIMD, opcode = 0x103, inputs = 1, outputs = 1},
|
||||
.I32X4_RELAXED_TRUNC_F64X2_U_ZERO = {prefix = PREFIX_SIMD, opcode = 0x104, inputs = 1, outputs = 1},
|
||||
.F32X4_RELAXED_MADD = {prefix = PREFIX_SIMD, opcode = 0x105, inputs = 3, outputs = 1},
|
||||
.F32X4_RELAXED_NMADD = {prefix = PREFIX_SIMD, opcode = 0x106, inputs = 3, outputs = 1},
|
||||
.F64X2_RELAXED_MADD = {prefix = PREFIX_SIMD, opcode = 0x107, inputs = 3, outputs = 1},
|
||||
.F64X2_RELAXED_NMADD = {prefix = PREFIX_SIMD, opcode = 0x108, inputs = 3, outputs = 1},
|
||||
.I8X16_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x109, inputs = 3, outputs = 1},
|
||||
.I16X8_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x10A, inputs = 3, outputs = 1},
|
||||
.I32X4_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x10B, inputs = 3, outputs = 1},
|
||||
.I64X2_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x10C, inputs = 3, outputs = 1},
|
||||
.F32X4_RELAXED_MIN = {prefix = PREFIX_SIMD, opcode = 0x10D, inputs = 2, outputs = 1},
|
||||
.F32X4_RELAXED_MAX = {prefix = PREFIX_SIMD, opcode = 0x10E, inputs = 2, outputs = 1},
|
||||
.F64X2_RELAXED_MIN = {prefix = PREFIX_SIMD, opcode = 0x10F, inputs = 2, outputs = 1},
|
||||
.F64X2_RELAXED_MAX = {prefix = PREFIX_SIMD, opcode = 0x110, inputs = 2, outputs = 1},
|
||||
.I16X8_RELAXED_Q15MULR_S = {prefix = PREFIX_SIMD, opcode = 0x111, inputs = 2, outputs = 1},
|
||||
.I16X8_RELAXED_DOT_I8X16_I7X16_S = {prefix = PREFIX_SIMD, opcode = 0x112, inputs = 2, outputs = 1},
|
||||
.I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S = {prefix = PREFIX_SIMD, opcode = 0x113, inputs = 3, outputs = 1},
|
||||
|
||||
// ------------------------------------------ 0xFE threads / atomics prefix
|
||||
.MEMORY_ATOMIC_NOTIFY = {prefix = PREFIX_ATOM, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.MEMORY_ATOMIC_WAIT32 = {prefix = PREFIX_ATOM, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.MEMORY_ATOMIC_WAIT64 = {prefix = PREFIX_ATOM, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.ATOMIC_FENCE = {prefix = PREFIX_ATOM, opcode = 0x03, imm = {.ZERO_BYTE, .NONE}},
|
||||
.I32_ATOMIC_LOAD = {prefix = PREFIX_ATOM, opcode = 0x10, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_LOAD = {prefix = PREFIX_ATOM, opcode = 0x11, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_LOAD8_U = {prefix = PREFIX_ATOM, opcode = 0x12, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_LOAD16_U = {prefix = PREFIX_ATOM, opcode = 0x13, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_LOAD8_U = {prefix = PREFIX_ATOM, opcode = 0x14, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_LOAD16_U = {prefix = PREFIX_ATOM, opcode = 0x15, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_LOAD32_U = {prefix = PREFIX_ATOM, opcode = 0x16, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_STORE = {prefix = PREFIX_ATOM, opcode = 0x17, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_STORE = {prefix = PREFIX_ATOM, opcode = 0x18, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_STORE8 = {prefix = PREFIX_ATOM, opcode = 0x19, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_STORE16 = {prefix = PREFIX_ATOM, opcode = 0x1A, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_STORE8 = {prefix = PREFIX_ATOM, opcode = 0x1B, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_STORE16 = {prefix = PREFIX_ATOM, opcode = 0x1C, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_STORE32 = {prefix = PREFIX_ATOM, opcode = 0x1D, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW_ADD = {prefix = PREFIX_ATOM, opcode = 0x1E, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW_ADD = {prefix = PREFIX_ATOM, opcode = 0x1F, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW8_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x20, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW16_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x21, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW8_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x22, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW16_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x23, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW32_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x24, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW_SUB = {prefix = PREFIX_ATOM, opcode = 0x25, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW_SUB = {prefix = PREFIX_ATOM, opcode = 0x26, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW8_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x27, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW16_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW8_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW16_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW32_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW_AND = {prefix = PREFIX_ATOM, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW_AND = {prefix = PREFIX_ATOM, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW8_AND_U = {prefix = PREFIX_ATOM, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW16_AND_U = {prefix = PREFIX_ATOM, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW8_AND_U = {prefix = PREFIX_ATOM, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW16_AND_U = {prefix = PREFIX_ATOM, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW32_AND_U = {prefix = PREFIX_ATOM, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW_OR = {prefix = PREFIX_ATOM, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW_OR = {prefix = PREFIX_ATOM, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW8_OR_U = {prefix = PREFIX_ATOM, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW16_OR_U = {prefix = PREFIX_ATOM, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW8_OR_U = {prefix = PREFIX_ATOM, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW16_OR_U = {prefix = PREFIX_ATOM, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW32_OR_U = {prefix = PREFIX_ATOM, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW_XOR = {prefix = PREFIX_ATOM, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW_XOR = {prefix = PREFIX_ATOM, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW8_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW16_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW8_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW16_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3F, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW32_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x40, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW_XCHG = {prefix = PREFIX_ATOM, opcode = 0x41, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW_XCHG = {prefix = PREFIX_ATOM, opcode = 0x42, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW8_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x43, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW16_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x44, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW8_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x45, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW16_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x46, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW32_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x47, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW_CMPXCHG = {prefix = PREFIX_ATOM, opcode = 0x48, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW_CMPXCHG = {prefix = PREFIX_ATOM, opcode = 0x49, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW8_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4A, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I32_ATOMIC_RMW16_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4B, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW8_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4C, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW16_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4D, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.I64_ATOMIC_RMW32_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4E, imm = {.MEMARG, .NONE}, flags = MEM},
|
||||
.MEMORY_ATOMIC_NOTIFY = {prefix = PREFIX_ATOM, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.MEMORY_ATOMIC_WAIT32 = {prefix = PREFIX_ATOM, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 3, outputs = 1},
|
||||
.MEMORY_ATOMIC_WAIT64 = {prefix = PREFIX_ATOM, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 3, outputs = 1},
|
||||
.ATOMIC_FENCE = {prefix = PREFIX_ATOM, opcode = 0x03, imm = {.ZERO_BYTE, .NONE}, inputs = 0, outputs = 0},
|
||||
.I32_ATOMIC_LOAD = {prefix = PREFIX_ATOM, opcode = 0x10, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.I64_ATOMIC_LOAD = {prefix = PREFIX_ATOM, opcode = 0x11, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.I32_ATOMIC_LOAD8_U = {prefix = PREFIX_ATOM, opcode = 0x12, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.I32_ATOMIC_LOAD16_U = {prefix = PREFIX_ATOM, opcode = 0x13, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.I64_ATOMIC_LOAD8_U = {prefix = PREFIX_ATOM, opcode = 0x14, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.I64_ATOMIC_LOAD16_U = {prefix = PREFIX_ATOM, opcode = 0x15, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.I64_ATOMIC_LOAD32_U = {prefix = PREFIX_ATOM, opcode = 0x16, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 1, outputs = 1},
|
||||
.I32_ATOMIC_STORE = {prefix = PREFIX_ATOM, opcode = 0x17, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.I64_ATOMIC_STORE = {prefix = PREFIX_ATOM, opcode = 0x18, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.I32_ATOMIC_STORE8 = {prefix = PREFIX_ATOM, opcode = 0x19, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.I32_ATOMIC_STORE16 = {prefix = PREFIX_ATOM, opcode = 0x1A, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.I64_ATOMIC_STORE8 = {prefix = PREFIX_ATOM, opcode = 0x1B, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.I64_ATOMIC_STORE16 = {prefix = PREFIX_ATOM, opcode = 0x1C, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.I64_ATOMIC_STORE32 = {prefix = PREFIX_ATOM, opcode = 0x1D, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 0},
|
||||
.I32_ATOMIC_RMW_ADD = {prefix = PREFIX_ATOM, opcode = 0x1E, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW_ADD = {prefix = PREFIX_ATOM, opcode = 0x1F, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW8_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x20, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW16_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x21, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW8_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x22, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW16_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x23, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW32_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x24, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW_SUB = {prefix = PREFIX_ATOM, opcode = 0x25, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW_SUB = {prefix = PREFIX_ATOM, opcode = 0x26, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW8_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x27, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW16_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW8_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW16_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW32_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW_AND = {prefix = PREFIX_ATOM, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW_AND = {prefix = PREFIX_ATOM, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW8_AND_U = {prefix = PREFIX_ATOM, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW16_AND_U = {prefix = PREFIX_ATOM, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW8_AND_U = {prefix = PREFIX_ATOM, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW16_AND_U = {prefix = PREFIX_ATOM, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW32_AND_U = {prefix = PREFIX_ATOM, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW_OR = {prefix = PREFIX_ATOM, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW_OR = {prefix = PREFIX_ATOM, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW8_OR_U = {prefix = PREFIX_ATOM, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW16_OR_U = {prefix = PREFIX_ATOM, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW8_OR_U = {prefix = PREFIX_ATOM, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW16_OR_U = {prefix = PREFIX_ATOM, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW32_OR_U = {prefix = PREFIX_ATOM, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW_XOR = {prefix = PREFIX_ATOM, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW_XOR = {prefix = PREFIX_ATOM, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW8_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW16_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW8_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW16_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3F, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW32_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x40, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW_XCHG = {prefix = PREFIX_ATOM, opcode = 0x41, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW_XCHG = {prefix = PREFIX_ATOM, opcode = 0x42, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW8_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x43, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW16_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x44, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW8_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x45, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW16_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x46, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I64_ATOMIC_RMW32_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x47, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 2, outputs = 1},
|
||||
.I32_ATOMIC_RMW_CMPXCHG = {prefix = PREFIX_ATOM, opcode = 0x48, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 3, outputs = 1},
|
||||
.I64_ATOMIC_RMW_CMPXCHG = {prefix = PREFIX_ATOM, opcode = 0x49, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 3, outputs = 1},
|
||||
.I32_ATOMIC_RMW8_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4A, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 3, outputs = 1},
|
||||
.I32_ATOMIC_RMW16_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4B, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 3, outputs = 1},
|
||||
.I64_ATOMIC_RMW8_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4C, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 3, outputs = 1},
|
||||
.I64_ATOMIC_RMW16_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4D, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 3, outputs = 1},
|
||||
.I64_ATOMIC_RMW32_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4E, imm = {.MEMARG, .NONE}, flags = MEM, inputs = 3, outputs = 1},
|
||||
}
|
||||
|
||||
// Per-mnemonic encode form. Returns a pointer into the rodata table.
|
||||
|
||||
@@ -65,8 +65,19 @@ Encoding :: struct #packed {
|
||||
opcode: u16, // 2 -- primary opcode, or sub-opcode within a prefix group (SIMD reaches 0x113)
|
||||
imm: [2]Imm_Kind, // 2 -- immediate layout, walked in order
|
||||
flags: Encoding_Flags, // 1
|
||||
inputs: i8, // 1 -- stack operands consumed (the arity in); -1 when it varies
|
||||
outputs: i8, // 1 -- stack results produced (the arity out); -1 when it varies
|
||||
}
|
||||
#assert(size_of(Encoding) == 8)
|
||||
#assert(size_of(Encoding) == 10)
|
||||
|
||||
// `inputs`/`outputs` give the fixed stack arity of an instruction: how many
|
||||
// values it pops and how many it pushes. They are -1 when the count is not a
|
||||
// constant of the opcode -- i.e. it depends on a type/blocktype immediate or on
|
||||
// the surrounding control frame. That covers `call`/`call_indirect` (the callee
|
||||
// or referenced signature), the structured control ops `block`/`loop`/`if`
|
||||
// (their blocktype) plus `else`/`end`, the branches `br`/`br_if`/`br_table` and
|
||||
// `return` (the target/result types, and stack-polymorphism), and the
|
||||
// stack-polymorphic `unreachable`. Everything else is a fixed (inputs, outputs).
|
||||
|
||||
// =============================================================================
|
||||
// LEB128 + little-endian primitives (shared by encoder and decoder)
|
||||
|
||||
@@ -28,6 +28,7 @@ Mnemonic :: enum u16 {
|
||||
BLOCK, LOOP, IF, ELSE, END,
|
||||
BR, BR_IF, BR_TABLE,
|
||||
RETURN, CALL, CALL_INDIRECT,
|
||||
RETURN_CALL, RETURN_CALL_INDIRECT,
|
||||
|
||||
// -------------------------------------------------------------- parametric
|
||||
DROP, SELECT,
|
||||
@@ -226,6 +227,7 @@ MNEMONIC_NAMES := [Mnemonic]string{
|
||||
.BLOCK = "block", .LOOP = "loop", .IF = "if", .ELSE = "else", .END = "end",
|
||||
.BR = "br", .BR_IF = "br_if", .BR_TABLE = "br_table",
|
||||
.RETURN = "return", .CALL = "call", .CALL_INDIRECT = "call_indirect",
|
||||
.RETURN_CALL = "return_call", .RETURN_CALL_INDIRECT = "return_call_indirect",
|
||||
|
||||
.DROP = "drop", .SELECT = "select",
|
||||
|
||||
|
||||
@@ -95,6 +95,9 @@ sbprint :: proc(
|
||||
strings.write_byte(sb, ' ')
|
||||
strings.write_u64(sb, u64(u32(bb)))
|
||||
}
|
||||
|
||||
case .CALL_INDIRECT:
|
||||
|
||||
case:
|
||||
for slot in 0..<inst.operand_count {
|
||||
strings.write_byte(sb, ' ')
|
||||
@@ -273,12 +276,16 @@ write_operand :: proc(
|
||||
}
|
||||
|
||||
case .MEMARG:
|
||||
// WAT prints non-trivial memargs as `align=N offset=N`
|
||||
// WAT prints non-trivial memargs as `offset=N align=N`
|
||||
// omitting either when it is the natural default is a refinement.
|
||||
strings.write_string(sb, "align=")
|
||||
strings.write_u64(sb, u64(op.memarg.align))
|
||||
strings.write_string(sb, " offset=")
|
||||
strings.write_u64(sb, u64(op.memarg.offset))
|
||||
if op.memarg.offset != 0 {
|
||||
strings.write_string(sb, "offset=")
|
||||
strings.write_u64(sb, u64(op.memarg.offset))
|
||||
}
|
||||
if op.memarg.align != 0 {
|
||||
strings.write_string(sb, " align=")
|
||||
strings.write_u64(sb, u64(op.memarg.align))
|
||||
}
|
||||
|
||||
case .BLOCK_TYPE:
|
||||
write_block_type(sb, op.immediate)
|
||||
|
||||
Reference in New Issue
Block a user