Merge pull request #4032 from Feoramund/fix-intrinsic-wording

Fix SIMD intrinsics wording
This commit is contained in:
gingerBill
2024-08-06 20:13:10 +01:00
committed by GitHub
2 changed files with 6 additions and 6 deletions

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@@ -303,11 +303,11 @@ simd_nearest :: proc(a: #simd[N]any_float) -> #simd[N]any_float ---
simd_to_bits :: proc(v: #simd[N]T) -> #simd[N]Integer where size_of(T) == size_of(Integer), type_is_unsigned(Integer) ---
// equivalent a swizzle with descending indices, e.g. reserve(a, 3, 2, 1, 0)
simd_reverse :: proc(a: #simd[N]T) -> #simd[N]T ---
// equivalent to a swizzle with descending indices, e.g. reserve(a, 3, 2, 1, 0)
simd_lanes_reverse :: proc(a: #simd[N]T) -> #simd[N]T ---
simd_rotate_left :: proc(a: #simd[N]T, $offset: int) -> #simd[N]T ---
simd_rotate_right :: proc(a: #simd[N]T, $offset: int) -> #simd[N]T ---
simd_lanes_rotate_left :: proc(a: #simd[N]T, $offset: int) -> #simd[N]T ---
simd_lanes_rotate_right :: proc(a: #simd[N]T, $offset: int) -> #simd[N]T ---
// Checks if the current target supports the given target features.
//

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@@ -1532,8 +1532,8 @@ gb_internal lbValue lb_build_builtin_simd_proc(lbProcedure *p, Ast *expr, TypeAn
{
char const *name = nullptr;
switch (builtin_id) {
case BuiltinProc_simd_reduce_any: name = "llvm.vector.reduce.and"; break;
case BuiltinProc_simd_reduce_all: name = "llvm.vector.reduce.or"; break;
case BuiltinProc_simd_reduce_any: name = "llvm.vector.reduce.or"; break;
case BuiltinProc_simd_reduce_all: name = "llvm.vector.reduce.and"; break;
}
LLVMTypeRef types[1] = { lb_type(p->module, arg0.type) };