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Add asm_tables_riscv.cpp
This commit is contained in:
gingerBill
716
src/asm_tables_riscv.cpp
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716
src/asm_tables_riscv.cpp
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@@ -0,0 +1,716 @@
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// =============================================================================
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// GENERATED FILE - DO NOT EDIT
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// =============================================================================
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//
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// Produces a C++ equivalent of the encoding table from core:rexcode written in Odin
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// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file
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// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin
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// odin run tablegen/cpp-compiler # Stage C: typed Odin literals -> C++ literals
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//
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struct Asm_riscv {
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enum Mnemonic : u16 {
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M_INVALID, M_LUI, M_AUIPC, M_JAL, M_JALR, M_BEQ, M_BNE, M_BLT, M_BGE, M_BLTU, M_BGEU, M_LB, M_LH, M_LW, M_LBU, M_LHU,
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M_SB, M_SH, M_SW, M_LWU, M_LD, M_SD, M_ADDI, M_SLTI, M_SLTIU, M_XORI, M_ORI, M_ANDI, M_SLLI, M_SRLI, M_SRAI, M_ADDIW,
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M_SLLIW, M_SRLIW, M_SRAIW, M_ADD, M_SUB, M_SLL, M_SLT, M_SLTU, M_XOR, M_SRL, M_SRA, M_OR, M_AND, M_ADDW, M_SUBW, M_SLLW,
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M_SRLW, M_SRAW, M_FENCE, M_FENCE_I, M_ECALL, M_EBREAK, M_CSRRW, M_CSRRS, M_CSRRC, M_CSRRWI, M_CSRRSI, M_CSRRCI, M_MUL, M_MULH, M_MULHSU, M_MULHU,
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M_DIV, M_DIVU, M_REM, M_REMU, M_MULW, M_DIVW, M_DIVUW, M_REMW, M_REMUW, M_LR_W, M_SC_W, M_AMOSWAP_W, M_AMOADD_W, M_AMOXOR_W, M_AMOAND_W, M_AMOOR_W,
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M_AMOMIN_W, M_AMOMAX_W, M_AMOMINU_W, M_AMOMAXU_W, M_LR_D, M_SC_D, M_AMOSWAP_D, M_AMOADD_D, M_AMOXOR_D, M_AMOAND_D, M_AMOOR_D, M_AMOMIN_D, M_AMOMAX_D, M_AMOMINU_D, M_AMOMAXU_D, M_FLW,
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M_FSW, M_FMADD_S, M_FMSUB_S, M_FNMSUB_S, M_FNMADD_S, M_FADD_S, M_FSUB_S, M_FMUL_S, M_FDIV_S, M_FSQRT_S, M_FSGNJ_S, M_FSGNJN_S, M_FSGNJX_S, M_FMIN_S, M_FMAX_S, M_FCVT_W_S,
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M_FCVT_WU_S, M_FMV_X_W, M_FEQ_S, M_FLT_S, M_FLE_S, M_FCLASS_S, M_FCVT_S_W, M_FCVT_S_WU, M_FMV_W_X, M_FCVT_L_S, M_FCVT_LU_S, M_FCVT_S_L, M_FCVT_S_LU, M_FLD, M_FSD, M_FMADD_D,
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M_FMSUB_D, M_FNMSUB_D, M_FNMADD_D, M_FADD_D, M_FSUB_D, M_FMUL_D, M_FDIV_D, M_FSQRT_D, M_FSGNJ_D, M_FSGNJN_D, M_FSGNJX_D, M_FMIN_D, M_FMAX_D, M_FCVT_S_D, M_FCVT_D_S, M_FEQ_D,
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M_FLT_D, M_FLE_D, M_FCLASS_D, M_FCVT_W_D, M_FCVT_WU_D, M_FCVT_D_W, M_FCVT_D_WU, M_FCVT_L_D, M_FCVT_LU_D, M_FCVT_D_L, M_FCVT_D_LU, M_FMV_X_D, M_FMV_D_X, M_C_NOP, M_C_EBREAK, M_C_ADDI4SPN,
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M_C_LW, M_C_LD, M_C_SW, M_C_SD, M_C_FLW, M_C_FSW, M_C_FLD, M_C_FSD, M_C_ADDI, M_C_ADDIW, M_C_LI, M_C_LUI, M_C_ADDI16SP, M_C_SRLI, M_C_SRAI, M_C_ANDI,
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M_C_SUB, M_C_XOR, M_C_OR, M_C_AND, M_C_SUBW, M_C_ADDW, M_C_J, M_C_JAL, M_C_BEQZ, M_C_BNEZ, M_C_SLLI, M_C_LWSP, M_C_LDSP, M_C_SWSP, M_C_SDSP, M_C_FLDSP,
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M_C_FSDSP, M_C_JR, M_C_JALR, M_C_MV, M_C_ADD, M_C_FLWSP, M_C_FSWSP,
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MNEMONIC_COUNT
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};
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static String const mnemonic_strings[MNEMONIC_COUNT];
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enum Prefix : u8 {
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PREFIX_INVALID,
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PREFIX_COUNT
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};
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enum PrefixKind : u8 { PrefixKind_None };
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static const u16 REG_CLASS_NONE = 0x000;
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static const u16 REG_CLASS_GPR64 = 0x100;
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static const u16 REG_CLASS_GPR32 = 0x200;
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static const u16 REG_CLASS_GPR16 = 0x300;
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static const u16 REG_CLASS_GPR8 = 0x400;
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static const u16 REG_CLASS_GPR8H = 0x500; // AH, CH, DH, BH - legacy high byte regs
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static const u16 REG_CLASS_XMM = 0x600;
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static const u16 REG_CLASS_YMM = 0x700;
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static const u16 REG_CLASS_ZMM = 0x800;
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static const u16 REG_CLASS_K = 0x900; // opmask
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static const u16 REG_CLASS_SEG = 0xA00; // segment
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static const u16 REG_CLASS_CR = 0xB00; // control
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static const u16 REG_CLASS_DR = 0xC00; // debug
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static const u16 REG_CLASS_BND = 0xD00; // bound
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static const u16 REG_CLASS_MM = 0xE00; // MMX
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static const u16 REG_CLASS_ST = 0xF00; // x87 FPU
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enum Register : u16 {
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REG_INVALID, REG_ZERO, REG_RA, REG_SP, REG_GP, REG_TP, REG_T0, REG_T1, REG_T2, REG_S0, REG_S1, REG_A0, REG_A1, REG_A2, REG_A3, REG_A4,
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REG_A5, REG_A6, REG_A7, REG_S2, REG_S3, REG_S4, REG_S5, REG_S6, REG_S7, REG_S8, REG_S9, REG_S10, REG_S11, REG_T3, REG_T4, REG_T5,
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REG_T6, REG_FT0, REG_FT1, REG_FT2, REG_FT3, REG_FT4, REG_FT5, REG_FT6, REG_FT7, REG_FS0, REG_FS1, REG_FA0, REG_FA1, REG_FA2, REG_FA3, REG_FA4,
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REG_FA5, REG_FA6, REG_FA7, REG_FS2, REG_FS3, REG_FS4, REG_FS5, REG_FS6, REG_FS7, REG_FS8, REG_FS9, REG_FS10, REG_FS11, REG_FT8, REG_FT9, REG_FT10,
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REG_FT11,
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REG_COUNT
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};
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enum ClobberFFlags : u8 {
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ClobberFFlag_NV = 1<<0, // invalid operation
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ClobberFFlag_DZ = 1<<1, // divide by zero
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ClobberFFlag_OF = 1<<2, // overflow
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ClobberFFlag_UF = 1<<3, // underflow
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ClobberFFlag_NX = 1<<4, // inexact
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};
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enum ClobberRegs : u8 {
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ClobberReg_RA = 1<<0, // x1, implicit link on C.JAL / C.JALR
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ClobberReg_SP = 1<<1, // x2, implicit base on the *SP compressed forms
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};
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static u8 const CLOBBER_REGS_NAMED = ClobberReg_RA|ClobberReg_SP;
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enum SideEffectFlags : u8 {
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SideEffectFlag_CONTROL = 1<<0, // writes pc: branches, jumps, and trap redirects
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SideEffectFlag_TRAP = 1<<1, // synchronous environment trap (ECALL / EBREAK)
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SideEffectFlag_FENCE = 1<<2, // explicit memory-ordering barrier (FENCE)
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SideEffectFlag_IFENCE = 1<<3, // instruction-fetch synchronization (FENCE.I)
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SideEffectFlag_ATOMIC = 1<<4, // indivisible memory RMW (AMO*, and the LR/SC pair)
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SideEffectFlag_RESERVATION = 1<<5, // sets or tests an LR/SC reservation
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};
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enum OperandSet : u8 {
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OperandSet_OP0 = 1<<0,
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OperandSet_OP1 = 1<<1,
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OperandSet_OP2 = 1<<2,
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OperandSet_OP3 = 1<<3,
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};
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u16 clobber_bit_for_reg_name(String const &pin) {
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static const struct { String name; u16 bit; } table[] = {
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{str_lit("ra"), ClobberReg_RA},
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{str_lit("sp"), ClobberReg_SP},
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{str_lit("x1"), ClobberReg_RA},
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{str_lit("x2"), ClobberReg_SP},
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};
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for (auto const &t : table) {
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if (pin == t.name) {
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return t.bit;
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}
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}
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return 0;
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}
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char const *clobber_reg_bit_name(u16 bit) {
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switch (bit) {
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case ClobberReg_RA: return "ra";
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case ClobberReg_SP: return "sp";
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}
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return "<reg>";
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}
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i32 flag_bit_from_name(String const &name, i32 *width_) {
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static const struct { String name; i32 bit; } table[] = {
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// fflags: accrued FP exception flags (fcsr[4:0])
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{str_lit("nx"), 0}, // Inexact
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{str_lit("uf"), 1}, // Underflow
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{str_lit("of"), 2}, // Overflow
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{str_lit("dz"), 3}, // Divide by Zero
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{str_lit("nv"), 4}, // Invalid Operation
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// frm: rounding mode (fcsr[7:5], 3-bit field, low bit)
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{str_lit("frm"), 5}, // Rounding Mode
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};
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for (auto const &t : table) {
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if (name == t.name) {
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if (width_) {
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if (t.name == "frm") {
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*width_ = 3;
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} else {
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*width_ = 1;
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}
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}
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return t.bit;
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}
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}
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return -1;
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}
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struct Clobber {
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OperandSet written; // operand slots whose register/CSR is written
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OperandSet read; // operand slots whose register/CSR/mem-base is read
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ClobberRegs implicit_wr; // implicit reg writes (ra on C.JAL/C.JALR)
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ClobberRegs implicit_rd; // implicit reg reads (sp on the *SP forms)
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ClobberFFlags fflags_wr; // accrued exception flags this op may raise
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bool reads_frm; // consumes the dynamic rounding mode from fcsr
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bool writes_mem;
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bool reads_mem;
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SideEffectFlags side_effects;
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bool implies_clobber_flags() const {
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return (fflags_wr != 0);
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}
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bool implies_clobber_memory() const {
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return writes_mem || reads_mem ||
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(side_effects & (SideEffectFlag_FENCE|SideEffectFlag_ATOMIC)) != 0;
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}
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bool implies_side_effects() const {
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return side_effects != 0;
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}
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u8 is_call_or_mem() const {
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return (cast(u16)side_effects & SideEffectFlag_CONTROL) != 0 ||
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(cast(u16)implicit_wr & ClobberReg_SP) != 0;
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}
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bool has_control() const {
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return (cast(u16)side_effects & SideEffectFlag_CONTROL) != 0;
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}
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bool has_halt() const {
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return false;
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}
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bool is_conditional() const {
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return has_control();
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}
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};
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void clobber_implicit_regs(StringSet *clobber_registers_set, u16 implicit_regs) {
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u8 regs = cast(u8)implicit_regs;
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for (u8 bit = 1; bit != 0; bit <<= 1) {
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if ((regs & bit) == 0) {
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continue;
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}
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char const *rname = clobber_reg_bit_name(bit);
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string_set_update(clobber_registers_set, make_string_c(rname));
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}
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}
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static u16 const register_codes [REG_COUNT];
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static String const register_strings[REG_COUNT];
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enum OperandType : u8 {
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OP_NONE,
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OP_GPR,
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OP_FPR,
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OP_IMM12,
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OP_IMM12U,
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OP_IMM5,
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OP_IMM6,
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OP_IMM20,
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OP_REL13,
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OP_REL21,
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OP_MEM,
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OP_CSR,
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OP_FENCE_FLAGS,
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OP_ROUND_MODE,
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OP_ZIMM5,
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OP_GPR_C,
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OP_GPR_SP,
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OP_GPR_NONZERO,
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OP_FPR_C,
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OP_IMM_C6S,
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OP_IMM_C6U,
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OP_IMM_C8U,
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OP_IMM_C10S,
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OP_IMM_C18S,
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OP_REL9,
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OP_REL12,
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OP_MEM_C_W,
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OP_MEM_C_D,
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OP_MEM_C_SP_W,
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OP_MEM_C_SP_D,
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};
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enum OperandEncoding : u8 {
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ENC_NONE,
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ENC_RD,
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ENC_RS1,
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ENC_RS2,
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ENC_RS3,
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ENC_SHAMT5,
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ENC_SHAMT6,
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ENC_IMM_I,
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ENC_IMM_S,
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ENC_IMM_B,
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ENC_IMM_U,
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ENC_IMM_J,
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ENC_OFFSET_BASE_I,
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ENC_OFFSET_BASE_S,
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ENC_OFFSET_BASE_A,
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ENC_CSR_FIELD,
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ENC_ZIMM_FIELD,
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ENC_FENCE_PRED,
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ENC_FENCE_SUCC,
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ENC_ROUND_FIELD,
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ENC_AQRL,
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ENC_C_RD_RS1,
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ENC_C_RS2,
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ENC_C_RD_PRIMED,
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ENC_C_RS1_PRIMED,
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ENC_C_RS2_PRIMED,
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ENC_C_RD_RS1_PRIMED,
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ENC_C_IMM_CI_S,
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ENC_C_IMM_CI_U,
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ENC_C_IMM_CIW,
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ENC_C_IMM_LUI,
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ENC_C_IMM_ADDI16SP,
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ENC_C_IMM_CSS_W,
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ENC_C_IMM_CSS_D,
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ENC_C_IMM_CL_W,
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ENC_C_IMM_CL_D,
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ENC_C_BRANCH9,
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ENC_C_BRANCH12,
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ENC_C_OFFSET_BASE_W,
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ENC_C_OFFSET_BASE_D,
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ENC_C_SP_OFFSET_W,
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ENC_C_SP_OFFSET_D,
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};
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enum Feature : u8 {
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ENC_I,
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ENC_M,
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ENC_A,
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ENC_F,
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ENC_D,
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ENC_ZICSR,
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ENC_ZIFENCEI,
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ENC_C,
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};
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typedef u8 EncodingFlags; // cannot use a C++ bit field to due lack of portability
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#pragma pack(push, 1)
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struct Encoding {
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Mnemonic mnemonic;
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OperandType ops[4];
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OperandEncoding enc[4];
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u32 bits;
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u32 mask;
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Feature feature;
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EncodingFlags flags;
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bool has_implicit () const { return ((flags>>7u)&1) != 0; }
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u8 explicit_count() const { return cast(u8)((flags>>4u)&((1u<<3)-1)); }
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};
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#pragma pack(pop)
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GB_STATIC_ASSERT(gb_size_of(Encoding) == 20);
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// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS.
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struct EncodeRun {
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u32 start; // start index in ENCODE_FORMS
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u32 count; // number of forms for this mnemonic
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};
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static EncodeRun const raw_encode_runs [199];
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static u8 const raw_encode_forms [3960];
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static u8 const raw_clobber_forms[1782];
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StringMap<Mnemonic> mnemonic_map;
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StringMap<Register> register_map;
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||||
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u16 XLEN;
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u16 FLEN;
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bool init(i64 word_size) {
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XLEN = cast(u16)word_size;
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FLEN = cast(u16)word_size;
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string_map_init(&mnemonic_map, MNEMONIC_COUNT*2);
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for (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) {
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string_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m);
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}
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string_map_init(®ister_map, REG_COUNT*2);
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for (u16 r = REG_INVALID+1; r < REG_COUNT; r++) {
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string_map_set(®ister_map, register_strings[r], cast(Register)r);
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}
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return true;
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}
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||||
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||||
Mnemonic mnemonic_lookup(String const &name) {
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Mnemonic *found = string_map_get(&mnemonic_map, name);
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||||
return found ? *found : M_INVALID;
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||||
}
|
||||
Prefix prefix_lookup(String const &name) {
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||||
return PREFIX_INVALID;
|
||||
}
|
||||
static String const prefix_strings[PREFIX_COUNT];
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||||
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||||
Register register_lookup(String const &name) {
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||||
Register *found = string_map_get(®ister_map, name);
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||||
return found ? *found : REG_INVALID;
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||||
}
|
||||
Slice<Encoding> encoding_forms(/*Mnemonic*/ u16 m) const {
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||||
EncodeRun r = raw_encode_runs[m];
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||||
Encoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms;
|
||||
return Slice<Encoding>{ENCODE_FORMS+r.start, r.count};
|
||||
}
|
||||
Slice<Clobber> clobber_forms(/*Mnemonic*/ u16 m) const {
|
||||
EncodeRun r = raw_encode_runs[m];
|
||||
Clobber *CLOBBER_FORMS = cast(Clobber *)raw_clobber_forms;
|
||||
return Slice<Clobber>{CLOBBER_FORMS+r.start, r.count};
|
||||
}
|
||||
u16 reg_class(/*Register*/ u16 r) const {
|
||||
return 0xFF00 & r;
|
||||
}
|
||||
// size in bits for register
|
||||
u16 reg_size(Register r) const {
|
||||
switch (reg_class(register_codes[r])) {
|
||||
case REG_CLASS_GPR64: return 64;
|
||||
case REG_CLASS_GPR32: return 32;
|
||||
case REG_CLASS_GPR16: return 16;
|
||||
case REG_CLASS_GPR8: return 8;
|
||||
case REG_CLASS_GPR8H: return 8;
|
||||
case REG_CLASS_XMM: return 128;
|
||||
case REG_CLASS_YMM: return 256;
|
||||
case REG_CLASS_ZMM: return 512;
|
||||
case REG_CLASS_K: return 64;
|
||||
case REG_CLASS_MM: return 64;
|
||||
case REG_CLASS_ST: return 80;
|
||||
case REG_CLASS_SEG: return 16;
|
||||
case REG_CLASS_CR: return 64;
|
||||
case REG_CLASS_DR: return 64;
|
||||
case REG_CLASS_BND: return 128;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
AsmOperandKind kind_from_operand_type(OperandType type) const {
|
||||
switch (type) {
|
||||
case OP_NONE:
|
||||
return AsmOperand_Invalid;
|
||||
|
||||
// Registers
|
||||
case OP_GPR:
|
||||
case OP_FPR:
|
||||
case OP_GPR_C:
|
||||
case OP_GPR_SP:
|
||||
case OP_GPR_NONZERO:
|
||||
case OP_FPR_C:
|
||||
return AsmOperand_Register;
|
||||
|
||||
case OP_CSR: // 12-bit CSR address; treat as immediate (no CSR reg class exists)
|
||||
// TODO(bill): what should this be?
|
||||
return AsmOperand_Immediate;
|
||||
|
||||
// Immediates (incl. things that ultimately encode as an immediate field:
|
||||
// CSR address, fence flags, rounding mode).
|
||||
case OP_IMM12:
|
||||
case OP_IMM12U:
|
||||
case OP_IMM5:
|
||||
case OP_IMM6:
|
||||
case OP_IMM20:
|
||||
case OP_FENCE_FLAGS: // iorw mask -> 4-bit immediate field
|
||||
case OP_ROUND_MODE: // rm -> 3-bit immediate field
|
||||
case OP_ZIMM5:
|
||||
case OP_IMM_C6S:
|
||||
case OP_IMM_C6U:
|
||||
case OP_IMM_C8U:
|
||||
case OP_IMM_C10S:
|
||||
case OP_IMM_C18S:
|
||||
return AsmOperand_Immediate;
|
||||
|
||||
// Branch/jump targets are written as labels.
|
||||
case OP_REL13:
|
||||
case OP_REL21:
|
||||
case OP_REL9:
|
||||
case OP_REL12:
|
||||
return AsmOperand_Label;
|
||||
|
||||
// Memory
|
||||
case OP_MEM:
|
||||
case OP_MEM_C_W:
|
||||
case OP_MEM_C_D:
|
||||
case OP_MEM_C_SP_W:
|
||||
case OP_MEM_C_SP_D:
|
||||
return AsmOperand_Memory;
|
||||
}
|
||||
return AsmOperand_Invalid;
|
||||
}
|
||||
|
||||
AsmRegClass reg_class_from_operand_type(OperandType type) const {
|
||||
switch (type) {
|
||||
case OP_GPR:
|
||||
case OP_GPR_C:
|
||||
case OP_GPR_SP:
|
||||
case OP_GPR_NONZERO:
|
||||
return AsmRegClass_Integer;
|
||||
|
||||
case OP_FPR:
|
||||
case OP_FPR_C:
|
||||
return AsmRegClass_Float;
|
||||
|
||||
// No vector/mask operand types are present in this list; everything
|
||||
// else (immediates, memory, labels, CSR, etc.) has no register class.
|
||||
default:
|
||||
return AsmRegClass_Unknown;
|
||||
}
|
||||
}
|
||||
|
||||
bool operand_type_is_implicit(OperandType t) const {
|
||||
switch (t) {
|
||||
// sp is fixed by the mnemonic (c.addi16sp / c.*sp bases) and isn't a
|
||||
// register the user freely chooses, so it's encoded implicitly.
|
||||
// If your parser actually reads `sp` from the operand text, flip this.
|
||||
case OP_GPR_SP:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
AsmRegClass operand_type_reg_class(OperandType t) const {
|
||||
// Same mapping as reg_class_from_operand_type — these two look
|
||||
// redundant; consider collapsing them into one.
|
||||
return reg_class_from_operand_type(t);
|
||||
}
|
||||
|
||||
u16 operand_type_bit_width(OperandType t) const {
|
||||
switch (t) {
|
||||
case OP_NONE:
|
||||
return 0;
|
||||
|
||||
// Registers -> architectural register data width (like OP_R*, OP_XMM).
|
||||
// RISC-V doesn't encode width in the operand type: GPR is XLEN, FPR is
|
||||
// FLEN, both target-config dependent -> treat as data-dependent = 0,
|
||||
// same as x86 OP_K. (Or hardcode 32/64 if your assembler is fixed-config.)
|
||||
// The _C / _SP / _NONZERO variants only restrict *which* regs, not width.
|
||||
case OP_GPR:
|
||||
case OP_GPR_C:
|
||||
case OP_GPR_SP:
|
||||
case OP_GPR_NONZERO:
|
||||
return XLEN;
|
||||
case OP_FPR:
|
||||
case OP_FPR_C:
|
||||
return FLEN;
|
||||
|
||||
// Memory -> access size (like OP_M*). Base OP_MEM's size comes from the
|
||||
// opcode, so it's sizeless like x86 OP_M. Compressed forms name the size.
|
||||
case OP_MEM:
|
||||
return 0;
|
||||
case OP_MEM_C_W:
|
||||
case OP_MEM_C_SP_W:
|
||||
return 32;
|
||||
case OP_MEM_C_D:
|
||||
case OP_MEM_C_SP_D:
|
||||
return 64;
|
||||
|
||||
// Immediates -> value width (unchanged; matches x86 OP_IMM*).
|
||||
case OP_IMM12:
|
||||
case OP_IMM12U:
|
||||
case OP_CSR:
|
||||
return 12;
|
||||
case OP_IMM5:
|
||||
case OP_ZIMM5:
|
||||
return 5;
|
||||
case OP_IMM6:
|
||||
return 6;
|
||||
case OP_IMM20:
|
||||
return 20;
|
||||
case OP_FENCE_FLAGS:
|
||||
return 4;
|
||||
case OP_ROUND_MODE:
|
||||
return 3;
|
||||
case OP_IMM_C6S:
|
||||
case OP_IMM_C6U:
|
||||
return 6;
|
||||
case OP_IMM_C8U:
|
||||
return 8;
|
||||
case OP_IMM_C10S:
|
||||
return 10;
|
||||
case OP_IMM_C18S:
|
||||
return 18;
|
||||
|
||||
// Rels -> displacement value width (unchanged; matches x86 OP_REL*).
|
||||
case OP_REL13:
|
||||
return 13;
|
||||
case OP_REL21:
|
||||
return 21;
|
||||
case OP_REL9:
|
||||
return 9;
|
||||
case OP_REL12:
|
||||
return 12;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int form_explicit_slot(Encoding const &form, int explicit_index) const {
|
||||
int seen = 0;
|
||||
for (int j = 0; j < gb_count_of(form.ops); j++) {
|
||||
auto t = form.ops[j];
|
||||
if (!t) {
|
||||
break;
|
||||
}
|
||||
if (operand_type_is_implicit(t)) {
|
||||
continue;
|
||||
}
|
||||
if (seen == explicit_index) {
|
||||
return j;
|
||||
}
|
||||
seen += 1;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) const {
|
||||
// RISC-V does not have prefixes
|
||||
return false;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
|
||||
gb_global Asm_riscv g_asm_riscv;
|
||||
|
||||
|
||||
|
||||
String const Asm_riscv::prefix_strings[Asm_riscv::PREFIX_COUNT]{};
|
||||
String const Asm_riscv::mnemonic_strings[Asm_riscv::MNEMONIC_COUNT] {
|
||||
str_lit(""), str_lit("lui"), str_lit("auipc"), str_lit("jal"), str_lit("jalr"), str_lit("beq"), str_lit("bne"), str_lit("blt"), str_lit("bge"), str_lit("bltu"), str_lit("bgeu"), str_lit("lb"), str_lit("lh"), str_lit("lw"), str_lit("lbu"), str_lit("lhu"),
|
||||
str_lit("sb"), str_lit("sh"), str_lit("sw"), str_lit("lwu"), str_lit("ld"), str_lit("sd"), str_lit("addi"), str_lit("slti"), str_lit("sltiu"), str_lit("xori"), str_lit("ori"), str_lit("andi"), str_lit("slli"), str_lit("srli"), str_lit("srai"), str_lit("addiw"),
|
||||
str_lit("slliw"), str_lit("srliw"), str_lit("sraiw"), str_lit("add"), str_lit("sub"), str_lit("sll"), str_lit("slt"), str_lit("sltu"), str_lit("xor"), str_lit("srl"), str_lit("sra"), str_lit("or"), str_lit("and"), str_lit("addw"), str_lit("subw"), str_lit("sllw"),
|
||||
str_lit("srlw"), str_lit("sraw"), str_lit("fence"), str_lit("fence_i"), str_lit("ecall"), str_lit("ebreak"), str_lit("csrrw"), str_lit("csrrs"), str_lit("csrrc"), str_lit("csrrwi"), str_lit("csrrsi"), str_lit("csrrci"), str_lit("mul"), str_lit("mulh"), str_lit("mulhsu"), str_lit("mulhu"),
|
||||
str_lit("div"), str_lit("divu"), str_lit("rem"), str_lit("remu"), str_lit("mulw"), str_lit("divw"), str_lit("divuw"), str_lit("remw"), str_lit("remuw"), str_lit("lr_w"), str_lit("sc_w"), str_lit("amoswap_w"), str_lit("amoadd_w"), str_lit("amoxor_w"), str_lit("amoand_w"), str_lit("amoor_w"),
|
||||
str_lit("amomin_w"), str_lit("amomax_w"), str_lit("amominu_w"), str_lit("amomaxu_w"), str_lit("lr_d"), str_lit("sc_d"), str_lit("amoswap_d"), str_lit("amoadd_d"), str_lit("amoxor_d"), str_lit("amoand_d"), str_lit("amoor_d"), str_lit("amomin_d"), str_lit("amomax_d"), str_lit("amominu_d"), str_lit("amomaxu_d"), str_lit("flw"),
|
||||
str_lit("fsw"), str_lit("fmadd_s"), str_lit("fmsub_s"), str_lit("fnmsub_s"), str_lit("fnmadd_s"), str_lit("fadd_s"), str_lit("fsub_s"), str_lit("fmul_s"), str_lit("fdiv_s"), str_lit("fsqrt_s"), str_lit("fsgnj_s"), str_lit("fsgnjn_s"), str_lit("fsgnjx_s"), str_lit("fmin_s"), str_lit("fmax_s"), str_lit("fcvt_w_s"),
|
||||
str_lit("fcvt_wu_s"), str_lit("fmv_x_w"), str_lit("feq_s"), str_lit("flt_s"), str_lit("fle_s"), str_lit("fclass_s"), str_lit("fcvt_s_w"), str_lit("fcvt_s_wu"), str_lit("fmv_w_x"), str_lit("fcvt_l_s"), str_lit("fcvt_lu_s"), str_lit("fcvt_s_l"), str_lit("fcvt_s_lu"), str_lit("fld"), str_lit("fsd"), str_lit("fmadd_d"),
|
||||
str_lit("fmsub_d"), str_lit("fnmsub_d"), str_lit("fnmadd_d"), str_lit("fadd_d"), str_lit("fsub_d"), str_lit("fmul_d"), str_lit("fdiv_d"), str_lit("fsqrt_d"), str_lit("fsgnj_d"), str_lit("fsgnjn_d"), str_lit("fsgnjx_d"), str_lit("fmin_d"), str_lit("fmax_d"), str_lit("fcvt_s_d"), str_lit("fcvt_d_s"), str_lit("feq_d"),
|
||||
str_lit("flt_d"), str_lit("fle_d"), str_lit("fclass_d"), str_lit("fcvt_w_d"), str_lit("fcvt_wu_d"), str_lit("fcvt_d_w"), str_lit("fcvt_d_wu"), str_lit("fcvt_l_d"), str_lit("fcvt_lu_d"), str_lit("fcvt_d_l"), str_lit("fcvt_d_lu"), str_lit("fmv_x_d"), str_lit("fmv_d_x"), str_lit("c_nop"), str_lit("c_ebreak"), str_lit("c_addi4spn"),
|
||||
str_lit("c_lw"), str_lit("c_ld"), str_lit("c_sw"), str_lit("c_sd"), str_lit("c_flw"), str_lit("c_fsw"), str_lit("c_fld"), str_lit("c_fsd"), str_lit("c_addi"), str_lit("c_addiw"), str_lit("c_li"), str_lit("c_lui"), str_lit("c_addi16sp"), str_lit("c_srli"), str_lit("c_srai"), str_lit("c_andi"),
|
||||
str_lit("c_sub"), str_lit("c_xor"), str_lit("c_or"), str_lit("c_and"), str_lit("c_subw"), str_lit("c_addw"), str_lit("c_j"), str_lit("c_jal"), str_lit("c_beqz"), str_lit("c_bnez"), str_lit("c_slli"), str_lit("c_lwsp"), str_lit("c_ldsp"), str_lit("c_swsp"), str_lit("c_sdsp"), str_lit("c_fldsp"),
|
||||
str_lit("c_fsdsp"), str_lit("c_jr"), str_lit("c_jalr"), str_lit("c_mv"), str_lit("c_add"), str_lit("c_flwsp"), str_lit("c_fswsp"),
|
||||
};
|
||||
u16 const Asm_riscv::register_codes[Asm_riscv::REG_COUNT] {
|
||||
0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270,
|
||||
271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286,
|
||||
287, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526,
|
||||
527, 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542,
|
||||
543,
|
||||
};
|
||||
String const Asm_riscv::register_strings[Asm_riscv::REG_COUNT] {
|
||||
str_lit(""), str_lit("zero"), str_lit("ra"), str_lit("sp"), str_lit("gp"), str_lit("tp"), str_lit("t0"), str_lit("t1"), str_lit("t2"), str_lit("s0"), str_lit("s1"), str_lit("a0"), str_lit("a1"), str_lit("a2"), str_lit("a3"), str_lit("a4"),
|
||||
str_lit("a5"), str_lit("a6"), str_lit("a7"), str_lit("s2"), str_lit("s3"), str_lit("s4"), str_lit("s5"), str_lit("s6"), str_lit("s7"), str_lit("s8"), str_lit("s9"), str_lit("s10"), str_lit("s11"), str_lit("t3"), str_lit("t4"), str_lit("t5"),
|
||||
str_lit("t6"), str_lit("ft0"), str_lit("ft1"), str_lit("ft2"), str_lit("ft3"), str_lit("ft4"), str_lit("ft5"), str_lit("ft6"), str_lit("ft7"), str_lit("fs0"), str_lit("fs1"), str_lit("fa0"), str_lit("fa1"), str_lit("fa2"), str_lit("fa3"), str_lit("fa4"),
|
||||
str_lit("fa5"), str_lit("fa6"), str_lit("fa7"), str_lit("fs2"), str_lit("fs3"), str_lit("fs4"), str_lit("fs5"), str_lit("fs6"), str_lit("fs7"), str_lit("fs8"), str_lit("fs9"), str_lit("fs10"), str_lit("fs11"), str_lit("ft8"), str_lit("ft9"), str_lit("ft10"),
|
||||
str_lit("ft11"),
|
||||
};
|
||||
Asm_riscv::EncodeRun const Asm_riscv::raw_encode_runs[199] = {
|
||||
{ 0, 0}, { 0, 1}, { 1, 1}, { 2, 1}, { 3, 1}, { 4, 1}, { 5, 1}, { 6, 1}, { 7, 1}, { 8, 1}, { 9, 1}, { 10, 1}, { 11, 1}, { 12, 1}, { 13, 1}, { 14, 1},
|
||||
{ 15, 1}, { 16, 1}, { 17, 1}, { 18, 1}, { 19, 1}, { 20, 1}, { 21, 1}, { 22, 1}, { 23, 1}, { 24, 1}, { 25, 1}, { 26, 1}, { 27, 1}, { 28, 1}, { 29, 1}, { 30, 1},
|
||||
{ 31, 1}, { 32, 1}, { 33, 1}, { 34, 1}, { 35, 1}, { 36, 1}, { 37, 1}, { 38, 1}, { 39, 1}, { 40, 1}, { 41, 1}, { 42, 1}, { 43, 1}, { 44, 1}, { 45, 1}, { 46, 1},
|
||||
{ 47, 1}, { 48, 1}, { 49, 1}, { 50, 1}, { 51, 1}, { 52, 1}, { 53, 1}, { 54, 1}, { 55, 1}, { 56, 1}, { 57, 1}, { 58, 1}, { 59, 1}, { 60, 1}, { 61, 1}, { 62, 1},
|
||||
{ 63, 1}, { 64, 1}, { 65, 1}, { 66, 1}, { 67, 1}, { 68, 1}, { 69, 1}, { 70, 1}, { 71, 1}, { 72, 1}, { 73, 1}, { 74, 1}, { 75, 1}, { 76, 1}, { 77, 1}, { 78, 1},
|
||||
{ 79, 1}, { 80, 1}, { 81, 1}, { 82, 1}, { 83, 1}, { 84, 1}, { 85, 1}, { 86, 1}, { 87, 1}, { 88, 1}, { 89, 1}, { 90, 1}, { 91, 1}, { 92, 1}, { 93, 1}, { 94, 1},
|
||||
{ 95, 1}, { 96, 1}, { 97, 1}, { 98, 1}, { 99, 1}, { 100, 1}, { 101, 1}, { 102, 1}, { 103, 1}, { 104, 1}, { 105, 1}, { 106, 1}, { 107, 1}, { 108, 1}, { 109, 1}, { 110, 1},
|
||||
{ 111, 1}, { 112, 1}, { 113, 1}, { 114, 1}, { 115, 1}, { 116, 1}, { 117, 1}, { 118, 1}, { 119, 1}, { 120, 1}, { 121, 1}, { 122, 1}, { 123, 1}, { 124, 1}, { 125, 1}, { 126, 1},
|
||||
{ 127, 1}, { 128, 1}, { 129, 1}, { 130, 1}, { 131, 1}, { 132, 1}, { 133, 1}, { 134, 1}, { 135, 1}, { 136, 1}, { 137, 1}, { 138, 1}, { 139, 1}, { 140, 1}, { 141, 1}, { 142, 1},
|
||||
{ 143, 1}, { 144, 1}, { 145, 1}, { 146, 1}, { 147, 1}, { 148, 1}, { 149, 1}, { 150, 1}, { 151, 1}, { 152, 1}, { 153, 1}, { 154, 1}, { 155, 1}, { 156, 1}, { 157, 1}, { 158, 1},
|
||||
{ 159, 1}, { 160, 1}, { 161, 1}, { 162, 1}, { 163, 1}, { 164, 1}, { 165, 1}, { 166, 1}, { 167, 1}, { 168, 1}, { 169, 1}, { 170, 1}, { 171, 1}, { 172, 1}, { 173, 1}, { 174, 1},
|
||||
{ 175, 1}, { 176, 1}, { 177, 1}, { 178, 1}, { 179, 1}, { 180, 1}, { 181, 1}, { 182, 1}, { 183, 1}, { 184, 1}, { 185, 1}, { 186, 1}, { 187, 1}, { 188, 1}, { 189, 1}, { 190, 1},
|
||||
{ 191, 1}, { 192, 1}, { 193, 1}, { 194, 1}, { 195, 1}, { 196, 1}, { 197, 1},
|
||||
};
|
||||
u8 const Asm_riscv::raw_encode_forms[3960] = {
|
||||
0x01, 0x00, 0x01, 0x07, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x37, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x07, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x09, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0x6f, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x00, 0x01, 0x01,
|
||||
0x03, 0x00, 0x01, 0x02, 0x07, 0x00, 0x67, 0x00, 0x00, 0x00, 0x7f, 0x70, 0x00, 0x00, 0x00, 0x04, 0x05, 0x00, 0x01, 0x01, 0x08, 0x00, 0x02, 0x03, 0x09, 0x00, 0x63, 0x00, 0x00, 0x00, 0x7f, 0x70, 0x00, 0x00, 0x00, 0x04, 0x06, 0x00, 0x01, 0x01, 0x08, 0x00, 0x02, 0x03, 0x09, 0x00, 0x63, 0x10, 0x00, 0x00, 0x7f, 0x70, 0x00, 0x00, 0x00, 0x04, 0x07, 0x00, 0x01, 0x01, 0x08, 0x00, 0x02, 0x03,
|
||||
0x09, 0x00, 0x63, 0x40, 0x00, 0x00, 0x7f, 0x70, 0x00, 0x00, 0x00, 0x04, 0x08, 0x00, 0x01, 0x01, 0x08, 0x00, 0x02, 0x03, 0x09, 0x00, 0x63, 0x50, 0x00, 0x00, 0x7f, 0x70, 0x00, 0x00, 0x00, 0x04, 0x09, 0x00, 0x01, 0x01, 0x08, 0x00, 0x02, 0x03, 0x09, 0x00, 0x63, 0x60, 0x00, 0x00, 0x7f, 0x70, 0x00, 0x00, 0x00, 0x04, 0x0a, 0x00, 0x01, 0x01, 0x08, 0x00, 0x02, 0x03, 0x09, 0x00, 0x63, 0x70,
|
||||
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0x03, 0x00, 0x53, 0x00, 0x00, 0x10, 0x7f, 0x00, 0x00, 0xfe, 0x03, 0x08, 0x68, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0x18, 0x7f, 0x00, 0x00, 0xfe, 0x03, 0x08, 0x69, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0x58, 0x7f, 0x00, 0xf0, 0xff, 0x03, 0x08, 0x6a, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00,
|
||||
0x00, 0x20, 0x7f, 0x70, 0x00, 0xfe, 0x03, 0x00, 0x6b, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x10, 0x00, 0x20, 0x7f, 0x70, 0x00, 0xfe, 0x03, 0x00, 0x6c, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x20, 0x00, 0x20, 0x7f, 0x70, 0x00, 0xfe, 0x03, 0x00, 0x6d, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0x28, 0x7f, 0x70,
|
||||
0x00, 0xfe, 0x03, 0x00, 0x6e, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x10, 0x00, 0x28, 0x7f, 0x70, 0x00, 0xfe, 0x03, 0x00, 0x6f, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0xc0, 0x7f, 0x00, 0xf0, 0xff, 0x03, 0x08, 0x70, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x10, 0xc0, 0x7f, 0x00, 0xf0, 0xff, 0x03, 0x08,
|
||||
0x71, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0xe0, 0x7f, 0x70, 0xf0, 0xff, 0x03, 0x00, 0x72, 0x00, 0x01, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x20, 0x00, 0xa0, 0x7f, 0x70, 0x00, 0xfe, 0x03, 0x00, 0x73, 0x00, 0x01, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x10, 0x00, 0xa0, 0x7f, 0x70, 0x00, 0xfe, 0x03, 0x00, 0x74, 0x00, 0x01, 0x02,
|
||||
0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0xa0, 0x7f, 0x70, 0x00, 0xfe, 0x03, 0x00, 0x75, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x10, 0x00, 0xe0, 0x7f, 0x70, 0xf0, 0xff, 0x03, 0x00, 0x76, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0xd0, 0x7f, 0x00, 0xf0, 0xff, 0x03, 0x08, 0x77, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02,
|
||||
0x00, 0x00, 0x53, 0x00, 0x10, 0xd0, 0x7f, 0x00, 0xf0, 0xff, 0x03, 0x08, 0x78, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0xf0, 0x7f, 0x70, 0xf0, 0xff, 0x03, 0x00, 0x79, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x20, 0xc0, 0x7f, 0x00, 0xf0, 0xff, 0x03, 0x0a, 0x7a, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00,
|
||||
0x30, 0xc0, 0x7f, 0x00, 0xf0, 0xff, 0x03, 0x0a, 0x7b, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x20, 0xd0, 0x7f, 0x00, 0xf0, 0xff, 0x03, 0x0a, 0x7c, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x30, 0xd0, 0x7f, 0x00, 0xf0, 0xff, 0x03, 0x0a, 0x7d, 0x00, 0x02, 0x0a, 0x00, 0x00, 0x01, 0x0c, 0x00, 0x00, 0x07, 0x30, 0x00, 0x00, 0x7f, 0x70,
|
||||
0x00, 0x00, 0x04, 0x00, 0x7e, 0x00, 0x02, 0x0a, 0x00, 0x00, 0x03, 0x0d, 0x00, 0x00, 0x27, 0x30, 0x00, 0x00, 0x7f, 0x70, 0x00, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02, 0x03, 0x04, 0x43, 0x00, 0x00, 0x02, 0x7f, 0x00, 0x00, 0x06, 0x04, 0x08, 0x80, 0x00, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02, 0x03, 0x04, 0x47, 0x00, 0x00, 0x02, 0x7f, 0x00, 0x00, 0x06, 0x04, 0x08,
|
||||
0x81, 0x00, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02, 0x03, 0x04, 0x4b, 0x00, 0x00, 0x02, 0x7f, 0x00, 0x00, 0x06, 0x04, 0x08, 0x82, 0x00, 0x02, 0x02, 0x02, 0x02, 0x01, 0x02, 0x03, 0x04, 0x4f, 0x00, 0x00, 0x02, 0x7f, 0x00, 0x00, 0x06, 0x04, 0x08, 0x83, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0x02, 0x7f, 0x00, 0x00, 0xfe, 0x04, 0x08, 0x84, 0x00, 0x02, 0x02,
|
||||
0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0x0a, 0x7f, 0x00, 0x00, 0xfe, 0x04, 0x08, 0x85, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0x12, 0x7f, 0x00, 0x00, 0xfe, 0x04, 0x08, 0x86, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0x1a, 0x7f, 0x00, 0x00, 0xfe, 0x04, 0x08, 0x87, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x02,
|
||||
0x00, 0x00, 0x53, 0x00, 0x00, 0x5a, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x08, 0x88, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0x22, 0x7f, 0x70, 0x00, 0xfe, 0x04, 0x00, 0x89, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x10, 0x00, 0x22, 0x7f, 0x70, 0x00, 0xfe, 0x04, 0x00, 0x8a, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x20,
|
||||
0x00, 0x22, 0x7f, 0x70, 0x00, 0xfe, 0x04, 0x00, 0x8b, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0x2a, 0x7f, 0x70, 0x00, 0xfe, 0x04, 0x00, 0x8c, 0x00, 0x02, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x10, 0x00, 0x2a, 0x7f, 0x70, 0x00, 0xfe, 0x04, 0x00, 0x8d, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x10, 0x40, 0x7f, 0x00,
|
||||
0xf0, 0xff, 0x04, 0x08, 0x8e, 0x00, 0x02, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0x42, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x08, 0x8f, 0x00, 0x01, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x20, 0x00, 0xa2, 0x7f, 0x70, 0x00, 0xfe, 0x04, 0x00, 0x90, 0x00, 0x01, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x10, 0x00, 0xa2, 0x7f, 0x70, 0x00, 0xfe, 0x04, 0x00,
|
||||
0x91, 0x00, 0x01, 0x02, 0x02, 0x00, 0x01, 0x02, 0x03, 0x00, 0x53, 0x00, 0x00, 0xa2, 0x7f, 0x70, 0x00, 0xfe, 0x04, 0x00, 0x92, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x10, 0x00, 0xe2, 0x7f, 0x70, 0xf0, 0xff, 0x04, 0x00, 0x93, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0xc2, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x08, 0x94, 0x00, 0x01, 0x02,
|
||||
0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x10, 0xc2, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x08, 0x95, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0xd2, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x08, 0x96, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x10, 0xd2, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x08, 0x97, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02,
|
||||
0x00, 0x00, 0x53, 0x00, 0x20, 0xc2, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x0a, 0x98, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x30, 0xc2, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x0a, 0x99, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x20, 0xd2, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x0a, 0x9a, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00,
|
||||
0x30, 0xd2, 0x7f, 0x00, 0xf0, 0xff, 0x04, 0x0a, 0x9b, 0x00, 0x01, 0x02, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0xe2, 0x7f, 0x70, 0xf0, 0xff, 0x04, 0x02, 0x9c, 0x00, 0x02, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x53, 0x00, 0x00, 0xf2, 0x7f, 0x70, 0xf0, 0xff, 0x04, 0x02, 0x9d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0xff, 0xff,
|
||||
0x00, 0x00, 0x07, 0x00, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x07, 0x00, 0x9f, 0x00, 0x0f, 0x10, 0x15, 0x00, 0x17, 0x00, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x00, 0xa0, 0x00, 0x0f, 0x1a, 0x00, 0x00, 0x17, 0x26, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x00,
|
||||
0xa1, 0x00, 0x0f, 0x1b, 0x00, 0x00, 0x17, 0x27, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x02, 0xa2, 0x00, 0x0f, 0x1a, 0x00, 0x00, 0x19, 0x26, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x00, 0xa3, 0x00, 0x0f, 0x1b, 0x00, 0x00, 0x19, 0x27, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x02, 0xa4, 0x00, 0x12, 0x1a,
|
||||
0x00, 0x00, 0x17, 0x26, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x03, 0x01, 0xa5, 0x00, 0x12, 0x1a, 0x00, 0x00, 0x19, 0x26, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x03, 0x01, 0xa6, 0x00, 0x12, 0x1b, 0x00, 0x00, 0x17, 0x27, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x04, 0x00, 0xa7, 0x00, 0x12, 0x1b, 0x00, 0x00, 0x19, 0x27,
|
||||
0x00, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x04, 0x00, 0xa8, 0x00, 0x11, 0x13, 0x00, 0x00, 0x15, 0x1b, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x00, 0xa9, 0x00, 0x11, 0x13, 0x00, 0x00, 0x15, 0x1b, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x02, 0xaa, 0x00, 0x11, 0x13, 0x00, 0x00, 0x15, 0x1b, 0x00, 0x00, 0x01, 0x40,
|
||||
0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x00, 0xab, 0x00, 0x11, 0x17, 0x00, 0x00, 0x15, 0x1e, 0x00, 0x00, 0x01, 0x60, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x00, 0xac, 0x00, 0x10, 0x16, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x01, 0x61, 0x00, 0x00, 0x83, 0xef, 0x00, 0x00, 0x07, 0x00, 0xad, 0x00, 0x0f, 0x14, 0x00, 0x00, 0x1a, 0x1c, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x03, 0xec,
|
||||
0x00, 0x00, 0x07, 0x00, 0xae, 0x00, 0x0f, 0x14, 0x00, 0x00, 0x1a, 0x1c, 0x00, 0x00, 0x01, 0x84, 0x00, 0x00, 0x03, 0xec, 0x00, 0x00, 0x07, 0x00, 0xaf, 0x00, 0x0f, 0x13, 0x00, 0x00, 0x1a, 0x1b, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00, 0x03, 0xec, 0x00, 0x00, 0x07, 0x00, 0xb0, 0x00, 0x0f, 0x0f, 0x00, 0x00, 0x1a, 0x19, 0x00, 0x00, 0x01, 0x8c, 0x00, 0x00, 0x63, 0xfc, 0x00, 0x00, 0x07, 0x00,
|
||||
0xb1, 0x00, 0x0f, 0x0f, 0x00, 0x00, 0x1a, 0x19, 0x00, 0x00, 0x21, 0x8c, 0x00, 0x00, 0x63, 0xfc, 0x00, 0x00, 0x07, 0x00, 0xb2, 0x00, 0x0f, 0x0f, 0x00, 0x00, 0x1a, 0x19, 0x00, 0x00, 0x41, 0x8c, 0x00, 0x00, 0x63, 0xfc, 0x00, 0x00, 0x07, 0x00, 0xb3, 0x00, 0x0f, 0x0f, 0x00, 0x00, 0x1a, 0x19, 0x00, 0x00, 0x61, 0x8c, 0x00, 0x00, 0x63, 0xfc, 0x00, 0x00, 0x07, 0x00, 0xb4, 0x00, 0x0f, 0x0f,
|
||||
0x00, 0x00, 0x1a, 0x19, 0x00, 0x00, 0x01, 0x9c, 0x00, 0x00, 0x63, 0xfc, 0x00, 0x00, 0x07, 0x02, 0xb5, 0x00, 0x0f, 0x0f, 0x00, 0x00, 0x1a, 0x19, 0x00, 0x00, 0x21, 0x9c, 0x00, 0x00, 0x63, 0xfc, 0x00, 0x00, 0x07, 0x02, 0xb6, 0x00, 0x19, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x01, 0xa0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x04, 0xb7, 0x00, 0x19, 0x00, 0x00, 0x00, 0x25, 0x00,
|
||||
0x00, 0x00, 0x01, 0x20, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x05, 0xb8, 0x00, 0x0f, 0x18, 0x00, 0x00, 0x18, 0x24, 0x00, 0x00, 0x01, 0xc0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x04, 0xb9, 0x00, 0x0f, 0x18, 0x00, 0x00, 0x18, 0x24, 0x00, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x04, 0xba, 0x00, 0x11, 0x14, 0x00, 0x00, 0x15, 0x1c, 0x00, 0x00, 0x02, 0x00,
|
||||
0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x00, 0xbb, 0x00, 0x11, 0x1c, 0x00, 0x00, 0x15, 0x28, 0x00, 0x00, 0x02, 0x40, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x00, 0xbc, 0x00, 0x11, 0x1d, 0x00, 0x00, 0x15, 0x29, 0x00, 0x00, 0x02, 0x60, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x02, 0xbd, 0x00, 0x01, 0x1c, 0x00, 0x00, 0x16, 0x20, 0x00, 0x00, 0x02, 0xc0, 0x00, 0x00, 0x03, 0xe0,
|
||||
0x00, 0x00, 0x07, 0x00, 0xbe, 0x00, 0x01, 0x1d, 0x00, 0x00, 0x16, 0x21, 0x00, 0x00, 0x02, 0xe0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x07, 0x02, 0xbf, 0x00, 0x02, 0x1d, 0x00, 0x00, 0x15, 0x29, 0x00, 0x00, 0x02, 0x20, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x04, 0x00, 0xc0, 0x00, 0x02, 0x1d, 0x00, 0x00, 0x16, 0x21, 0x00, 0x00, 0x02, 0xa0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x04, 0x00,
|
||||
0xc1, 0x00, 0x11, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x7f, 0xf0, 0x00, 0x00, 0x07, 0x04, 0xc2, 0x00, 0x11, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x02, 0x90, 0x00, 0x00, 0x7f, 0xf0, 0x00, 0x00, 0x07, 0x04, 0xc3, 0x00, 0x11, 0x11, 0x00, 0x00, 0x15, 0x16, 0x00, 0x00, 0x02, 0x80, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x07, 0x00, 0xc4, 0x00, 0x11, 0x11,
|
||||
0x00, 0x00, 0x15, 0x16, 0x00, 0x00, 0x02, 0x90, 0x00, 0x00, 0x03, 0xf0, 0x00, 0x00, 0x07, 0x00, 0xc5, 0x00, 0x02, 0x1c, 0x00, 0x00, 0x15, 0x28, 0x00, 0x00, 0x02, 0x60, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x03, 0x01, 0xc6, 0x00, 0x02, 0x1c, 0x00, 0x00, 0x16, 0x20, 0x00, 0x00, 0x02, 0xe0, 0x00, 0x00, 0x03, 0xe0, 0x00, 0x00, 0x03, 0x01,
|
||||
};
|
||||
u8 const Asm_riscv::raw_clobber_forms[1782] = {
|
||||
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};
|
||||
Reference in New Issue
Block a user