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rexcode/mips: MSA BIT-shift, element-index, GPR-index, I8 forms

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New MSA_BIT_SHIFT / MSA_ELM_IDX / MSA_I8 encodings (the data-format marker
is fixed in the entry bits; the operand drives the low bits; decode infers
df from the marker). SLLI/SRAI/SRLI (.B/.H/.W/.D shift), SPLATI/SLDI
(element index), SPLAT/SLD (GPR index), VSHF (.B/.H/.W/.D shuffle), and
the I8 forms ANDI/ORI/XORI/NORI/BMNZI/BMZI/BSELI.B + SHF.B/H/W. 42 forms.
Spot-checked byte-exact vs llvm-mc and decode-clean across all formats;
281 tests green.
This commit is contained in:
Brendan Punsky
2026-06-18 03:17:39 -04:00
committed by Flāvius
parent 307aa2a9dd
commit 4ab24007b7
13 changed files with 801 additions and 384 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
core/rexcode/mips/decoder.odin
View File

@@ -313,6 +313,26 @@ extract_operand_inline :: #force_inline proc "contextless" (
return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
case .MSA_BIT5:
return Operand{immediate = i64((word >> 11) & 0x1F), kind = .IMMEDIATE, size = 1}
case .MSA_BIT_SHIFT:
// m at 22:16; df from the marker, shift = m - marker.
m := (word >> 16) & 0x7F
sh: u32
if m >= 0x70 { sh = m & 0x07 }
else if m >= 0x60 { sh = m & 0x0F }
else if m >= 0x40 { sh = m & 0x1F }
else { sh = m & 0x3F }
return Operand{immediate = i64(sh), kind = .IMMEDIATE, size = 1}
case .MSA_ELM_IDX:
// n at 21:16; df from the marker, index = n - marker.
n := (word >> 16) & 0x3F
idx: u32
if n >= 0x38 { idx = n & 0x01 }
else if n >= 0x30 { idx = n & 0x03 }
else if n >= 0x20 { idx = n & 0x07 }
else { idx = n & 0x0F }
return Operand{immediate = i64(idx), kind = .IMMEDIATE, size = 1}
case .MSA_I8:
return Operand{immediate = i64((word >> 16) & 0xFF), kind = .IMMEDIATE, size = 1}
case .MSA_OFFSET_BASE_B, .MSA_OFFSET_BASE_H, .MSA_OFFSET_BASE_W, .MSA_OFFSET_BASE_D:
shift: u32 = 0

6
core/rexcode/mips/encoder.odin
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@@ -388,6 +388,12 @@ pack_operand_inline :: #force_inline proc(
return (u32(op.immediate) & 0x3FF) << 16
case .MSA_BIT5:
return (u32(op.immediate) & 0x1F) << 11
case .MSA_BIT_SHIFT, .MSA_ELM_IDX:
// The marker (data format) is fixed in `bits`; the operand drives the
// low bits of the shift/index field at bit 16.
return (u32(op.immediate) & 0x3F) << 16
case .MSA_I8:
return (u32(op.immediate) & 0xFF) << 16
// MSA memory operand: base GPR at 15:11, signed-10 disp at 25:16
// (caller has already scaled the displacement by element size).

6
core/rexcode/mips/encoding_types.odin
View File

@@ -231,6 +231,12 @@ Operand_Encoding :: enum u8 {
MSA_I5, // 5-bit immediate at bits 20:16 (LDI/I5 forms)
MSA_S10, // signed 10-bit displacement at bits 25:16 (MI10 load/store)
MSA_BIT5, // bit position (5-bit) at bits 16:11 (BIT form)
// The shift amount / element index sits at bits 22:16 / 21:16 with the data
// format encoded by the high (marker) bits; the operand drives the low bits
// (the marker is fixed in the entry `bits`). Decode infers df from the marker.
MSA_BIT_SHIFT, // BIT-format shift amount (.B m=0x70|sh, .H 0x60|sh, .W 0x40|sh, .D sh)
MSA_ELM_IDX, // ELM-format element index (.B n, .H 0x20|n, .W 0x30|n, .D 0x38|n)
MSA_I8, // 8-bit immediate at bits 23:16 (I8 forms: ANDI.B/SHF/...)
// MSA memory operand: base GPR at bits 15:11 + signed 10-bit disp at 25:16,
// scaled by element size (1/2/4/8 for B/H/W/D).

168
core/rexcode/mips/mnemonic_builders.odin
View File

@@ -1186,12 +1186,26 @@ inst_nor_v_w_w_w :: #force_inline proc "contextless" (dst: Register, sr
emit_nor_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nor_v_w_w_w(dst, src, src2)) }
inst_xor_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XOR_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_xor_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xor_v_w_w_w(dst, src, src2)) }
inst_andi_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ANDI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_andi_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_andi_b_w_w_i5(dst, src, imm)) }
inst_ori_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ORI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_ori_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ori_b_w_w_i5(dst, src, imm)) }
inst_nori_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .NORI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_nori_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_nori_b_w_w_i5(dst, src, imm)) }
inst_xori_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XORI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_xori_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_xori_b_w_w_i5(dst, src, imm)) }
inst_bsel_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSEL_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_bsel_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsel_v_w_w_w(dst, src, src2)) }
inst_bseli_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BSELI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_bseli_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bseli_b_w_w_i5(dst, src, imm)) }
inst_bmnz_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BMNZ_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_bmnz_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bmnz_v_w_w_w(dst, src, src2)) }
inst_bmnzi_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BMNZI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_bmnzi_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bmnzi_b_w_w_i5(dst, src, imm)) }
inst_bmz_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BMZ_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_bmz_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bmz_v_w_w_w(dst, src, src2)) }
inst_bmzi_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BMZI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_bmzi_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bmzi_b_w_w_i5(dst, src, imm)) }
inst_ceq_b_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CEQ_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_ceq_b_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ceq_b_w_w_w(dst, src, src2)) }
inst_ceq_h_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CEQ_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
@@ -1288,6 +1302,30 @@ inst_sra_w_w_w_w :: #force_inline proc "contextless" (dst: Register, sr
emit_sra_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sra_w_w_w_w(dst, src, src2)) }
inst_sra_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRA_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_sra_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sra_d_w_w_w(dst, src, src2)) }
inst_slli_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLLI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_slli_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_slli_b_w_w_i5(dst, src, imm)) }
inst_slli_h_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLLI_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_slli_h_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_slli_h_w_w_i5(dst, src, imm)) }
inst_slli_w_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLLI_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_slli_w_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_slli_w_w_w_i5(dst, src, imm)) }
inst_slli_d_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLLI_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_slli_d_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_slli_d_w_w_i5(dst, src, imm)) }
inst_srli_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRLI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_srli_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srli_b_w_w_i5(dst, src, imm)) }
inst_srli_h_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRLI_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_srli_h_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srli_h_w_w_i5(dst, src, imm)) }
inst_srli_w_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRLI_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_srli_w_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srli_w_w_w_i5(dst, src, imm)) }
inst_srli_d_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRLI_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_srli_d_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srli_d_w_w_i5(dst, src, imm)) }
inst_srai_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRAI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_srai_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srai_b_w_w_i5(dst, src, imm)) }
inst_srai_h_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRAI_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_srai_h_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srai_h_w_w_i5(dst, src, imm)) }
inst_srai_w_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRAI_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_srai_w_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srai_w_w_w_i5(dst, src, imm)) }
inst_srai_d_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRAI_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_srai_d_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srai_d_w_w_i5(dst, src, imm)) }
inst_fadd_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_fadd_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_w_w_w_w(dst, src, src2)) }
inst_fadd_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
@@ -1384,6 +1422,52 @@ inst_ldi_w_w_i5 :: #force_inline proc "contextless" (dst: Register, im
emit_ldi_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_ldi_w_w_i5(dst, imm)) }
inst_ldi_d_w_i5 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LDI_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm, 1), {}, {}}} }
emit_ldi_d_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_ldi_d_w_i5(dst, imm)) }
inst_shf_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHF_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_shf_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shf_b_w_w_i5(dst, src, imm)) }
inst_shf_h_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHF_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_shf_h_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shf_h_w_w_i5(dst, src, imm)) }
inst_shf_w_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHF_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_shf_w_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shf_w_w_w_i5(dst, src, imm)) }
inst_vshf_b_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSHF_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vshf_b_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vshf_b_w_w_w(dst, src, src2)) }
inst_vshf_h_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSHF_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vshf_h_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vshf_h_w_w_w(dst, src, src2)) }
inst_vshf_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSHF_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vshf_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vshf_w_w_w_w(dst, src, src2)) }
inst_vshf_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSHF_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vshf_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vshf_d_w_w_w(dst, src, src2)) }
inst_sld_b_w_w_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction { return Instruction{mnemonic = .SLD_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_gpr(src2), {}}} }
emit_sld_b_w_w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) { append(instructions, inst_sld_b_w_w_r(dst, src, src2)) }
inst_sld_h_w_w_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction { return Instruction{mnemonic = .SLD_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_gpr(src2), {}}} }
emit_sld_h_w_w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) { append(instructions, inst_sld_h_w_w_r(dst, src, src2)) }
inst_sld_w_w_w_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction { return Instruction{mnemonic = .SLD_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_gpr(src2), {}}} }
emit_sld_w_w_w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) { append(instructions, inst_sld_w_w_w_r(dst, src, src2)) }
inst_sld_d_w_w_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction { return Instruction{mnemonic = .SLD_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_gpr(src2), {}}} }
emit_sld_d_w_w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) { append(instructions, inst_sld_d_w_w_r(dst, src, src2)) }
inst_sldi_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLDI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_sldi_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sldi_b_w_w_i5(dst, src, imm)) }
inst_sldi_h_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLDI_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_sldi_h_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sldi_h_w_w_i5(dst, src, imm)) }
inst_sldi_w_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLDI_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_sldi_w_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sldi_w_w_w_i5(dst, src, imm)) }
inst_sldi_d_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLDI_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_sldi_d_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sldi_d_w_w_i5(dst, src, imm)) }
inst_splat_b_w_w_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction { return Instruction{mnemonic = .SPLAT_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_gpr(src2), {}}} }
emit_splat_b_w_w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) { append(instructions, inst_splat_b_w_w_r(dst, src, src2)) }
inst_splat_h_w_w_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction { return Instruction{mnemonic = .SPLAT_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_gpr(src2), {}}} }
emit_splat_h_w_w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) { append(instructions, inst_splat_h_w_w_r(dst, src, src2)) }
inst_splat_w_w_w_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction { return Instruction{mnemonic = .SPLAT_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_gpr(src2), {}}} }
emit_splat_w_w_w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) { append(instructions, inst_splat_w_w_w_r(dst, src, src2)) }
inst_splat_d_w_w_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: GPR) -> Instruction { return Instruction{mnemonic = .SPLAT_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_gpr(src2), {}}} }
emit_splat_d_w_w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: GPR) { append(instructions, inst_splat_d_w_w_r(dst, src, src2)) }
inst_splati_b_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SPLATI_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_splati_b_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_splati_b_w_w_i5(dst, src, imm)) }
inst_splati_h_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SPLATI_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_splati_h_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_splati_h_w_w_i5(dst, src, imm)) }
inst_splati_w_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SPLATI_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_splati_w_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_splati_w_w_w_i5(dst, src, imm)) }
inst_splati_d_w_w_i5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SPLATI_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), {}}} }
emit_splati_d_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_splati_d_w_w_i5(dst, src, imm)) }
inst_nloc_b_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLOC_B, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
emit_nloc_b_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_nloc_b_w_w(dst, src)) }
inst_nloc_h_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLOC_H, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
@@ -2871,12 +2955,26 @@ inst_nor_v :: inst_nor_v_w_w_w
emit_nor_v :: emit_nor_v_w_w_w
inst_xor_v :: inst_xor_v_w_w_w
emit_xor_v :: emit_xor_v_w_w_w
inst_andi_b :: inst_andi_b_w_w_i5
emit_andi_b :: emit_andi_b_w_w_i5
inst_ori_b :: inst_ori_b_w_w_i5
emit_ori_b :: emit_ori_b_w_w_i5
inst_nori_b :: inst_nori_b_w_w_i5
emit_nori_b :: emit_nori_b_w_w_i5
inst_xori_b :: inst_xori_b_w_w_i5
emit_xori_b :: emit_xori_b_w_w_i5
inst_bsel_v :: inst_bsel_v_w_w_w
emit_bsel_v :: emit_bsel_v_w_w_w
inst_bseli_b :: inst_bseli_b_w_w_i5
emit_bseli_b :: emit_bseli_b_w_w_i5
inst_bmnz_v :: inst_bmnz_v_w_w_w
emit_bmnz_v :: emit_bmnz_v_w_w_w
inst_bmnzi_b :: inst_bmnzi_b_w_w_i5
emit_bmnzi_b :: emit_bmnzi_b_w_w_i5
inst_bmz_v :: inst_bmz_v_w_w_w
emit_bmz_v :: emit_bmz_v_w_w_w
inst_bmzi_b :: inst_bmzi_b_w_w_i5
emit_bmzi_b :: emit_bmzi_b_w_w_i5
inst_ceq_b :: inst_ceq_b_w_w_w
emit_ceq_b :: emit_ceq_b_w_w_w
inst_ceq_h :: inst_ceq_h_w_w_w
@@ -2973,6 +3071,30 @@ inst_sra_w :: inst_sra_w_w_w_w
emit_sra_w :: emit_sra_w_w_w_w
inst_sra_d :: inst_sra_d_w_w_w
emit_sra_d :: emit_sra_d_w_w_w
inst_slli_b :: inst_slli_b_w_w_i5
emit_slli_b :: emit_slli_b_w_w_i5
inst_slli_h :: inst_slli_h_w_w_i5
emit_slli_h :: emit_slli_h_w_w_i5
inst_slli_w :: inst_slli_w_w_w_i5
emit_slli_w :: emit_slli_w_w_w_i5
inst_slli_d :: inst_slli_d_w_w_i5
emit_slli_d :: emit_slli_d_w_w_i5
inst_srli_b :: inst_srli_b_w_w_i5
emit_srli_b :: emit_srli_b_w_w_i5
inst_srli_h :: inst_srli_h_w_w_i5
emit_srli_h :: emit_srli_h_w_w_i5
inst_srli_w :: inst_srli_w_w_w_i5
emit_srli_w :: emit_srli_w_w_w_i5
inst_srli_d :: inst_srli_d_w_w_i5
emit_srli_d :: emit_srli_d_w_w_i5
inst_srai_b :: inst_srai_b_w_w_i5
emit_srai_b :: emit_srai_b_w_w_i5
inst_srai_h :: inst_srai_h_w_w_i5
emit_srai_h :: emit_srai_h_w_w_i5
inst_srai_w :: inst_srai_w_w_w_i5
emit_srai_w :: emit_srai_w_w_w_i5
inst_srai_d :: inst_srai_d_w_w_i5
emit_srai_d :: emit_srai_d_w_w_i5
inst_fadd_w :: inst_fadd_w_w_w_w
emit_fadd_w :: emit_fadd_w_w_w_w
inst_fadd_d :: inst_fadd_d_w_w_w
@@ -3069,6 +3191,52 @@ inst_ldi_w :: inst_ldi_w_w_i5
emit_ldi_w :: emit_ldi_w_w_i5
inst_ldi_d :: inst_ldi_d_w_i5
emit_ldi_d :: emit_ldi_d_w_i5
inst_shf_b :: inst_shf_b_w_w_i5
emit_shf_b :: emit_shf_b_w_w_i5
inst_shf_h :: inst_shf_h_w_w_i5
emit_shf_h :: emit_shf_h_w_w_i5
inst_shf_w :: inst_shf_w_w_w_i5
emit_shf_w :: emit_shf_w_w_w_i5
inst_vshf_b :: inst_vshf_b_w_w_w
emit_vshf_b :: emit_vshf_b_w_w_w
inst_vshf_h :: inst_vshf_h_w_w_w
emit_vshf_h :: emit_vshf_h_w_w_w
inst_vshf_w :: inst_vshf_w_w_w_w
emit_vshf_w :: emit_vshf_w_w_w_w
inst_vshf_d :: inst_vshf_d_w_w_w
emit_vshf_d :: emit_vshf_d_w_w_w
inst_sld_b :: inst_sld_b_w_w_r
emit_sld_b :: emit_sld_b_w_w_r
inst_sld_h :: inst_sld_h_w_w_r
emit_sld_h :: emit_sld_h_w_w_r
inst_sld_w :: inst_sld_w_w_w_r
emit_sld_w :: emit_sld_w_w_w_r
inst_sld_d :: inst_sld_d_w_w_r
emit_sld_d :: emit_sld_d_w_w_r
inst_sldi_b :: inst_sldi_b_w_w_i5
emit_sldi_b :: emit_sldi_b_w_w_i5
inst_sldi_h :: inst_sldi_h_w_w_i5
emit_sldi_h :: emit_sldi_h_w_w_i5
inst_sldi_w :: inst_sldi_w_w_w_i5
emit_sldi_w :: emit_sldi_w_w_w_i5
inst_sldi_d :: inst_sldi_d_w_w_i5
emit_sldi_d :: emit_sldi_d_w_w_i5
inst_splat_b :: inst_splat_b_w_w_r
emit_splat_b :: emit_splat_b_w_w_r
inst_splat_h :: inst_splat_h_w_w_r
emit_splat_h :: emit_splat_h_w_w_r
inst_splat_w :: inst_splat_w_w_w_r
emit_splat_w :: emit_splat_w_w_w_r
inst_splat_d :: inst_splat_d_w_w_r
emit_splat_d :: emit_splat_d_w_w_r
inst_splati_b :: inst_splati_b_w_w_i5
emit_splati_b :: emit_splati_b_w_w_i5
inst_splati_h :: inst_splati_h_w_w_i5
emit_splati_h :: emit_splati_h_w_w_i5
inst_splati_w :: inst_splati_w_w_w_i5
emit_splati_w :: emit_splati_w_w_w_i5
inst_splati_d :: inst_splati_d_w_w_i5
emit_splati_d :: emit_splati_d_w_w_i5
inst_nloc_b :: inst_nloc_b_w_w
emit_nloc_b :: emit_nloc_b_w_w
inst_nloc_h :: inst_nloc_h_w_w

42
core/rexcode/mips/tablegen/encoding_table.odin
View File

@@ -1509,5 +1509,47 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
.FFINT_S_D = { {.FFINT_S_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3D001E, 0xFFFF003F, .MSA, {}} },
.FFINT_U_W = { {.FFINT_U_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3E001E, 0xFFFF003F, .MSA, {}} },
.FFINT_U_D = { {.FFINT_U_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3F001E, 0xFFFF003F, .MSA, {}} },
.SLLI_B = { {.SLLI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78700009, 0xFFF8003F, .MSA, {}} },
.SLLI_H = { {.SLLI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78600009, 0xFFF0003F, .MSA, {}} },
.SLLI_W = { {.SLLI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78400009, 0xFFE0003F, .MSA, {}} },
.SLLI_D = { {.SLLI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78000009, 0xFFC0003F, .MSA, {}} },
.SRAI_B = { {.SRAI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78F00009, 0xFFF8003F, .MSA, {}} },
.SRAI_H = { {.SRAI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78E00009, 0xFFF0003F, .MSA, {}} },
.SRAI_W = { {.SRAI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78C00009, 0xFFE0003F, .MSA, {}} },
.SRAI_D = { {.SRAI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78800009, 0xFFC0003F, .MSA, {}} },
.SRLI_B = { {.SRLI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79700009, 0xFFF8003F, .MSA, {}} },
.SRLI_H = { {.SRLI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79600009, 0xFFF0003F, .MSA, {}} },
.SRLI_W = { {.SRLI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79400009, 0xFFE0003F, .MSA, {}} },
.SRLI_D = { {.SRLI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79000009, 0xFFC0003F, .MSA, {}} },
.SPLATI_B = { {.SPLATI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78400019, 0xFFF0003F, .MSA, {}} },
.SPLATI_H = { {.SPLATI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78600019, 0xFFF8003F, .MSA, {}} },
.SPLATI_W = { {.SPLATI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78700019, 0xFFFC003F, .MSA, {}} },
.SPLATI_D = { {.SPLATI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78780019, 0xFFFE003F, .MSA, {}} },
.SLDI_B = { {.SLDI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78000019, 0xFFF0003F, .MSA, {}} },
.SLDI_H = { {.SLDI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78200019, 0xFFF8003F, .MSA, {}} },
.SLDI_W = { {.SLDI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78300019, 0xFFFC003F, .MSA, {}} },
.SLDI_D = { {.SLDI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78380019, 0xFFFE003F, .MSA, {}} },
.VSHF_B = { {.VSHF_B, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78000015, 0xFFE0003F, .MSA, {}} },
.VSHF_H = { {.VSHF_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78200015, 0xFFE0003F, .MSA, {}} },
.VSHF_W = { {.VSHF_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78400015, 0xFFE0003F, .MSA, {}} },
.VSHF_D = { {.VSHF_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78600015, 0xFFE0003F, .MSA, {}} },
.SPLAT_B = { {.SPLAT_B, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78800014, 0xFFE0003F, .MSA, {}} },
.SPLAT_H = { {.SPLAT_H, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78A00014, 0xFFE0003F, .MSA, {}} },
.SPLAT_W = { {.SPLAT_W, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78C00014, 0xFFE0003F, .MSA, {}} },
.SPLAT_D = { {.SPLAT_D, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78E00014, 0xFFE0003F, .MSA, {}} },
.SLD_B = { {.SLD_B, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78000014, 0xFFE0003F, .MSA, {}} },
.SLD_H = { {.SLD_H, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78200014, 0xFFE0003F, .MSA, {}} },
.SLD_W = { {.SLD_W, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78400014, 0xFFE0003F, .MSA, {}} },
.SLD_D = { {.SLD_D, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78600014, 0xFFE0003F, .MSA, {}} },
.ANDI_B = { {.ANDI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x78000000, 0xFF00003F, .MSA, {}} },
.ORI_B = { {.ORI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x79000000, 0xFF00003F, .MSA, {}} },
.XORI_B = { {.XORI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7B000000, 0xFF00003F, .MSA, {}} },
.NORI_B = { {.NORI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7A000000, 0xFF00003F, .MSA, {}} },
.BMNZI_B = { {.BMNZI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x78000001, 0xFF00003F, .MSA, {}} },
.BMZI_B = { {.BMZI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x79000001, 0xFF00003F, .MSA, {}} },
.BSELI_B = { {.BSELI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7A000001, 0xFF00003F, .MSA, {}} },
.SHF_B = { {.SHF_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x78000002, 0xFF00003F, .MSA, {}} },
.SHF_H = { {.SHF_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x79000002, 0xFF00003F, .MSA, {}} },
.SHF_W = { {.SHF_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7A000002, 0xFF00003F, .MSA, {}} },
// SPECGEN:END
}

148
core/rexcode/mips/tablegen/generated/decode_tables.odin
View File

@@ -8,7 +8,7 @@ package rexcode_mips_generated
import lib "../.."
@(rodata)
DECODE_ENTRIES := [840]lib.Decode_Entry{
DECODE_ENTRIES := [882]lib.Decode_Entry{
{ .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00000000, 0xFFFFFFFF, .MIPS_I, {} },
{ .SSNOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00000040, 0xFFFFFFFF, .MIPS32_R1, {} },
{ .EHB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x000000C0, 0xFFFFFFFF, .MIPS32_R2, {} },
@@ -480,6 +480,20 @@ DECODE_ENTRIES := [840]lib.Decode_Entry{
{ .PCNT_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B05001E, 0xFFFF003F, .MSA, {} },
{ .PCNT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B06001E, 0xFFFF003F, .MSA, {} },
{ .PCNT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B07001E, 0xFFFF003F, .MSA, {} },
{ .SLDI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78380019, 0xFFFE003F, .MSA, {} },
{ .SPLATI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78780019, 0xFFFE003F, .MSA, {} },
{ .SLDI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78300019, 0xFFFC003F, .MSA, {} },
{ .SPLATI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78700019, 0xFFFC003F, .MSA, {} },
{ .SLLI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78700009, 0xFFF8003F, .MSA, {} },
{ .SRLI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79700009, 0xFFF8003F, .MSA, {} },
{ .SRAI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78F00009, 0xFFF8003F, .MSA, {} },
{ .SLDI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78200019, 0xFFF8003F, .MSA, {} },
{ .SPLATI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78600019, 0xFFF8003F, .MSA, {} },
{ .SLLI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78600009, 0xFFF0003F, .MSA, {} },
{ .SRLI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79600009, 0xFFF0003F, .MSA, {} },
{ .SRAI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78E00009, 0xFFF0003F, .MSA, {} },
{ .SLDI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78000019, 0xFFF0003F, .MSA, {} },
{ .SPLATI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78400019, 0xFFF0003F, .MSA, {} },
{ .ADDV_B, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800000E, 0xFFE0003F, .MSA, {} },
{ .ADDV_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7820000E, 0xFFE0003F, .MSA, {} },
{ .ADDV_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840000E, 0xFFE0003F, .MSA, {} },
@@ -593,6 +607,9 @@ DECODE_ENTRIES := [840]lib.Decode_Entry{
{ .SRA_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0000D, 0xFFE0003F, .MSA, {} },
{ .SRA_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0000D, 0xFFE0003F, .MSA, {} },
{ .SRA_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0000D, 0xFFE0003F, .MSA, {} },
{ .SLLI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78400009, 0xFFE0003F, .MSA, {} },
{ .SRLI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79400009, 0xFFE0003F, .MSA, {} },
{ .SRAI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78C00009, 0xFFE0003F, .MSA, {} },
{ .FADD_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800001B, 0xFFE0003F, .MSA, {} },
{ .FADD_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7820001B, 0xFFE0003F, .MSA, {} },
{ .FSUB_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840001B, 0xFFE0003F, .MSA, {} },
@@ -617,6 +634,31 @@ DECODE_ENTRIES := [840]lib.Decode_Entry{
{ .LDI_H, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B200007, 0xFFE0003F, .MSA, {} },
{ .LDI_W, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B400007, 0xFFE0003F, .MSA, {} },
{ .LDI_D, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B600007, 0xFFE0003F, .MSA, {} },
{ .VSHF_B, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78000015, 0xFFE0003F, .MSA, {} },
{ .VSHF_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78200015, 0xFFE0003F, .MSA, {} },
{ .VSHF_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78400015, 0xFFE0003F, .MSA, {} },
{ .VSHF_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78600015, 0xFFE0003F, .MSA, {} },
{ .SLD_B, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78000014, 0xFFE0003F, .MSA, {} },
{ .SLD_H, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78200014, 0xFFE0003F, .MSA, {} },
{ .SLD_W, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78400014, 0xFFE0003F, .MSA, {} },
{ .SLD_D, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78600014, 0xFFE0003F, .MSA, {} },
{ .SPLAT_B, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78800014, 0xFFE0003F, .MSA, {} },
{ .SPLAT_H, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78A00014, 0xFFE0003F, .MSA, {} },
{ .SPLAT_W, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78C00014, 0xFFE0003F, .MSA, {} },
{ .SPLAT_D, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78E00014, 0xFFE0003F, .MSA, {} },
{ .SLLI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78000009, 0xFFC0003F, .MSA, {} },
{ .SRLI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79000009, 0xFFC0003F, .MSA, {} },
{ .SRAI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78800009, 0xFFC0003F, .MSA, {} },
{ .ANDI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x78000000, 0xFF00003F, .MSA, {} },
{ .ORI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x79000000, 0xFF00003F, .MSA, {} },
{ .NORI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7A000000, 0xFF00003F, .MSA, {} },
{ .XORI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7B000000, 0xFF00003F, .MSA, {} },
{ .BSELI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7A000001, 0xFF00003F, .MSA, {} },
{ .BMNZI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x78000001, 0xFF00003F, .MSA, {} },
{ .BMZI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x79000001, 0xFF00003F, .MSA, {} },
{ .SHF_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x78000002, 0xFF00003F, .MSA, {} },
{ .SHF_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x79000002, 0xFF00003F, .MSA, {} },
{ .SHF_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7A000002, 0xFF00003F, .MSA, {} },
{ .LD_B, {.MSA_VEC,.MEM,.NONE,.NONE}, {.WD,.MSA_OFFSET_BASE_B,.NONE,.NONE}, 0x78000020, 0xFC00003F, .MSA, {} },
{ .LD_H, {.MSA_VEC,.MEM,.NONE,.NONE}, {.WD,.MSA_OFFSET_BASE_H,.NONE,.NONE}, 0x78000021, 0xFC00003F, .MSA, {} },
{ .LD_W, {.MSA_VEC,.MEM,.NONE,.NONE}, {.WD,.MSA_OFFSET_BASE_W,.NONE,.NONE}, 0x78000022, 0xFC00003F, .MSA, {} },
@@ -883,40 +925,40 @@ DECODE_INDEX_PRIMARY := [64]lib.Decode_Index{
0x1B = { 320, 13},
0x1C = { 333, 109},
0x1D = { 442, 1},
0x1E = { 443, 174},
0x1F = { 617, 78},
0x20 = { 695, 1},
0x21 = { 696, 1},
0x22 = { 697, 1},
0x23 = { 698, 1},
0x24 = { 699, 1},
0x25 = { 700, 1},
0x26 = { 701, 1},
0x27 = { 702, 1},
0x28 = { 703, 1},
0x29 = { 704, 1},
0x2A = { 705, 1},
0x2B = { 706, 1},
0x2C = { 707, 1},
0x2D = { 708, 1},
0x2E = { 709, 1},
0x2F = { 710, 1},
0x30 = { 711, 1},
0x31 = { 712, 1},
0x32 = { 713, 3},
0x33 = { 716, 1},
0x34 = { 717, 63},
0x35 = { 780, 3},
0x36 = { 783, 5},
0x37 = { 788, 6},
0x38 = { 794, 1},
0x39 = { 795, 1},
0x3A = { 796, 3},
0x3B = { 799, 2},
0x3C = { 801, 27},
0x3D = { 828, 3},
0x3E = { 831, 5},
0x3F = { 836, 4},
0x1E = { 443, 216},
0x1F = { 659, 78},
0x20 = { 737, 1},
0x21 = { 738, 1},
0x22 = { 739, 1},
0x23 = { 740, 1},
0x24 = { 741, 1},
0x25 = { 742, 1},
0x26 = { 743, 1},
0x27 = { 744, 1},
0x28 = { 745, 1},
0x29 = { 746, 1},
0x2A = { 747, 1},
0x2B = { 748, 1},
0x2C = { 749, 1},
0x2D = { 750, 1},
0x2E = { 751, 1},
0x2F = { 752, 1},
0x30 = { 753, 1},
0x31 = { 754, 1},
0x32 = { 755, 3},
0x33 = { 758, 1},
0x34 = { 759, 63},
0x35 = { 822, 3},
0x36 = { 825, 5},
0x37 = { 830, 6},
0x38 = { 836, 1},
0x39 = { 837, 1},
0x3A = { 838, 3},
0x3B = { 841, 2},
0x3C = { 843, 27},
0x3D = { 870, 3},
0x3E = { 873, 5},
0x3F = { 878, 4},
}
@(rodata)
@@ -1063,23 +1105,23 @@ DECODE_INDEX_SPECIAL2 := [64]lib.Decode_Index{
@(rodata)
DECODE_INDEX_SPECIAL3 := [64]lib.Decode_Index{
0x00 = { 617, 2},
0x01 = { 619, 1},
0x02 = { 620, 1},
0x03 = { 621, 1},
0x04 = { 622, 1},
0x05 = { 623, 1},
0x06 = { 624, 1},
0x07 = { 625, 1},
0x0A = { 626, 3},
0x0C = { 629, 1},
0x0F = { 630, 8},
0x10 = { 638, 12},
0x12 = { 650, 9},
0x13 = { 659, 9},
0x20 = { 668, 5},
0x24 = { 673, 4},
0x30 = { 677, 9},
0x38 = { 686, 9},
0x00 = { 659, 2},
0x01 = { 661, 1},
0x02 = { 662, 1},
0x03 = { 663, 1},
0x04 = { 664, 1},
0x05 = { 665, 1},
0x06 = { 666, 1},
0x07 = { 667, 1},
0x0A = { 668, 3},
0x0C = { 671, 1},
0x0F = { 672, 8},
0x10 = { 680, 12},
0x12 = { 692, 9},
0x13 = { 701, 9},
0x20 = { 710, 5},
0x24 = { 715, 4},
0x30 = { 719, 9},
0x38 = { 728, 9},
}

746
core/rexcode/mips/tablegen/generated/encode_tables.odin
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@@ -8,7 +8,7 @@ package rexcode_mips_generated
import lib "../.."
@(rodata)
ENCODE_FORMS := [840]lib.Encoding{
ENCODE_FORMS := [882]lib.Encoding{
// .ADD
{ .ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000020, 0xFC0007FF, .MIPS_I, {} },
// .ADDU
@@ -1167,12 +1167,26 @@ ENCODE_FORMS := [840]lib.Encoding{
{ .NOR_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840001E, 0xFFE0003F, .MSA, {} },
// .XOR_V
{ .XOR_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7860001E, 0xFFE0003F, .MSA, {} },
// .ANDI_B
{ .ANDI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x78000000, 0xFF00003F, .MSA, {} },
// .ORI_B
{ .ORI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x79000000, 0xFF00003F, .MSA, {} },
// .NORI_B
{ .NORI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7A000000, 0xFF00003F, .MSA, {} },
// .XORI_B
{ .XORI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7B000000, 0xFF00003F, .MSA, {} },
// .BSEL_V
{ .BSEL_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001E, 0xFFE0003F, .MSA, {} },
// .BSELI_B
{ .BSELI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7A000001, 0xFF00003F, .MSA, {} },
// .BMNZ_V
{ .BMNZ_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001E, 0xFFE0003F, .MSA, {} },
// .BMNZI_B
{ .BMNZI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x78000001, 0xFF00003F, .MSA, {} },
// .BMZ_V
{ .BMZ_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001E, 0xFFE0003F, .MSA, {} },
// .BMZI_B
{ .BMZI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x79000001, 0xFF00003F, .MSA, {} },
// .CEQ_B
{ .CEQ_B, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800000F, 0xFFE0003F, .MSA, {} },
// .CEQ_H
@@ -1269,6 +1283,30 @@ ENCODE_FORMS := [840]lib.Encoding{
{ .SRA_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0000D, 0xFFE0003F, .MSA, {} },
// .SRA_D
{ .SRA_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0000D, 0xFFE0003F, .MSA, {} },
// .SLLI_B
{ .SLLI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78700009, 0xFFF8003F, .MSA, {} },
// .SLLI_H
{ .SLLI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78600009, 0xFFF0003F, .MSA, {} },
// .SLLI_W
{ .SLLI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78400009, 0xFFE0003F, .MSA, {} },
// .SLLI_D
{ .SLLI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78000009, 0xFFC0003F, .MSA, {} },
// .SRLI_B
{ .SRLI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79700009, 0xFFF8003F, .MSA, {} },
// .SRLI_H
{ .SRLI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79600009, 0xFFF0003F, .MSA, {} },
// .SRLI_W
{ .SRLI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79400009, 0xFFE0003F, .MSA, {} },
// .SRLI_D
{ .SRLI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x79000009, 0xFFC0003F, .MSA, {} },
// .SRAI_B
{ .SRAI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78F00009, 0xFFF8003F, .MSA, {} },
// .SRAI_H
{ .SRAI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78E00009, 0xFFF0003F, .MSA, {} },
// .SRAI_W
{ .SRAI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78C00009, 0xFFE0003F, .MSA, {} },
// .SRAI_D
{ .SRAI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_BIT_SHIFT,.NONE}, 0x78800009, 0xFFC0003F, .MSA, {} },
// .FADD_W
{ .FADD_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800001B, 0xFFE0003F, .MSA, {} },
// .FADD_D
@@ -1365,6 +1403,52 @@ ENCODE_FORMS := [840]lib.Encoding{
{ .LDI_W, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B400007, 0xFFE0003F, .MSA, {} },
// .LDI_D
{ .LDI_D, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B600007, 0xFFE0003F, .MSA, {} },
// .SHF_B
{ .SHF_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x78000002, 0xFF00003F, .MSA, {} },
// .SHF_H
{ .SHF_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x79000002, 0xFF00003F, .MSA, {} },
// .SHF_W
{ .SHF_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_I8,.NONE}, 0x7A000002, 0xFF00003F, .MSA, {} },
// .VSHF_B
{ .VSHF_B, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78000015, 0xFFE0003F, .MSA, {} },
// .VSHF_H
{ .VSHF_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78200015, 0xFFE0003F, .MSA, {} },
// .VSHF_W
{ .VSHF_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78400015, 0xFFE0003F, .MSA, {} },
// .VSHF_D
{ .VSHF_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78600015, 0xFFE0003F, .MSA, {} },
// .SLD_B
{ .SLD_B, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78000014, 0xFFE0003F, .MSA, {} },
// .SLD_H
{ .SLD_H, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78200014, 0xFFE0003F, .MSA, {} },
// .SLD_W
{ .SLD_W, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78400014, 0xFFE0003F, .MSA, {} },
// .SLD_D
{ .SLD_D, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78600014, 0xFFE0003F, .MSA, {} },
// .SLDI_B
{ .SLDI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78000019, 0xFFF0003F, .MSA, {} },
// .SLDI_H
{ .SLDI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78200019, 0xFFF8003F, .MSA, {} },
// .SLDI_W
{ .SLDI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78300019, 0xFFFC003F, .MSA, {} },
// .SLDI_D
{ .SLDI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78380019, 0xFFFE003F, .MSA, {} },
// .SPLAT_B
{ .SPLAT_B, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78800014, 0xFFE0003F, .MSA, {} },
// .SPLAT_H
{ .SPLAT_H, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78A00014, 0xFFE0003F, .MSA, {} },
// .SPLAT_W
{ .SPLAT_W, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78C00014, 0xFFE0003F, .MSA, {} },
// .SPLAT_D
{ .SPLAT_D, {.MSA_VEC,.MSA_VEC,.GPR,.NONE}, {.WD,.WS,.RT,.NONE}, 0x78E00014, 0xFFE0003F, .MSA, {} },
// .SPLATI_B
{ .SPLATI_B, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78400019, 0xFFF0003F, .MSA, {} },
// .SPLATI_H
{ .SPLATI_H, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78600019, 0xFFF8003F, .MSA, {} },
// .SPLATI_W
{ .SPLATI_W, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78700019, 0xFFFC003F, .MSA, {} },
// .SPLATI_D
{ .SPLATI_D, {.MSA_VEC,.MSA_VEC,.IMM5,.NONE}, {.WD,.WS,.MSA_ELM_IDX,.NONE}, 0x78780019, 0xFFFE003F, .MSA, {} },
// .NLOC_B
{ .NLOC_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B08001E, 0xFFFF003F, .MSA, {} },
// .NLOC_H
@@ -2391,334 +2475,334 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
.OR_V = { 576, 1},
.NOR_V = { 577, 1},
.XOR_V = { 578, 1},
.ANDI_B = { 579, 0},
.ORI_B = { 579, 0},
.NORI_B = { 579, 0},
.XORI_B = { 579, 0},
.BSEL_V = { 579, 1},
.BSELI_B = { 580, 0},
.BMNZ_V = { 580, 1},
.BMNZI_B = { 581, 0},
.BMZ_V = { 581, 1},
.BMZI_B = { 582, 0},
.CEQ_B = { 582, 1},
.CEQ_H = { 583, 1},
.CEQ_W = { 584, 1},
.CEQ_D = { 585, 1},
.CLT_S_B = { 586, 1},
.CLT_S_H = { 587, 1},
.CLT_S_W = { 588, 1},
.CLT_S_D = { 589, 1},
.CLT_U_B = { 590, 1},
.CLT_U_H = { 591, 1},
.CLT_U_W = { 592, 1},
.CLT_U_D = { 593, 1},
.CLE_S_B = { 594, 1},
.CLE_S_H = { 595, 1},
.CLE_S_W = { 596, 1},
.CLE_S_D = { 597, 1},
.CLE_U_B = { 598, 1},
.CLE_U_H = { 599, 1},
.CLE_U_W = { 600, 1},
.CLE_U_D = { 601, 1},
.MIN_S_B = { 602, 1},
.MIN_S_H = { 603, 1},
.MIN_S_W = { 604, 1},
.MIN_S_D = { 605, 1},
.MIN_U_B = { 606, 1},
.MIN_U_H = { 607, 1},
.MIN_U_W = { 608, 1},
.MIN_U_D = { 609, 1},
.MAX_S_B = { 610, 1},
.MAX_S_H = { 611, 1},
.MAX_S_W = { 612, 1},
.MAX_S_D = { 613, 1},
.MAX_U_B = { 614, 1},
.MAX_U_H = { 615, 1},
.MAX_U_W = { 616, 1},
.MAX_U_D = { 617, 1},
.SLL_B = { 618, 1},
.SLL_H = { 619, 1},
.SLL_W = { 620, 1},
.SLL_D = { 621, 1},
.SRL_B = { 622, 1},
.SRL_H = { 623, 1},
.SRL_W = { 624, 1},
.SRL_D = { 625, 1},
.SRA_B = { 626, 1},
.SRA_H = { 627, 1},
.SRA_W = { 628, 1},
.SRA_D = { 629, 1},
.SLLI_B = { 630, 0},
.SLLI_H = { 630, 0},
.SLLI_W = { 630, 0},
.SLLI_D = { 630, 0},
.SRLI_B = { 630, 0},
.SRLI_H = { 630, 0},
.SRLI_W = { 630, 0},
.SRLI_D = { 630, 0},
.SRAI_B = { 630, 0},
.SRAI_H = { 630, 0},
.SRAI_W = { 630, 0},
.SRAI_D = { 630, 0},
.FADD_W = { 630, 1},
.FADD_D = { 631, 1},
.FSUB_W = { 632, 1},
.FSUB_D = { 633, 1},
.FMUL_W = { 634, 1},
.FMUL_D = { 635, 1},
.FDIV_W = { 636, 1},
.FDIV_D = { 637, 1},
.FSQRT_W = { 638, 1},
.FSQRT_D = { 639, 1},
.FRSQRT_W = { 640, 1},
.FRSQRT_D = { 641, 1},
.FRCP_W = { 642, 1},
.FRCP_D = { 643, 1},
.FRINT_W = { 644, 1},
.FRINT_D = { 645, 1},
.FMAX_W = { 646, 1},
.FMAX_D = { 647, 1},
.FMIN_W = { 648, 1},
.FMIN_D = { 649, 1},
.FCEQ_W = { 650, 1},
.FCEQ_D = { 651, 1},
.FCNE_W = { 652, 1},
.FCNE_D = { 653, 1},
.FCLT_W = { 654, 1},
.FCLT_D = { 655, 1},
.FCLE_W = { 656, 1},
.FCLE_D = { 657, 1},
.FFINT_S_W = { 658, 1},
.FFINT_S_D = { 659, 1},
.FFINT_U_W = { 660, 1},
.FFINT_U_D = { 661, 1},
.FTRUNC_S_W = { 662, 1},
.FTRUNC_S_D = { 663, 1},
.FTRUNC_U_W = { 664, 1},
.FTRUNC_U_D = { 665, 1},
.FCVT_S_W = { 666, 0},
.FCVT_S_D = { 666, 0},
.FCVT_D_W = { 666, 0},
.LD_B = { 666, 1},
.LD_H = { 667, 1},
.LD_W = { 668, 1},
.LD_D = { 669, 1},
.ST_B = { 670, 1},
.ST_H = { 671, 1},
.ST_W = { 672, 1},
.ST_D = { 673, 1},
.LDI_B = { 674, 1},
.LDI_H = { 675, 1},
.LDI_W = { 676, 1},
.LDI_D = { 677, 1},
.COPY_S_B = { 678, 0},
.COPY_S_H = { 678, 0},
.COPY_S_W = { 678, 0},
.COPY_U_B = { 678, 0},
.COPY_U_H = { 678, 0},
.COPY_U_W = { 678, 0},
.INSERT_B = { 678, 0},
.INSERT_H = { 678, 0},
.INSERT_W = { 678, 0},
.INSERT_D = { 678, 0},
.INSVE_B = { 678, 0},
.INSVE_H = { 678, 0},
.INSVE_W = { 678, 0},
.INSVE_D = { 678, 0},
.SHF_B = { 678, 0},
.SHF_H = { 678, 0},
.SHF_W = { 678, 0},
.VSHF_B = { 678, 0},
.VSHF_H = { 678, 0},
.VSHF_W = { 678, 0},
.VSHF_D = { 678, 0},
.SLD_B = { 678, 0},
.SLD_H = { 678, 0},
.SLD_W = { 678, 0},
.SLD_D = { 678, 0},
.SLDI_B = { 678, 0},
.SLDI_H = { 678, 0},
.SLDI_W = { 678, 0},
.SLDI_D = { 678, 0},
.SPLAT_B = { 678, 0},
.SPLAT_H = { 678, 0},
.SPLAT_W = { 678, 0},
.SPLAT_D = { 678, 0},
.SPLATI_B = { 678, 0},
.SPLATI_H = { 678, 0},
.SPLATI_W = { 678, 0},
.SPLATI_D = { 678, 0},
.BZ_V = { 678, 0},
.BNZ_V = { 678, 0},
.BZ_B = { 678, 0},
.BZ_H = { 678, 0},
.BZ_W = { 678, 0},
.BZ_D = { 678, 0},
.BNZ_B = { 678, 0},
.BNZ_H = { 678, 0},
.BNZ_W = { 678, 0},
.BNZ_D = { 678, 0},
.NLOC_B = { 678, 1},
.NLOC_H = { 679, 1},
.NLOC_W = { 680, 1},
.NLOC_D = { 681, 1},
.NLZC_B = { 682, 1},
.NLZC_H = { 683, 1},
.NLZC_W = { 684, 1},
.NLZC_D = { 685, 1},
.PCNT_B = { 686, 1},
.PCNT_H = { 687, 1},
.PCNT_W = { 688, 1},
.PCNT_D = { 689, 1},
.VMOV_S = { 690, 1},
.VMOV_P = { 691, 1},
.VMOV_T = { 692, 1},
.VMOV_Q = { 693, 1},
.LV_S = { 694, 1},
.LV_Q = { 695, 1},
.SV_S = { 696, 1},
.SV_Q = { 697, 1},
.LVL_Q = { 698, 1},
.LVR_Q = { 699, 1},
.SVL_Q = { 700, 1},
.SVR_Q = { 701, 1},
.VIIM_S = { 702, 1},
.VFIM_S = { 703, 1},
.VADD_S = { 704, 1},
.VADD_P = { 705, 1},
.VADD_T = { 706, 1},
.VADD_Q = { 707, 1},
.VSUB_S = { 708, 1},
.VSUB_P = { 709, 1},
.VSUB_T = { 710, 1},
.VSUB_Q = { 711, 1},
.VMUL_S = { 712, 1},
.VMUL_P = { 713, 1},
.VMUL_T = { 714, 1},
.VMUL_Q = { 715, 1},
.VDIV_S = { 716, 1},
.VDIV_P = { 717, 1},
.VDIV_T = { 718, 1},
.VDIV_Q = { 719, 1},
.VABS_S = { 720, 1},
.VABS_P = { 721, 1},
.VABS_T = { 722, 1},
.VABS_Q = { 723, 1},
.VNEG_S = { 724, 1},
.VNEG_P = { 725, 1},
.VNEG_T = { 726, 1},
.VNEG_Q = { 727, 1},
.VSQRT_S = { 728, 1},
.VRCP_S = { 729, 1},
.VRCP_P = { 730, 1},
.VRCP_T = { 731, 1},
.VRCP_Q = { 732, 1},
.VRSQ_S = { 733, 1},
.VRSQ_P = { 734, 1},
.VRSQ_T = { 735, 1},
.VRSQ_Q = { 736, 1},
.VDOT_P = { 737, 1},
.VDOT_T = { 738, 1},
.VDOT_Q = { 739, 1},
.VSCL_P = { 740, 1},
.VSCL_T = { 741, 1},
.VSCL_Q = { 742, 1},
.VHDP_P = { 743, 1},
.VHDP_T = { 744, 1},
.VHDP_Q = { 745, 1},
.VAVG_P = { 746, 1},
.VAVG_T = { 747, 1},
.VAVG_Q = { 748, 1},
.VFAD_P = { 749, 1},
.VFAD_T = { 750, 1},
.VFAD_Q = { 751, 1},
.VMMUL_P = { 752, 1},
.VMMUL_T = { 753, 1},
.VMMUL_Q = { 754, 1},
.VTFM2_P = { 755, 1},
.VTFM3_T = { 756, 1},
.VTFM4_Q = { 757, 1},
.VHTFM2_P = { 758, 1},
.VHTFM3_T = { 759, 1},
.VHTFM4_Q = { 760, 1},
.VMSCL_P = { 761, 1},
.VMSCL_T = { 762, 1},
.VMSCL_Q = { 763, 1},
.VMMOV_P = { 764, 1},
.VMMOV_T = { 765, 1},
.VMMOV_Q = { 766, 1},
.VMIDT_P = { 767, 1},
.VMIDT_T = { 768, 1},
.VMIDT_Q = { 769, 1},
.VMZERO_P = { 770, 1},
.VMZERO_T = { 771, 1},
.VMZERO_Q = { 772, 1},
.VMONE_P = { 773, 1},
.VMONE_T = { 774, 1},
.VMONE_Q = { 775, 1},
.VCRS_T = { 776, 1},
.VCRSP_T = { 777, 1},
.VQMUL_Q = { 778, 1},
.VCMP_S = { 779, 1},
.VCMP_P = { 780, 1},
.VCMP_T = { 781, 1},
.VCMP_Q = { 782, 1},
.VMIN_S = { 783, 1},
.VMIN_P = { 784, 1},
.VMIN_T = { 785, 1},
.VMIN_Q = { 786, 1},
.VMAX_S = { 787, 1},
.VMAX_P = { 788, 1},
.VMAX_T = { 789, 1},
.VMAX_Q = { 790, 1},
.VSIN_S = { 791, 1},
.VCOS_S = { 792, 1},
.VEXP2_S = { 793, 1},
.VLOG2_S = { 794, 1},
.VASIN_S = { 795, 1},
.VNRCP_S = { 796, 1},
.VNSIN_S = { 797, 1},
.VREXP2_S = { 798, 1},
.VSGN_S = { 799, 1},
.VI2F_S = { 800, 1},
.VI2F_P = { 801, 1},
.VI2F_T = { 802, 1},
.VI2F_Q = { 803, 1},
.VF2IN_S = { 804, 1},
.VF2IN_P = { 805, 1},
.VF2IN_T = { 806, 1},
.VF2IN_Q = { 807, 1},
.VF2IZ_S = { 808, 1},
.VF2IZ_P = { 809, 1},
.VF2IZ_T = { 810, 1},
.VF2IZ_Q = { 811, 1},
.VF2IU_S = { 812, 1},
.VF2IU_P = { 813, 1},
.VF2IU_T = { 814, 1},
.VF2IU_Q = { 815, 1},
.VF2ID_S = { 816, 1},
.VF2ID_P = { 817, 1},
.VF2ID_T = { 818, 1},
.VF2ID_Q = { 819, 1},
.VF2H_P = { 820, 1},
.VH2F_S = { 821, 1},
.VFLUSH = { 822, 1},
.VSYNC = { 823, 1},
.VNOP = { 824, 1},
.VPFXS = { 825, 1},
.VPFXT = { 826, 1},
.VPFXD = { 827, 1},
.VCST_S = { 828, 1},
.VCST_P = { 829, 1},
.VCST_T = { 830, 1},
.VCST_Q = { 831, 1},
.MFV = { 832, 1},
.MTV = { 833, 1},
.MFVC = { 834, 1},
.MTVC = { 835, 1},
.BVF = { 836, 1},
.BVT = { 837, 1},
.BVFL = { 838, 1},
.BVTL = { 839, 1},
.ANDI_B = { 579, 1},
.ORI_B = { 580, 1},
.NORI_B = { 581, 1},
.XORI_B = { 582, 1},
.BSEL_V = { 583, 1},
.BSELI_B = { 584, 1},
.BMNZ_V = { 585, 1},
.BMNZI_B = { 586, 1},
.BMZ_V = { 587, 1},
.BMZI_B = { 588, 1},
.CEQ_B = { 589, 1},
.CEQ_H = { 590, 1},
.CEQ_W = { 591, 1},
.CEQ_D = { 592, 1},
.CLT_S_B = { 593, 1},
.CLT_S_H = { 594, 1},
.CLT_S_W = { 595, 1},
.CLT_S_D = { 596, 1},
.CLT_U_B = { 597, 1},
.CLT_U_H = { 598, 1},
.CLT_U_W = { 599, 1},
.CLT_U_D = { 600, 1},
.CLE_S_B = { 601, 1},
.CLE_S_H = { 602, 1},
.CLE_S_W = { 603, 1},
.CLE_S_D = { 604, 1},
.CLE_U_B = { 605, 1},
.CLE_U_H = { 606, 1},
.CLE_U_W = { 607, 1},
.CLE_U_D = { 608, 1},
.MIN_S_B = { 609, 1},
.MIN_S_H = { 610, 1},
.MIN_S_W = { 611, 1},
.MIN_S_D = { 612, 1},
.MIN_U_B = { 613, 1},
.MIN_U_H = { 614, 1},
.MIN_U_W = { 615, 1},
.MIN_U_D = { 616, 1},
.MAX_S_B = { 617, 1},
.MAX_S_H = { 618, 1},
.MAX_S_W = { 619, 1},
.MAX_S_D = { 620, 1},
.MAX_U_B = { 621, 1},
.MAX_U_H = { 622, 1},
.MAX_U_W = { 623, 1},
.MAX_U_D = { 624, 1},
.SLL_B = { 625, 1},
.SLL_H = { 626, 1},
.SLL_W = { 627, 1},
.SLL_D = { 628, 1},
.SRL_B = { 629, 1},
.SRL_H = { 630, 1},
.SRL_W = { 631, 1},
.SRL_D = { 632, 1},
.SRA_B = { 633, 1},
.SRA_H = { 634, 1},
.SRA_W = { 635, 1},
.SRA_D = { 636, 1},
.SLLI_B = { 637, 1},
.SLLI_H = { 638, 1},
.SLLI_W = { 639, 1},
.SLLI_D = { 640, 1},
.SRLI_B = { 641, 1},
.SRLI_H = { 642, 1},
.SRLI_W = { 643, 1},
.SRLI_D = { 644, 1},
.SRAI_B = { 645, 1},
.SRAI_H = { 646, 1},
.SRAI_W = { 647, 1},
.SRAI_D = { 648, 1},
.FADD_W = { 649, 1},
.FADD_D = { 650, 1},
.FSUB_W = { 651, 1},
.FSUB_D = { 652, 1},
.FMUL_W = { 653, 1},
.FMUL_D = { 654, 1},
.FDIV_W = { 655, 1},
.FDIV_D = { 656, 1},
.FSQRT_W = { 657, 1},
.FSQRT_D = { 658, 1},
.FRSQRT_W = { 659, 1},
.FRSQRT_D = { 660, 1},
.FRCP_W = { 661, 1},
.FRCP_D = { 662, 1},
.FRINT_W = { 663, 1},
.FRINT_D = { 664, 1},
.FMAX_W = { 665, 1},
.FMAX_D = { 666, 1},
.FMIN_W = { 667, 1},
.FMIN_D = { 668, 1},
.FCEQ_W = { 669, 1},
.FCEQ_D = { 670, 1},
.FCNE_W = { 671, 1},
.FCNE_D = { 672, 1},
.FCLT_W = { 673, 1},
.FCLT_D = { 674, 1},
.FCLE_W = { 675, 1},
.FCLE_D = { 676, 1},
.FFINT_S_W = { 677, 1},
.FFINT_S_D = { 678, 1},
.FFINT_U_W = { 679, 1},
.FFINT_U_D = { 680, 1},
.FTRUNC_S_W = { 681, 1},
.FTRUNC_S_D = { 682, 1},
.FTRUNC_U_W = { 683, 1},
.FTRUNC_U_D = { 684, 1},
.FCVT_S_W = { 685, 0},
.FCVT_S_D = { 685, 0},
.FCVT_D_W = { 685, 0},
.LD_B = { 685, 1},
.LD_H = { 686, 1},
.LD_W = { 687, 1},
.LD_D = { 688, 1},
.ST_B = { 689, 1},
.ST_H = { 690, 1},
.ST_W = { 691, 1},
.ST_D = { 692, 1},
.LDI_B = { 693, 1},
.LDI_H = { 694, 1},
.LDI_W = { 695, 1},
.LDI_D = { 696, 1},
.COPY_S_B = { 697, 0},
.COPY_S_H = { 697, 0},
.COPY_S_W = { 697, 0},
.COPY_U_B = { 697, 0},
.COPY_U_H = { 697, 0},
.COPY_U_W = { 697, 0},
.INSERT_B = { 697, 0},
.INSERT_H = { 697, 0},
.INSERT_W = { 697, 0},
.INSERT_D = { 697, 0},
.INSVE_B = { 697, 0},
.INSVE_H = { 697, 0},
.INSVE_W = { 697, 0},
.INSVE_D = { 697, 0},
.SHF_B = { 697, 1},
.SHF_H = { 698, 1},
.SHF_W = { 699, 1},
.VSHF_B = { 700, 1},
.VSHF_H = { 701, 1},
.VSHF_W = { 702, 1},
.VSHF_D = { 703, 1},
.SLD_B = { 704, 1},
.SLD_H = { 705, 1},
.SLD_W = { 706, 1},
.SLD_D = { 707, 1},
.SLDI_B = { 708, 1},
.SLDI_H = { 709, 1},
.SLDI_W = { 710, 1},
.SLDI_D = { 711, 1},
.SPLAT_B = { 712, 1},
.SPLAT_H = { 713, 1},
.SPLAT_W = { 714, 1},
.SPLAT_D = { 715, 1},
.SPLATI_B = { 716, 1},
.SPLATI_H = { 717, 1},
.SPLATI_W = { 718, 1},
.SPLATI_D = { 719, 1},
.BZ_V = { 720, 0},
.BNZ_V = { 720, 0},
.BZ_B = { 720, 0},
.BZ_H = { 720, 0},
.BZ_W = { 720, 0},
.BZ_D = { 720, 0},
.BNZ_B = { 720, 0},
.BNZ_H = { 720, 0},
.BNZ_W = { 720, 0},
.BNZ_D = { 720, 0},
.NLOC_B = { 720, 1},
.NLOC_H = { 721, 1},
.NLOC_W = { 722, 1},
.NLOC_D = { 723, 1},
.NLZC_B = { 724, 1},
.NLZC_H = { 725, 1},
.NLZC_W = { 726, 1},
.NLZC_D = { 727, 1},
.PCNT_B = { 728, 1},
.PCNT_H = { 729, 1},
.PCNT_W = { 730, 1},
.PCNT_D = { 731, 1},
.VMOV_S = { 732, 1},
.VMOV_P = { 733, 1},
.VMOV_T = { 734, 1},
.VMOV_Q = { 735, 1},
.LV_S = { 736, 1},
.LV_Q = { 737, 1},
.SV_S = { 738, 1},
.SV_Q = { 739, 1},
.LVL_Q = { 740, 1},
.LVR_Q = { 741, 1},
.SVL_Q = { 742, 1},
.SVR_Q = { 743, 1},
.VIIM_S = { 744, 1},
.VFIM_S = { 745, 1},
.VADD_S = { 746, 1},
.VADD_P = { 747, 1},
.VADD_T = { 748, 1},
.VADD_Q = { 749, 1},
.VSUB_S = { 750, 1},
.VSUB_P = { 751, 1},
.VSUB_T = { 752, 1},
.VSUB_Q = { 753, 1},
.VMUL_S = { 754, 1},
.VMUL_P = { 755, 1},
.VMUL_T = { 756, 1},
.VMUL_Q = { 757, 1},
.VDIV_S = { 758, 1},
.VDIV_P = { 759, 1},
.VDIV_T = { 760, 1},
.VDIV_Q = { 761, 1},
.VABS_S = { 762, 1},
.VABS_P = { 763, 1},
.VABS_T = { 764, 1},
.VABS_Q = { 765, 1},
.VNEG_S = { 766, 1},
.VNEG_P = { 767, 1},
.VNEG_T = { 768, 1},
.VNEG_Q = { 769, 1},
.VSQRT_S = { 770, 1},
.VRCP_S = { 771, 1},
.VRCP_P = { 772, 1},
.VRCP_T = { 773, 1},
.VRCP_Q = { 774, 1},
.VRSQ_S = { 775, 1},
.VRSQ_P = { 776, 1},
.VRSQ_T = { 777, 1},
.VRSQ_Q = { 778, 1},
.VDOT_P = { 779, 1},
.VDOT_T = { 780, 1},
.VDOT_Q = { 781, 1},
.VSCL_P = { 782, 1},
.VSCL_T = { 783, 1},
.VSCL_Q = { 784, 1},
.VHDP_P = { 785, 1},
.VHDP_T = { 786, 1},
.VHDP_Q = { 787, 1},
.VAVG_P = { 788, 1},
.VAVG_T = { 789, 1},
.VAVG_Q = { 790, 1},
.VFAD_P = { 791, 1},
.VFAD_T = { 792, 1},
.VFAD_Q = { 793, 1},
.VMMUL_P = { 794, 1},
.VMMUL_T = { 795, 1},
.VMMUL_Q = { 796, 1},
.VTFM2_P = { 797, 1},
.VTFM3_T = { 798, 1},
.VTFM4_Q = { 799, 1},
.VHTFM2_P = { 800, 1},
.VHTFM3_T = { 801, 1},
.VHTFM4_Q = { 802, 1},
.VMSCL_P = { 803, 1},
.VMSCL_T = { 804, 1},
.VMSCL_Q = { 805, 1},
.VMMOV_P = { 806, 1},
.VMMOV_T = { 807, 1},
.VMMOV_Q = { 808, 1},
.VMIDT_P = { 809, 1},
.VMIDT_T = { 810, 1},
.VMIDT_Q = { 811, 1},
.VMZERO_P = { 812, 1},
.VMZERO_T = { 813, 1},
.VMZERO_Q = { 814, 1},
.VMONE_P = { 815, 1},
.VMONE_T = { 816, 1},
.VMONE_Q = { 817, 1},
.VCRS_T = { 818, 1},
.VCRSP_T = { 819, 1},
.VQMUL_Q = { 820, 1},
.VCMP_S = { 821, 1},
.VCMP_P = { 822, 1},
.VCMP_T = { 823, 1},
.VCMP_Q = { 824, 1},
.VMIN_S = { 825, 1},
.VMIN_P = { 826, 1},
.VMIN_T = { 827, 1},
.VMIN_Q = { 828, 1},
.VMAX_S = { 829, 1},
.VMAX_P = { 830, 1},
.VMAX_T = { 831, 1},
.VMAX_Q = { 832, 1},
.VSIN_S = { 833, 1},
.VCOS_S = { 834, 1},
.VEXP2_S = { 835, 1},
.VLOG2_S = { 836, 1},
.VASIN_S = { 837, 1},
.VNRCP_S = { 838, 1},
.VNSIN_S = { 839, 1},
.VREXP2_S = { 840, 1},
.VSGN_S = { 841, 1},
.VI2F_S = { 842, 1},
.VI2F_P = { 843, 1},
.VI2F_T = { 844, 1},
.VI2F_Q = { 845, 1},
.VF2IN_S = { 846, 1},
.VF2IN_P = { 847, 1},
.VF2IN_T = { 848, 1},
.VF2IN_Q = { 849, 1},
.VF2IZ_S = { 850, 1},
.VF2IZ_P = { 851, 1},
.VF2IZ_T = { 852, 1},
.VF2IZ_Q = { 853, 1},
.VF2IU_S = { 854, 1},
.VF2IU_P = { 855, 1},
.VF2IU_T = { 856, 1},
.VF2IU_Q = { 857, 1},
.VF2ID_S = { 858, 1},
.VF2ID_P = { 859, 1},
.VF2ID_T = { 860, 1},
.VF2ID_Q = { 861, 1},
.VF2H_P = { 862, 1},
.VH2F_S = { 863, 1},
.VFLUSH = { 864, 1},
.VSYNC = { 865, 1},
.VNOP = { 866, 1},
.VPFXS = { 867, 1},
.VPFXT = { 868, 1},
.VPFXD = { 869, 1},
.VCST_S = { 870, 1},
.VCST_P = { 871, 1},
.VCST_T = { 872, 1},
.VCST_Q = { 873, 1},
.MFV = { 874, 1},
.MTV = { 875, 1},
.MFVC = { 876, 1},
.MTVC = { 877, 1},
.BVF = { 878, 1},
.BVT = { 879, 1},
.BVFL = { 880, 1},
.BVTL = { 881, 1},
}

49
core/rexcode/mips/tablegen/specgen.lua
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@@ -103,6 +103,55 @@ for _, b in ipairs({
{"FTRUNC_S","ftrunc_s"},{"FTRUNC_U","ftrunc_u"},{"FFINT_S","ffint_s"},{"FFINT_U","ffint_u"},
}) do family(b[1], b[2], WD, false) end
-- ---- BIT: shift by immediate (Wd, Ws, m) -- marker per df in `bits` --------
local BIT_SH = {b=7, h=15, w=31, d=63}
for _, base in ipairs({{"SLLI","slli"},{"SRAI","srai"},{"SRLI","srli"}}) do
for _, d in ipairs(BHWD) do
local r = entry(base[1].."_"..d[1], "{.MSA_VEC,.MSA_VEC,.IMM5,.NONE}", "{.WD,.WS,.MSA_BIT_SHIFT,.NONE}", "MSA",
function(v) return string.format("%s.%s $w%d,$w%d,%d", base[2], d[2], v[1], v[2], v[3]) end, {31,31,BIT_SH[d[2]]})
if r then sections[#sections+1]=r end
end
end
-- ---- ELM: element broadcast/insert by immediate index (Wd, Ws[idx]) --------
local ELM_IDX = {b=15, h=7, w=3, d=1}
for _, base in ipairs({{"SPLATI","splati"},{"SLDI","sldi"}}) do
for _, d in ipairs(BHWD) do
local r = entry(base[1].."_"..d[1], "{.MSA_VEC,.MSA_VEC,.IMM5,.NONE}", "{.WD,.WS,.MSA_ELM_IDX,.NONE}", "MSA",
function(v) return string.format("%s.%s $w%d,$w%d[%d]", base[2], d[2], v[1], v[2], v[3]) end, {31,31,ELM_IDX[d[2]]})
if r then sections[#sections+1]=r end
end
end
-- ---- VSHF (3R vector shuffle) ----------------------------------------------
for _, d in ipairs(BHWD) do
local r = entry("VSHF_"..d[1], OPS3, ENC3, "MSA",
function(v) return string.format("vshf.%s $w%d,$w%d,$w%d", d[2], v[1], v[2], v[3]) end, {31,31,31})
if r then sections[#sections+1]=r end
end
-- ---- SPLAT / SLD (element broadcast/slide by GPR index) --------------------
for _, base in ipairs({{"SPLAT","splat"},{"SLD","sld"}}) do
for _, d in ipairs(BHWD) do
local r = entry(base[1].."_"..d[1], "{.MSA_VEC,.MSA_VEC,.GPR,.NONE}", "{.WD,.WS,.RT,.NONE}", "MSA",
function(v) return string.format("%s.%s $w%d,$w%d[$%d]", base[2], d[2], v[1], v[2], v[3]) end, {31,31,31})
if r then sections[#sections+1]=r end
end
end
-- ---- I8: 8-bit-immediate logical / shuffle ---------------------------------
for _, base in ipairs({{"ANDI_B","andi.b"},{"ORI_B","ori.b"},{"XORI_B","xori.b"},{"NORI_B","nori.b"},
{"BMNZI_B","bmnzi.b"},{"BMZI_B","bmzi.b"},{"BSELI_B","bseli.b"}}) do
local r = entry(base[1], "{.MSA_VEC,.MSA_VEC,.IMM5,.NONE}", "{.WD,.WS,.MSA_I8,.NONE}", "MSA",
function(v) return string.format("%s $w%d,$w%d,%d", base[2], v[1], v[2], v[3]) end, {31,31,255})
if r then sections[#sections+1]=r end
end
for _, d in ipairs({{"B","b"},{"H","h"},{"W","w"}}) do
local r = entry("SHF_"..d[1], "{.MSA_VEC,.MSA_VEC,.IMM5,.NONE}", "{.WD,.WS,.MSA_I8,.NONE}", "MSA",
function(v) return string.format("shf.%s $w%d,$w%d,%d", d[2], v[1], v[2], v[3]) end, {31,31,255})
if r then sections[#sections+1]=r end
end
-- ---- splice into the SoT ---------------------------------------------------
local region = " // SPECGEN:BEGIN\n" .. table.concat(sections, "\n") .. "\n // SPECGEN:END"
local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close()

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