mirror of
https://github.com/odin-lang/Odin.git
synced 2025-12-29 01:14:40 +00:00
Update sync2 to just use atomic intrinsics rather than the parapoly wrappers
This commit is contained in:
gingerBill
@@ -2,7 +2,6 @@
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package os
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import "core:time"
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import "core:path"
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/*
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For reference
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@@ -71,6 +70,36 @@ _fill_file_info_from_stat :: proc(fi: ^File_Info, s: OS_Stat) {
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fi.access_time = _make_time_from_unix_file_time(s.last_access);
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}
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@private
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path_base :: proc(path: string) -> string {
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is_separator :: proc(c: byte) -> bool {
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return c == '/';
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}
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if path == "" {
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return ".";
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}
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path := path;
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for len(path) > 0 && is_separator(path[len(path)-1]) {
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path = path[:len(path)-1];
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}
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i := len(path)-1;
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for i >= 0 && !is_separator(path[i]) {
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i -= 1;
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}
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if i >= 0 {
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path = path[i+1:];
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}
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if path == "" {
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return "/";
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}
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return path;
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}
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lstat :: proc(name: string, allocator := context.allocator) -> (fi: File_Info, err: Errno) {
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context.allocator = allocator;
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@@ -85,7 +114,7 @@ lstat :: proc(name: string, allocator := context.allocator) -> (fi: File_Info, e
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if err != ERROR_NONE {
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return;
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}
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fi.name = path.base(fi.fullpath);
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fi.name = path_base(fi.fullpath);
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return fi, ERROR_NONE;
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}
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@@ -103,7 +132,7 @@ stat :: proc(name: string, allocator := context.allocator) -> (fi: File_Info, er
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if err != ERROR_NONE {
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return;
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}
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fi.name = path.base(fi.fullpath);
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fi.name = path_base(fi.fullpath);
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return fi, ERROR_NONE;
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}
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@@ -121,6 +150,6 @@ fstat :: proc(fd: Handle, allocator := context.allocator) -> (fi: File_Info, err
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if err != ERROR_NONE {
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return;
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}
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fi.name = path.base(fi.fullpath);
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fi.name = path_base(fi.fullpath);
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return fi, ERROR_NONE;
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}
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@@ -4,167 +4,76 @@ import "intrinsics"
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// TODO(bill): Is this even a good design? The intrinsics seem to be more than good enough and just as clean
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Ordering :: enum {
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Relaxed, // Monotonic
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Release,
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Acquire,
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Acquire_Release,
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Sequentially_Consistent,
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}
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cpu_relax :: intrinsics.cpu_relax;
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strongest_failure_ordering_table := [Ordering]Ordering{
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.Relaxed = .Relaxed,
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.Release = .Relaxed,
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.Acquire = .Acquire,
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.Acquire_Release = .Acquire,
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.Sequentially_Consistent = .Sequentially_Consistent,
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};
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atomic_fence :: intrinsics.atomic_fence;
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atomic_fence_acq :: intrinsics.atomic_fence_acq;
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atomic_fence_rel :: intrinsics.atomic_fence_rel;
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atomic_fence_acqrel :: intrinsics.atomic_fence_acqrel;
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strongest_failure_ordering :: #force_inline proc(order: Ordering) -> Ordering {
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return strongest_failure_ordering_table[order];
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}
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atomic_store :: intrinsics.atomic_store;
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atomic_store_rel :: intrinsics.atomic_store_rel;
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atomic_store_relaxed :: intrinsics.atomic_store_relaxed;
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atomic_store_unordered :: intrinsics.atomic_store_unordered;
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fence :: #force_inline proc($order: Ordering) {
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when order == .Relaxed { #panic("there is no such thing as a relaxed fence"); }
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else when order == .Release { intrinsics.atomic_fence_rel(); }
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else when order == .Acquire { intrinsics.atomic_fence_acq(); }
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else when order == .Acquire_Release { intrinsics.atomic_fence_acqrel(); }
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else when order == .Sequentially_Consistent { intrinsics.atomic_fence(); }
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else { #panic("unknown order"); }
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}
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atomic_load :: intrinsics.atomic_load;
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atomic_load_acq :: intrinsics.atomic_load_acq;
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atomic_load_relaxed :: intrinsics.atomic_load_relaxed;
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atomic_load_unordered :: intrinsics.atomic_load_unordered;
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atomic_add :: intrinsics.atomic_add;
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atomic_add_acq :: intrinsics.atomic_add_acq;
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atomic_add_rel :: intrinsics.atomic_add_rel;
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atomic_add_acqrel :: intrinsics.atomic_add_acqrel;
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atomic_add_relaxed :: intrinsics.atomic_add_relaxed;
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atomic_sub :: intrinsics.atomic_sub;
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atomic_sub_acq :: intrinsics.atomic_sub_acq;
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atomic_sub_rel :: intrinsics.atomic_sub_rel;
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atomic_sub_acqrel :: intrinsics.atomic_sub_acqrel;
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atomic_sub_relaxed :: intrinsics.atomic_sub_relaxed;
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atomic_and :: intrinsics.atomic_and;
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atomic_and_acq :: intrinsics.atomic_and_acq;
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atomic_and_rel :: intrinsics.atomic_and_rel;
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atomic_and_acqrel :: intrinsics.atomic_and_acqrel;
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atomic_and_relaxed :: intrinsics.atomic_and_relaxed;
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atomic_nand :: intrinsics.atomic_nand;
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atomic_nand_acq :: intrinsics.atomic_nand_acq;
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atomic_nand_rel :: intrinsics.atomic_nand_rel;
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atomic_nand_acqrel :: intrinsics.atomic_nand_acqrel;
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atomic_nand_relaxed :: intrinsics.atomic_nand_relaxed;
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atomic_or :: intrinsics.atomic_or;
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atomic_or_acq :: intrinsics.atomic_or_acq;
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atomic_or_rel :: intrinsics.atomic_or_rel;
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atomic_or_acqrel :: intrinsics.atomic_or_acqrel;
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atomic_or_relaxed :: intrinsics.atomic_or_relaxed;
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atomic_xor :: intrinsics.atomic_xor;
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atomic_xor_acq :: intrinsics.atomic_xor_acq;
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atomic_xor_rel :: intrinsics.atomic_xor_rel;
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atomic_xor_acqrel :: intrinsics.atomic_xor_acqrel;
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atomic_xor_relaxed :: intrinsics.atomic_xor_relaxed;
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atomic_store :: #force_inline proc(dst: ^$T, val: T, $order: Ordering) {
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when order == .Relaxed { intrinsics.atomic_store_relaxed(dst, val); }
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else when order == .Release { intrinsics.atomic_store_rel(dst, val); }
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else when order == .Sequentially_Consistent { intrinsics.atomic_store(dst, val); }
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else when order == .Acquire { #panic("there is not such thing as an acquire store"); }
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else when order == .Acquire_Release { #panic("there is not such thing as an acquire/release store"); }
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else { #panic("unknown order"); }
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}
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atomic_xchg :: intrinsics.atomic_xchg;
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atomic_xchg_acq :: intrinsics.atomic_xchg_acq;
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atomic_xchg_rel :: intrinsics.atomic_xchg_rel;
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atomic_xchg_acqrel :: intrinsics.atomic_xchg_acqrel;
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atomic_xchg_relaxed :: intrinsics.atomic_xchg_relaxed;
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atomic_load :: #force_inline proc(dst: ^$T, $order: Ordering) -> T {
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when order == .Relaxed { return intrinsics.atomic_load_relaxed(dst); }
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else when order == .Acquire { return intrinsics.atomic_load_acq(dst); }
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else when order == .Sequentially_Consistent { return intrinsics.atomic_load(dst); }
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else when order == .Release { #panic("there is no such thing as a release load"); }
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else when order == .Acquire_Release { #panic("there is no such thing as an acquire/release load"); }
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else { #panic("unknown order"); }
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}
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atomic_exchange :: #force_inline proc(dst: ^$T, val: T, $order: Ordering) -> T {
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when order == .Relaxed { return intrinsics.atomic_xchg_relaxed(dst, val); }
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else when order == .Release { return intrinsics.atomic_xchg_rel(dst, val); }
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else when order == .Acquire { return intrinsics.atomic_xchg_acq(dst, val); }
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else when order == .Acquire_Release { return intrinsics.atomic_xchg_acqrel(dst, val); }
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else when order == .Sequentially_Consistent { return intrinsics.atomic_xchg(dst, val); }
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else { #panic("unknown order"); }
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}
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atomic_compare_exchange :: #force_inline proc(dst: ^$T, old, new: T, $success, $failure: Ordering) -> (val: T, ok: bool) {
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when failure == .Relaxed {
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when success == .Relaxed { return intrinsics.atomic_cxchg_relaxed(dst, old, new); }
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else when success == .Acquire { return intrinsics.atomic_cxchg_acq_failrelaxed(dst, old, new); }
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else when success == .Acquire_Release { return intrinsics.atomic_cxchg_acqrel_failrelaxed(dst, old, new); }
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else when success == .Sequentially_Consistent { return intrinsics.atomic_cxchg_failrelaxed(dst, old, new); }
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else when success == .Release { return intrinsics.atomic_cxchg_rel(dst, old, new); }
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else { #panic("an unknown ordering combination"); }
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} else when failure == .Acquire {
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when success == .Release { return intrinsics.atomic_cxchg_acqrel(dst, old, new); }
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else when success == .Acquire { return intrinsics.atomic_cxchg_acq(dst, old, new); }
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else { #panic("an unknown ordering combination"); }
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} else when failure == .Sequentially_Consistent {
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when success == .Sequentially_Consistent { return intrinsics.atomic_cxchg(dst, old, new); }
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else { #panic("an unknown ordering combination"); }
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} else when failure == .Acquire_Release {
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#panic("there is not such thing as an acquire/release failure ordering");
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} else when failure == .Release {
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when success == .Acquire { return instrinsics.atomic_cxchg_failacq(dst, old, new); }
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else { #panic("an unknown ordering combination"); }
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} else {
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return T{}, false;
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}
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}
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atomic_compare_exchange_weak :: #force_inline proc(dst: ^$T, old, new: T, $success, $failure: Ordering) -> (val: T, ok: bool) {
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when failure == .Relaxed {
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when success == .Relaxed { return intrinsics.atomic_cxchgweak_relaxed(dst, old, new); }
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else when success == .Acquire { return intrinsics.atomic_cxchgweak_acq_failrelaxed(dst, old, new); }
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else when success == .Acquire_Release { return intrinsics.atomic_cxchgweak_acqrel_failrelaxed(dst, old, new); }
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else when success == .Sequentially_Consistent { return intrinsics.atomic_cxchgweak_failrelaxed(dst, old, new); }
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else when success == .Release { return intrinsics.atomic_cxchgweak_rel(dst, old, new); }
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else { #panic("an unknown ordering combination"); }
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} else when failure == .Acquire {
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when success == .Release { return intrinsics.atomic_cxchgweak_acqrel(dst, old, new); }
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else when success == .Acquire { return intrinsics.atomic_cxchgweak_acq(dst, old, new); }
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else { #panic("an unknown ordering combination"); }
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} else when failure == .Sequentially_Consistent {
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when success == .Sequentially_Consistent { return intrinsics.atomic_cxchgweak(dst, old, new); }
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else { #panic("an unknown ordering combination"); }
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} else when failure == .Acquire_Release {
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#panic("there is not such thing as an acquire/release failure ordering");
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} else when failure == .Release {
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when success == .Acquire { return intrinsics.atomic_cxchgweak_failacq(dst, old, new); }
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else { #panic("an unknown ordering combination"); }
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} else {
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return T{}, false;
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}
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}
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atomic_add :: #force_inline proc(dst: ^$T, val: T, $order: Ordering) -> T {
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when order == .Relaxed { return intrinsics.atomic_add_relaxed(dst, val); }
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else when order == .Release { return intrinsics.atomic_add_rel(dst, val); }
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else when order == .Acquire { return intrinsics.atomic_add_acq(dst, val); }
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else when order == .Acquire_Release { return intrinsics.atomic_add_acqrel(dst, val); }
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else when order == .Sequentially_Consistent { return intrinsics.atomic_add(dst, val); }
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else { #panic("unknown order"); }
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}
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atomic_sub :: #force_inline proc(dst: ^$T, val: T, $order: Ordering) -> T {
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when order == .Relaxed { return intrinsics.atomic_sub_relaxed(dst, val); }
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else when order == .Release { return intrinsics.atomic_sub_rel(dst, val); }
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else when order == .Acquire { return intrinsics.atomic_sub_acq(dst, val); }
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else when order == .Acquire_Release { return intrinsics.atomic_sub_acqrel(dst, val); }
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else when order == .Sequentially_Consistent { return intrinsics.atomic_sub(dst, val); }
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else { #panic("unknown order"); }
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}
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atomic_and :: #force_inline proc(dst: ^$T, val: T, $order: Ordering) -> T {
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when order == .Relaxed { return intrinsics.atomic_and_relaxed(dst, val); }
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else when order == .Release { return intrinsics.atomic_and_rel(dst, val); }
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else when order == .Acquire { return intrinsics.atomic_and_acq(dst, val); }
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else when order == .Acquire_Release { return intrinsics.atomic_and_acqrel(dst, val); }
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else when order == .Sequentially_Consistent { return intrinsics.atomic_and(dst, val); }
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else { #panic("unknown order"); }
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}
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atomic_nand :: #force_inline proc(dst: ^$T, val: T, $order: Ordering) -> T {
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when order == .Relaxed { return intrinsics.atomic_nand_relaxed(dst, val); }
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else when order == .Release { return intrinsics.atomic_nand_rel(dst, val); }
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else when order == .Acquire { return intrinsics.atomic_nand_acq(dst, val); }
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else when order == .Acquire_Release { return intrinsics.atomic_nand_acqrel(dst, val); }
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else when order == .Sequentially_Consistent { return intrinsics.atomic_nand(dst, val); }
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else { #panic("unknown order"); }
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}
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atomic_or :: #force_inline proc(dst: ^$T, val: T, $order: Ordering) -> T {
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when order == .Relaxed { return intrinsics.atomic_or_relaxed(dst, val); }
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else when order == .Release { return intrinsics.atomic_or_rel(dst, val); }
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else when order == .Acquire { return intrinsics.atomic_or_acq(dst, val); }
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else when order == .Acquire_Release { return intrinsics.atomic_or_acqrel(dst, val); }
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else when order == .Sequentially_Consistent { return intrinsics.atomic_or(dst, val); }
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else { #panic("unknown order"); }
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}
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atomic_xor :: #force_inline proc(dst: ^$T, val: T, $order: Ordering) -> T {
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when order == .Relaxed { return intrinsics.atomic_xor_relaxed(dst, val); }
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else when order == .Release { return intrinsics.atomic_xor_rel(dst, val); }
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else when order == .Acquire { return intrinsics.atomic_xor_acq(dst, val); }
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else when order == .Acquire_Release { return intrinsics.atomic_xor_acqrel(dst, val); }
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else when order == .Sequentially_Consistent { return intrinsics.atomic_xor(dst, val); }
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else { #panic("unknown order"); }
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}
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atomic_cxchg :: intrinsics.atomic_cxchg;
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atomic_cxchg_acq :: intrinsics.atomic_cxchg_acq;
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atomic_cxchg_rel :: intrinsics.atomic_cxchg_rel;
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atomic_cxchg_acqrel :: intrinsics.atomic_cxchg_acqrel;
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atomic_cxchg_relaxed :: intrinsics.atomic_cxchg_relaxed;
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atomic_cxchg_failrelaxed :: intrinsics.atomic_cxchg_failrelaxed;
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atomic_cxchg_failacq :: intrinsics.atomic_cxchg_failacq;
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atomic_cxchg_acq_failrelaxed :: intrinsics.atomic_cxchg_acq_failrelaxed;
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atomic_cxchg_acqrel_failrelaxed :: intrinsics.atomic_cxchg_acqrel_failrelaxed;
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atomic_cxchgweak :: intrinsics.atomic_cxchgweak;
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atomic_cxchgweak_acq :: intrinsics.atomic_cxchgweak_acq;
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atomic_cxchgweak_rel :: intrinsics.atomic_cxchgweak_rel;
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atomic_cxchgweak_acqrel :: intrinsics.atomic_cxchgweak_acqrel;
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atomic_cxchgweak_relaxed :: intrinsics.atomic_cxchgweak_relaxed;
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atomic_cxchgweak_failrelaxed :: intrinsics.atomic_cxchgweak_failrelaxed;
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atomic_cxchgweak_failacq :: intrinsics.atomic_cxchgweak_failacq;
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atomic_cxchgweak_acq_failrelaxed :: intrinsics.atomic_cxchgweak_acq_failrelaxed;
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atomic_cxchgweak_acqrel_failrelaxed :: intrinsics.atomic_cxchgweak_acqrel_failrelaxed;
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@@ -5,7 +5,6 @@ package sync2
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import "core:mem"
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import "core:time"
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import "intrinsics"
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import "core:math/rand"
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_, _ :: time, rand;
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@@ -136,10 +135,10 @@ channel_peek :: proc(ch: $C/Channel($T, $D)) -> int {
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if c == nil {
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return -1;
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}
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if intrinsics.atomic_load(&c.closed) {
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if atomic_load(&c.closed) {
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return -1;
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}
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return intrinsics.atomic_load(&c.len);
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return atomic_load(&c.len);
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}
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@@ -238,7 +237,7 @@ raw_channel_destroy :: proc(c: ^Raw_Channel) {
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return;
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}
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context.allocator = c.allocator;
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intrinsics.atomic_store(&c.closed, true);
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atomic_store(&c.closed, true);
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free(c);
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}
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@@ -248,7 +247,7 @@ raw_channel_close :: proc(c: ^Raw_Channel, loc := #caller_location) {
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}
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mutex_lock(&c.mutex);
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defer mutex_unlock(&c.mutex);
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intrinsics.atomic_store(&c.closed, true);
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atomic_store(&c.closed, true);
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// Release readers and writers
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raw_channel_wait_queue_broadcast(c.recvq);
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@@ -317,12 +316,12 @@ raw_channel_recv_impl :: proc(c: ^Raw_Channel, res: rawptr, loc := #caller_locat
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if c == nil {
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panic(message="cannot recv message; channel is nil", loc=loc);
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}
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intrinsics.atomic_store(&c.ready, true);
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atomic_store(&c.ready, true);
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for c.len < 1 {
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raw_channel_wait_queue_signal(c.sendq);
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cond_wait(&c.cond, &c.mutex);
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}
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intrinsics.atomic_store(&c.ready, false);
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atomic_store(&c.ready, false);
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recv(c, res, loc);
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if c.cap > 0 {
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if c.len == c.cap - 1 {
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@@ -2,7 +2,6 @@
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//+private
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package sync2
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import "intrinsics"
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import win32 "core:sys/windows"
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import "core:time"
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@@ -12,24 +11,24 @@ raw_channel_wait_queue_wait_on :: proc(state: ^uintptr, timeout: time.Duration)
|
||||
ms = win32.DWORD((max(time.duration_nanoseconds(timeout), 0) + 999999)/1000000);
|
||||
}
|
||||
|
||||
v := intrinsics.atomic_load(state);
|
||||
v := atomic_load(state);
|
||||
for v == 0 {
|
||||
win32.WaitOnAddress(state, &v, size_of(state^), ms);
|
||||
v = intrinsics.atomic_load(state);
|
||||
v = atomic_load(state);
|
||||
}
|
||||
intrinsics.atomic_store(state, 0);
|
||||
atomic_store(state, 0);
|
||||
}
|
||||
|
||||
raw_channel_wait_queue_signal :: proc(q: ^Raw_Channel_Wait_Queue) {
|
||||
for x := q; x != nil; x = x.next {
|
||||
intrinsics.atomic_add(x.state, 1);
|
||||
atomic_add(x.state, 1);
|
||||
win32.WakeByAddressSingle(x.state);
|
||||
}
|
||||
}
|
||||
|
||||
raw_channel_wait_queue_broadcast :: proc(q: ^Raw_Channel_Wait_Queue) {
|
||||
for x := q; x != nil; x = x.next {
|
||||
intrinsics.atomic_add(x.state, 1);
|
||||
atomic_add(x.state, 1);
|
||||
win32.WakeByAddressAll(x.state);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,7 +1,6 @@
|
||||
package sync2
|
||||
|
||||
import "core:runtime"
|
||||
import "intrinsics"
|
||||
|
||||
// A Wait_Group waits for a collection of threads to finish
|
||||
//
|
||||
@@ -20,7 +19,7 @@ wait_group_add :: proc(wg: ^Wait_Group, delta: int) {
|
||||
mutex_lock(&wg.mutex);
|
||||
defer mutex_unlock(&wg.mutex);
|
||||
|
||||
intrinsics.atomic_add(&wg.counter, delta);
|
||||
atomic_add(&wg.counter, delta);
|
||||
if wg.counter < 0 {
|
||||
panic("sync.Wait_Group negative counter");
|
||||
}
|
||||
@@ -130,14 +129,14 @@ Ticket_Mutex :: struct {
|
||||
}
|
||||
|
||||
ticket_mutex_lock :: #force_inline proc(m: ^Ticket_Mutex) {
|
||||
ticket := intrinsics.atomic_add_relaxed(&m.ticket, 1);
|
||||
for ticket != intrinsics.atomic_load_acq(&m.serving) {
|
||||
intrinsics.cpu_relax();
|
||||
ticket := atomic_add_relaxed(&m.ticket, 1);
|
||||
for ticket != atomic_load_acq(&m.serving) {
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
ticket_mutex_unlock :: #force_inline proc(m: ^Ticket_Mutex) {
|
||||
intrinsics.atomic_add_relaxed(&m.serving, 1);
|
||||
atomic_add_relaxed(&m.serving, 1);
|
||||
}
|
||||
|
||||
|
||||
@@ -148,18 +147,18 @@ Benaphore :: struct {
|
||||
}
|
||||
|
||||
benaphore_lock :: proc(b: ^Benaphore) {
|
||||
if intrinsics.atomic_add_acq(&b.counter, 1) > 1 {
|
||||
if atomic_add_acq(&b.counter, 1) > 1 {
|
||||
sema_wait(&b.sema);
|
||||
}
|
||||
}
|
||||
|
||||
benaphore_try_lock :: proc(b: ^Benaphore) -> bool {
|
||||
v, _ := intrinsics.atomic_cxchg_acq(&b.counter, 1, 0);
|
||||
v, _ := atomic_cxchg_acq(&b.counter, 1, 0);
|
||||
return v == 0;
|
||||
}
|
||||
|
||||
benaphore_unlock :: proc(b: ^Benaphore) {
|
||||
if intrinsics.atomic_sub_rel(&b.counter, 1) > 0 {
|
||||
if atomic_sub_rel(&b.counter, 1) > 0 {
|
||||
sema_post(&b.sema);
|
||||
}
|
||||
}
|
||||
@@ -173,7 +172,7 @@ Recursive_Benaphore :: struct {
|
||||
|
||||
recursive_benaphore_lock :: proc(b: ^Recursive_Benaphore) {
|
||||
tid := runtime.current_thread_id();
|
||||
if intrinsics.atomic_add_acq(&b.counter, 1) > 1 {
|
||||
if atomic_add_acq(&b.counter, 1) > 1 {
|
||||
if tid != b.owner {
|
||||
sema_wait(&b.sema);
|
||||
}
|
||||
@@ -186,10 +185,10 @@ recursive_benaphore_lock :: proc(b: ^Recursive_Benaphore) {
|
||||
recursive_benaphore_try_lock :: proc(b: ^Recursive_Benaphore) -> bool {
|
||||
tid := runtime.current_thread_id();
|
||||
if b.owner == tid {
|
||||
intrinsics.atomic_add_acq(&b.counter, 1);
|
||||
atomic_add_acq(&b.counter, 1);
|
||||
}
|
||||
|
||||
if v, _ := intrinsics.atomic_cxchg_acq(&b.counter, 1, 0); v != 0 {
|
||||
if v, _ := atomic_cxchg_acq(&b.counter, 1, 0); v != 0 {
|
||||
return false;
|
||||
}
|
||||
// inside the lock
|
||||
@@ -206,7 +205,7 @@ recursive_benaphore_unlock :: proc(b: ^Recursive_Benaphore) {
|
||||
if recursion == 0 {
|
||||
b.owner = 0;
|
||||
}
|
||||
if intrinsics.atomic_sub_rel(&b.counter, 1) > 0 {
|
||||
if atomic_sub_rel(&b.counter, 1) > 0 {
|
||||
if recursion == 0 {
|
||||
sema_post(&b.sema);
|
||||
}
|
||||
@@ -224,7 +223,7 @@ Once :: struct {
|
||||
}
|
||||
|
||||
once_do :: proc(o: ^Once, fn: proc()) {
|
||||
if intrinsics.atomic_load_acq(&o.done) == false {
|
||||
if atomic_load_acq(&o.done) == false {
|
||||
_once_do_slow(o, fn);
|
||||
}
|
||||
}
|
||||
@@ -234,6 +233,6 @@ _once_do_slow :: proc(o: ^Once, fn: proc()) {
|
||||
defer mutex_unlock(&o.m);
|
||||
if !o.done {
|
||||
fn();
|
||||
intrinsics.atomic_store_rel(&o.done, true);
|
||||
atomic_store_rel(&o.done, true);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -4,7 +4,6 @@ package sync2
|
||||
|
||||
when !#config(ODIN_SYNC_USE_PTHREADS, false) {
|
||||
|
||||
import "intrinsics"
|
||||
import "core:time"
|
||||
|
||||
_Mutex_State :: enum i32 {
|
||||
@@ -17,13 +16,13 @@ _Mutex :: struct {
|
||||
}
|
||||
|
||||
_mutex_lock :: proc(m: ^Mutex) {
|
||||
if intrinsics.atomic_xchg_rel(&m.impl.state, .Unlocked) != .Unlocked {
|
||||
if atomic_xchg_rel(&m.impl.state, .Unlocked) != .Unlocked {
|
||||
_mutex_unlock_slow(m);
|
||||
}
|
||||
}
|
||||
|
||||
_mutex_unlock :: proc(m: ^Mutex) {
|
||||
switch intrinsics.atomic_xchg_rel(&m.impl.state, .Unlocked) {
|
||||
switch atomic_xchg_rel(&m.impl.state, .Unlocked) {
|
||||
case .Unlocked:
|
||||
unreachable();
|
||||
case .Locked:
|
||||
@@ -34,7 +33,7 @@ _mutex_unlock :: proc(m: ^Mutex) {
|
||||
}
|
||||
|
||||
_mutex_try_lock :: proc(m: ^Mutex) -> bool {
|
||||
_, ok := intrinsics.atomic_cxchg_acq(&m.impl.state, .Unlocked, .Locked);
|
||||
_, ok := atomic_cxchg_acq(&m.impl.state, .Unlocked, .Locked);
|
||||
return ok;
|
||||
}
|
||||
|
||||
@@ -44,7 +43,7 @@ _mutex_lock_slow :: proc(m: ^Mutex, curr_state: _Mutex_State) {
|
||||
new_state := curr_state; // Make a copy of it
|
||||
|
||||
spin_lock: for spin in 0..<i32(100) {
|
||||
state, ok := intrinsics.atomic_cxchgweak_acq(&m.impl.state, .Unlocked, new_state);
|
||||
state, ok := atomic_cxchgweak_acq(&m.impl.state, .Unlocked, new_state);
|
||||
if ok {
|
||||
return;
|
||||
}
|
||||
@@ -54,17 +53,17 @@ _mutex_lock_slow :: proc(m: ^Mutex, curr_state: _Mutex_State) {
|
||||
}
|
||||
|
||||
for i := min(spin+1, 32); i > 0; i -= 1 {
|
||||
intrinsics.cpu_relax();
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
for {
|
||||
if intrinsics.atomic_xchg_acq(&m.impl.state, .Waiting) == .Unlocked {
|
||||
if atomic_xchg_acq(&m.impl.state, .Waiting) == .Unlocked {
|
||||
return;
|
||||
}
|
||||
|
||||
// TODO(bill): Use a Futex here for Linux to improve performance and error handling
|
||||
intrinsics.cpu_relax();
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
@@ -91,25 +90,25 @@ _RW_Mutex :: struct {
|
||||
}
|
||||
|
||||
_rw_mutex_lock :: proc(rw: ^RW_Mutex) {
|
||||
_ = intrinsics.atomic_add(&rw.impl.state, RW_Mutex_State_Writer);
|
||||
_ = atomic_add(&rw.impl.state, RW_Mutex_State_Writer);
|
||||
mutex_lock(&rw.impl.mutex);
|
||||
|
||||
state := intrinsics.atomic_or(&rw.impl.state, RW_Mutex_State_Writer);
|
||||
state := atomic_or(&rw.impl.state, RW_Mutex_State_Writer);
|
||||
if state & RW_Mutex_State_Reader_Mask != 0 {
|
||||
sema_wait(&rw.impl.sema);
|
||||
}
|
||||
}
|
||||
|
||||
_rw_mutex_unlock :: proc(rw: ^RW_Mutex) {
|
||||
_ = intrinsics.atomic_and(&rw.impl.state, ~RW_Mutex_State_Is_Writing);
|
||||
_ = atomic_and(&rw.impl.state, ~RW_Mutex_State_Is_Writing);
|
||||
mutex_unlock(&rw.impl.mutex);
|
||||
}
|
||||
|
||||
_rw_mutex_try_lock :: proc(rw: ^RW_Mutex) -> bool {
|
||||
if mutex_try_lock(&rw.impl.mutex) {
|
||||
state := intrinsics.atomic_load(&rw.impl.state);
|
||||
state := atomic_load(&rw.impl.state);
|
||||
if state & RW_Mutex_State_Reader_Mask == 0 {
|
||||
_ = intrinsics.atomic_or(&rw.impl.state, RW_Mutex_State_Is_Writing);
|
||||
_ = atomic_or(&rw.impl.state, RW_Mutex_State_Is_Writing);
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -119,22 +118,22 @@ _rw_mutex_try_lock :: proc(rw: ^RW_Mutex) -> bool {
|
||||
}
|
||||
|
||||
_rw_mutex_shared_lock :: proc(rw: ^RW_Mutex) {
|
||||
state := intrinsics.atomic_load(&rw.impl.state);
|
||||
state := atomic_load(&rw.impl.state);
|
||||
for state & (RW_Mutex_State_Is_Writing|RW_Mutex_State_Writer_Mask) == 0 {
|
||||
ok: bool;
|
||||
state, ok = intrinsics.atomic_cxchgweak(&rw.impl.state, state, state + RW_Mutex_State_Reader);
|
||||
state, ok = atomic_cxchgweak(&rw.impl.state, state, state + RW_Mutex_State_Reader);
|
||||
if ok {
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
mutex_lock(&rw.impl.mutex);
|
||||
_ = intrinsics.atomic_add(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
_ = atomic_add(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
mutex_unlock(&rw.impl.mutex);
|
||||
}
|
||||
|
||||
_rw_mutex_shared_unlock :: proc(rw: ^RW_Mutex) {
|
||||
state := intrinsics.atomic_sub(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
state := atomic_sub(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
|
||||
if (state & RW_Mutex_State_Reader_Mask == RW_Mutex_State_Reader) &&
|
||||
(state & RW_Mutex_State_Is_Writing != 0) {
|
||||
@@ -143,15 +142,15 @@ _rw_mutex_shared_unlock :: proc(rw: ^RW_Mutex) {
|
||||
}
|
||||
|
||||
_rw_mutex_try_shared_lock :: proc(rw: ^RW_Mutex) -> bool {
|
||||
state := intrinsics.atomic_load(&rw.impl.state);
|
||||
state := atomic_load(&rw.impl.state);
|
||||
if state & (RW_Mutex_State_Is_Writing|RW_Mutex_State_Writer_Mask) == 0 {
|
||||
_, ok := intrinsics.atomic_cxchg(&rw.impl.state, state, state + RW_Mutex_State_Reader);
|
||||
_, ok := atomic_cxchg(&rw.impl.state, state, state + RW_Mutex_State_Reader);
|
||||
if ok {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
if mutex_try_lock(&rw.impl.mutex) {
|
||||
_ = intrinsics.atomic_add(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
_ = atomic_add(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
mutex_unlock(&rw.impl.mutex);
|
||||
return true;
|
||||
}
|
||||
@@ -167,13 +166,13 @@ Queue_Item :: struct {
|
||||
}
|
||||
|
||||
queue_item_wait :: proc(item: ^Queue_Item) {
|
||||
for intrinsics.atomic_load_acq(&item.futex) == 0 {
|
||||
for atomic_load_acq(&item.futex) == 0 {
|
||||
// TODO(bill): Use a Futex here for Linux to improve performance and error handling
|
||||
intrinsics.cpu_relax();
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
queue_item_signal :: proc(item: ^Queue_Item) {
|
||||
intrinsics.atomic_store_rel(&item.futex, 1);
|
||||
atomic_store_rel(&item.futex, 1);
|
||||
// TODO(bill): Use a Futex here for Linux to improve performance and error handling
|
||||
}
|
||||
|
||||
@@ -191,7 +190,7 @@ _cond_wait :: proc(c: ^Cond, m: ^Mutex) {
|
||||
waiter.next = c.impl.queue_head;
|
||||
c.impl.queue_head = waiter;
|
||||
|
||||
intrinsics.atomic_store(&c.impl.pending, true);
|
||||
atomic_store(&c.impl.pending, true);
|
||||
mutex_unlock(&c.impl.queue_mutex);
|
||||
|
||||
mutex_unlock(m);
|
||||
@@ -205,7 +204,7 @@ _cond_wait_with_timeout :: proc(c: ^Cond, m: ^Mutex, timeout: time.Duration) ->
|
||||
}
|
||||
|
||||
_cond_signal :: proc(c: ^Cond) {
|
||||
if !intrinsics.atomic_load(&c.impl.pending) {
|
||||
if !atomic_load(&c.impl.pending) {
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -214,7 +213,7 @@ _cond_signal :: proc(c: ^Cond) {
|
||||
if c.impl.queue_head != nil {
|
||||
c.impl.queue_head = c.impl.queue_head.next;
|
||||
}
|
||||
intrinsics.atomic_store(&c.impl.pending, c.impl.queue_head != nil);
|
||||
atomic_store(&c.impl.pending, c.impl.queue_head != nil);
|
||||
mutex_unlock(&c.impl.queue_mutex);
|
||||
|
||||
if waiter != nil {
|
||||
@@ -223,11 +222,11 @@ _cond_signal :: proc(c: ^Cond) {
|
||||
}
|
||||
|
||||
_cond_broadcast :: proc(c: ^Cond) {
|
||||
if !intrinsics.atomic_load(&c.impl.pending) {
|
||||
if !atomic_load(&c.impl.pending) {
|
||||
return;
|
||||
}
|
||||
|
||||
intrinsics.atomic_store(&c.impl.pending, false);
|
||||
atomic_store(&c.impl.pending, false);
|
||||
|
||||
mutex_lock(&c.impl.queue_mutex);
|
||||
waiters := c.impl.queue_head;
|
||||
|
||||
@@ -4,7 +4,6 @@ package sync2
|
||||
|
||||
when #config(ODIN_SYNC_USE_PTHREADS, false) {
|
||||
|
||||
import "intrinsics"
|
||||
import "core:time"
|
||||
import "core:sys/unix"
|
||||
|
||||
@@ -53,25 +52,25 @@ _RW_Mutex :: struct {
|
||||
}
|
||||
|
||||
_rw_mutex_lock :: proc(rw: ^RW_Mutex) {
|
||||
_ = intrinsics.atomic_add(&rw.impl.state, RW_Mutex_State_Writer);
|
||||
_ = atomic_add(&rw.impl.state, RW_Mutex_State_Writer);
|
||||
mutex_lock(&rw.impl.mutex);
|
||||
|
||||
state := intrinsics.atomic_or(&rw.impl.state, RW_Mutex_State_Writer);
|
||||
state := atomic_or(&rw.impl.state, RW_Mutex_State_Writer);
|
||||
if state & RW_Mutex_State_Reader_Mask != 0 {
|
||||
sema_wait(&rw.impl.sema);
|
||||
}
|
||||
}
|
||||
|
||||
_rw_mutex_unlock :: proc(rw: ^RW_Mutex) {
|
||||
_ = intrinsics.atomic_and(&rw.impl.state, ~RW_Mutex_State_Is_Writing);
|
||||
_ = atomic_and(&rw.impl.state, ~RW_Mutex_State_Is_Writing);
|
||||
mutex_unlock(&rw.impl.mutex);
|
||||
}
|
||||
|
||||
_rw_mutex_try_lock :: proc(rw: ^RW_Mutex) -> bool {
|
||||
if mutex_try_lock(&rw.impl.mutex) {
|
||||
state := intrinsics.atomic_load(&rw.impl.state);
|
||||
state := atomic_load(&rw.impl.state);
|
||||
if state & RW_Mutex_State_Reader_Mask == 0 {
|
||||
_ = intrinsics.atomic_or(&rw.impl.state, RW_Mutex_State_Is_Writing);
|
||||
_ = atomic_or(&rw.impl.state, RW_Mutex_State_Is_Writing);
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -81,22 +80,22 @@ _rw_mutex_try_lock :: proc(rw: ^RW_Mutex) -> bool {
|
||||
}
|
||||
|
||||
_rw_mutex_shared_lock :: proc(rw: ^RW_Mutex) {
|
||||
state := intrinsics.atomic_load(&rw.impl.state);
|
||||
state := atomic_load(&rw.impl.state);
|
||||
for state & (RW_Mutex_State_Is_Writing|RW_Mutex_State_Writer_Mask) == 0 {
|
||||
ok: bool;
|
||||
state, ok = intrinsics.atomic_cxchgweak(&rw.impl.state, state, state + RW_Mutex_State_Reader);
|
||||
state, ok = atomic_cxchgweak(&rw.impl.state, state, state + RW_Mutex_State_Reader);
|
||||
if ok {
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
mutex_lock(&rw.impl.mutex);
|
||||
_ = intrinsics.atomic_add(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
_ = atomic_add(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
mutex_unlock(&rw.impl.mutex);
|
||||
}
|
||||
|
||||
_rw_mutex_shared_unlock :: proc(rw: ^RW_Mutex) {
|
||||
state := intrinsics.atomic_sub(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
state := atomic_sub(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
|
||||
if (state & RW_Mutex_State_Reader_Mask == RW_Mutex_State_Reader) &&
|
||||
(state & RW_Mutex_State_Is_Writing != 0) {
|
||||
@@ -105,15 +104,15 @@ _rw_mutex_shared_unlock :: proc(rw: ^RW_Mutex) {
|
||||
}
|
||||
|
||||
_rw_mutex_try_shared_lock :: proc(rw: ^RW_Mutex) -> bool {
|
||||
state := intrinsics.atomic_load(&rw.impl.state);
|
||||
state := atomic_load(&rw.impl.state);
|
||||
if state & (RW_Mutex_State_Is_Writing|RW_Mutex_State_Writer_Mask) == 0 {
|
||||
_, ok := intrinsics.atomic_cxchg(&rw.impl.state, state, state + RW_Mutex_State_Reader);
|
||||
_, ok := atomic_cxchg(&rw.impl.state, state, state + RW_Mutex_State_Reader);
|
||||
if ok {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
if mutex_try_lock(&rw.impl.mutex) {
|
||||
_ = intrinsics.atomic_add(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
_ = atomic_add(&rw.impl.state, RW_Mutex_State_Reader);
|
||||
mutex_unlock(&rw.impl.mutex);
|
||||
return true;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user