mirror of
https://github.com/odin-lang/Odin.git
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Impl simd arm pmull
This commit is contained in:
Alexander Zhura
406
core/simd/arm/pmull.odin
Normal file
406
core/simd/arm/pmull.odin
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@@ -0,0 +1,406 @@
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#+build arm64,arm32
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package simd_arm
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import "core:simd"
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// Join two smaller vectors into a single larger vector
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p8)
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@(require_results, enable_target_feature = "neon")
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vcombine_p8 :: #force_inline proc "c" (low, high: poly8x8_t) -> poly8x16_t {
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when ODIN_ENDIAN == .Little {
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return simd.shuffle(low, high, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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} else {
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low := simd.shuffle(low, low, 7, 6, 5, 4, 3, 2, 1, 0)
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high := simd.shuffle(high, high, 7, 6, 5, 4, 3, 2, 1, 0)
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c := simd.shuffle(low, high, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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return simd.shuffle(c, c, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
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}
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}
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// Join two smaller vectors into a single larger vector
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p16)
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@(require_results, enable_target_feature = "neon")
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vcombine_p16 :: #force_inline proc "c" (low, high: poly16x4_t) -> poly16x8_t {
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when ODIN_ENDIAN == .Little {
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return simd.shuffle(low, high, 0, 1, 2, 3, 4, 5, 6, 7)
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} else {
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low := simd.shuffle(low, low, 3, 2, 1, 0)
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high := simd.shuffle(high, high, 3, 2, 1, 0)
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c := simd.shuffle(low, high, 0, 1, 2, 3, 4, 5, 6, 7)
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return simd.shuffle(c, c, 7, 6, 5, 4, 3, 2, 1, 0)
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}
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}
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// Join two smaller vectors into a single larger vector
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcombine_p64)
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@(require_results, enable_target_feature = "neon")
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vcombine_p64 :: #force_inline proc "c" (low, high: poly64x1_t) -> poly64x2_t {
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when ODIN_ENDIAN == .Little {
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return simd.shuffle(low, high, 0, 1)
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} else {
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c := simd.shuffle(low, high, 0, 1)
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return simd.shuffle(c, c, 1, 0)
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}
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}
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// Insert vector element from another vector element
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)
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@(require_results, enable_target_feature = "neon")
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vset_lane_p8 :: #force_inline proc "c" (a: poly8_t, v: poly8x8_t, $LANE: int32_t) -> poly8x8_t where 0 <= LANE, LANE < 8 {
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when ODIN_ENDIAN == .Little {
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return simd.replace(v, LANE, a)
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} else {
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v := simd.shuffle(v, v, 7, 6, 5, 4, 3, 2, 1, 0)
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c := simd.replace(v, LANE, a)
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return simd.shuffle(c, c, 7, 6, 5, 4, 3, 2, 1, 0)
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}
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}
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// Insert vector element from another vector element
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)
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@(require_results, enable_target_feature = "neon")
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vset_lane_p16 :: #force_inline proc "c" (a: poly16_t, v: poly16x4_t, $LANE: int32_t) -> poly16x4_t where 0 <= LANE, LANE < 4 {
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when ODIN_ENDIAN == .Little {
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return simd.replace(v, LANE, a)
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} else {
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v := simd.shuffle(v, v, 3, 2, 1, 0)
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c := simd.replace(v, LANE, a)
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return simd.shuffle(c, c, 3, 2, 1, 0)
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}
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}
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// Insert vector element from another vector element
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)
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@(require_results, enable_target_feature = "neon")
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vset_lane_p64 :: #force_inline proc "c" (a: poly64_t, v: poly64x1_t, $LANE: int32_t) -> poly64x1_t where LANE == 0 {
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return simd.replace(v, LANE, a)
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}
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// Move vector element to general-purpose register
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p8)
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@(require_results, enable_target_feature = "neon")
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vget_lane_p8 :: #force_inline proc "c" (v: poly8x8_t, $LANE: int32_t) -> poly8_t where 0 <= LANE, LANE < 8 {
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when ODIN_ENDIAN == .Little {
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return simd.extract(v, LANE)
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} else {
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v := simd.shuffle(v, v, 7, 6, 5, 4, 3, 2, 1, 0)
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return simd.extract(v, LANE)
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}
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}
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// Move vector element to general-purpose register
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p16)
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@(require_results, enable_target_feature = "neon")
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vget_lane_p16 :: #force_inline proc "c" (v: poly16x4_t, $LANE: int32_t) -> poly16_t where 0 <= LANE, LANE < 4 {
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when ODIN_ENDIAN == .Little {
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return simd.extract(v, LANE)
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} else {
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v := simd.shuffle(v, v, 3, 2, 1, 0)
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return simd.extract(v, LANE)
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}
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}
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// Move vector element to general-purpose register
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_p64)
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@(require_results, enable_target_feature = "neon")
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vget_lane_p64 :: #force_inline proc "c" (v: poly64x1_t, $LANE: int32_t) -> poly64_t where LANE == 0 {
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return simd.extract(v, LANE)
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}
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// Insert vector element from another vector element
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)
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@(require_results, enable_target_feature = "neon")
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vsetq_lane_p8 :: #force_inline proc "c" (a: poly8_t, v: poly8x16_t, $LANE: int32_t) -> poly8x16_t where 0 <= LANE, LANE < 16 {
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when ODIN_ENDIAN == .Little {
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return simd.replace(v, LANE, a)
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} else {
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v := simd.shuffle(v, v, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
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c := simd.replace(v, LANE, a)
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return simd.shuffle(c, c, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
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}
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}
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// Insert vector element from another vector element
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)
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@(require_results, enable_target_feature = "neon")
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vsetq_lane_p16 :: #force_inline proc "c" (a: poly16_t, v: poly16x8_t, $LANE: int32_t) -> poly16x8_t where 0 <= LANE, LANE < 8 {
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when ODIN_ENDIAN == .Little {
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return simd.replace(v, LANE, a)
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} else {
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v := simd.shuffle(v, v, 7, 6, 5, 4, 3, 2, 1, 0)
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c := simd.replace(v, LANE, a)
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return simd_shuffle(c, c, 7, 6, 5, 4, 3, 2, 1, 0)
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}
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}
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// Insert vector element from another vector element
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)
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@(require_results, enable_target_feature = "neon")
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vsetq_lane_p64 :: #force_inline proc "c" (a: poly64_t, v: poly64x2_t, $LANE: int32_t) -> poly64x2_t where 0 <= LANE, LANE < 2 {
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when ODIN_ENDIAN == .Little {
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return simd.replace(v, LANE, a)
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} else {
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v := simd.shuffle(v, v, 1, 0)
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c := simd.replace(v, LANE, a)
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return simd.shuffle(c, c, 1, 0)
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}
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}
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// Move vector element to general-purpose register
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p8)
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@(require_results, enable_target_feature = "neon")
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vgetq_lane_p8 :: #force_inline proc "c" (v: poly8x16_t, $LANE: int32_t) -> poly8_t where 0 <= LANE, LANE < 16 {
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when ODIN_ENDIAN == .Little {
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return simd.extract(v, LANE)
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} else {
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v := simd.shuffle(v, v, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
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return simd.extract(v, LANE)
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}
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}
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// Move vector element to general-purpose register
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p16)
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@(require_results, enable_target_feature = "neon")
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vgetq_lane_p16 :: #force_inline proc "c" (v: poly16x8_t, $LANE: int32_t) -> poly16_t where 0 <= LANE, LANE < 8 {
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when ODIN_ENDIAN == .Little {
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return simd.extract(v, LANE)
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} else {
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v := simd.shuffle(v, v, 7, 6, 5, 4, 3, 2, 1, 0)
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return simd.extract(v, LANE)
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}
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}
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// Move vector element to general-purpose register
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_p64)
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@(require_results, enable_target_feature = "neon")
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vgetq_lane_p64 :: #force_inline proc "c" (v: poly64x2_t, $LANE: int32_t) -> poly64_t where 0 <= LANE, LANE < 2 {
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when ODIN_ENDIAN == .Little {
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return simd.extract(v, LANE)
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} else {
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v := simd.shuffle(v, v, 1, 0)
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return simd.extract(v, LANE)
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}
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}
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// Duplicate vector element to vector or scalar
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p8)
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@(require_results, enable_target_feature = "neon")
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vget_low_p8 :: #force_inline proc "c" (a: poly8x16_t) -> poly8x8_t {
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when ODIN_ENDIAN == .Little {
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return simd.shuffle(a, a, 0, 1, 2, 3, 4, 5, 6, 7)
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} else {
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a := simd.shuffle(a, a, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
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b := simd.shuffle(a, a, 0, 1, 2, 3, 4, 5, 6, 7)
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return simd.shuffle(b, b, 7, 6, 5, 4, 3, 2, 1, 0)
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}
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}
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// Duplicate vector element to vector or scalar
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p16)
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@(require_results, enable_target_feature = "neon")
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vget_low_p16 :: #force_inline proc "c" (a: poly16x8_t) -> poly16x4_t {
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when ODIN_ENDIAN == .Little {
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return simd.shuffle(a, a, 0, 1, 2, 3)
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} else {
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a := simd.shuffle(a, a, 7, 6, 5, 4, 3, 2, 1, 0)
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b := simd.shuffle(a, a, 0, 1, 2, 3)
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return simd.shuffle(b, b, 3, 2, 1, 0)
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}
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}
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// Duplicate vector element to vector or scalar
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_p64)
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@(require_results, enable_target_feature = "neon")
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vget_low_p64 :: #force_inline proc "c" (a: poly64x2_t) -> poly64x1_t {
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when ODIN_ENDIAN == .Little {
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return transmute(poly64x1_t)simd.extract(a, 0)
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} else {
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a := simd.shuffle(a, a, 1, 0)
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return transmute(poly64x1_t)simd.extract(a, 0)
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}
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}
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// Duplicate vector element to vector or scalar
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)
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@(require_results, enable_target_feature = "neon")
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vget_high_p8 :: #force_inline proc "c" (a: poly8x16_t) -> poly8x8_t {
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when ODIN_ENDIAN == .Little {
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return simd.shuffle(a, a, 8, 9, 10, 11, 12, 13, 14, 15)
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} else {
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a := simd.shuffle(a, a, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
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b := simd.shuffle(a, a, 8, 9, 10, 11, 12, 13, 14, 15)
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return simd.shuffle(b, b, 7, 6, 5, 4, 3, 2, 1, 0)
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}
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}
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// Duplicate vector element to vector or scalar
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)
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@(require_results, enable_target_feature = "neon")
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vget_high_p16 :: #force_inline proc "c" (a: poly16x8_t) -> poly16x4_t {
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when ODIN_ENDIAN == .Little {
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return simd.shuffle(a, a, 4, 5, 6, 7)
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} else {
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a := simd.shuffle(a, a, 7, 6, 5, 4, 3, 2, 1, 0)
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b := simd.shuffle(a, a, 4, 5, 6, 7)
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return simd.shuffle(b, b, 3, 2, 1, 0)
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}
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}
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// Duplicate vector element to vector or scalar
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p64)
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@(require_results, enable_target_feature = "neon")
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vget_high_p64 :: #force_inline proc "c" (a: poly64x2_t) -> poly64x1_t {
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when ODIN_ENDIAN == .Little {
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return transmute(poly64x1_t)simd.extract(a, 1)
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} else {
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a := simd.shuffle(a, a, 1, 0)
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return transmute(poly64x1_t)simd.extract(a, 1)
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}
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}
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// Bitwise exclusive OR
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)
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@(require_results, enable_target_feature = "neon")
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vadd_p8 :: #force_inline proc "c" (a, b: poly8x8_t) -> poly8x8_t {
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return simd.bit_xor(a, b)
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}
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// Bitwise exclusive OR
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)
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@(require_results, enable_target_feature = "neon")
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vadd_p16 :: #force_inline proc "c" (a, b: poly16x4_t) -> poly16x4_t {
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return simd.bit_xor(a, b)
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}
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// Bitwise exclusive OR
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)
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@(require_results, enable_target_feature = "neon")
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vadd_p64 :: #force_inline proc "c" (a, b: poly64x1_t) -> poly64x1_t {
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return simd.bit_xor(a, b)
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}
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// Bitwise exclusive OR
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)
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@(require_results, enable_target_feature = "neon")
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vaddq_p8 :: #force_inline proc "c" (a, b: poly8x16_t) -> poly8x16_t {
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return simd.bit_xor(a, b)
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}
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// Bitwise exclusive OR
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)
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@(require_results, enable_target_feature = "neon")
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vaddq_p16 :: #force_inline proc "c" (a, b: poly16x8_t) -> poly16x8_t {
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return simd.bit_xor(a, b)
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}
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// Bitwise exclusive OR
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)
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@(require_results, enable_target_feature = "neon")
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vaddq_p64 :: #force_inline proc "c" (a, b: poly64x2_t) -> poly64x2_t {
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return simd.bit_xor(a, b)
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}
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// Bitwise exclusive OR
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)
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@(require_results, enable_target_feature = "neon")
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vaddq_p128 :: #force_inline proc "c" (a, b: poly128_t) -> poly128_t {
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return a ~ b
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}
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// Polynomial multiply
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)
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@(require_results, enable_target_feature = "neon")
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vmul_p8 :: #force_inline proc "c" (a, b: poly8x8_t) -> poly8x8_t {
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return _vmul_p8(a, b)
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}
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// Polynomial multiply
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//
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// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)
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@(require_results, enable_target_feature = "neon")
|
||||
vmulq_p8 :: #force_inline proc "c" (a, b: poly8x16_t) -> poly8x16_t {
|
||||
return _vmulq_p8(a, b)
|
||||
}
|
||||
|
||||
// Polynomial multiply long
|
||||
//
|
||||
// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)
|
||||
@(require_results, enable_target_feature = "neon")
|
||||
vmull_p8 :: #force_inline proc "c" (a, b: poly8x8_t) -> poly16x8_t {
|
||||
return _vmull_p8(a, b)
|
||||
}
|
||||
|
||||
when ODIN_ARCH == .arm64 {
|
||||
// Polynomial multiply long
|
||||
//
|
||||
// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)
|
||||
@(require_results, enable_target_feature = "neon")
|
||||
vmull_high_p8 :: #force_inline proc "c" (a, b: poly8x16_t) -> poly16x8_t {
|
||||
a := vget_high_p8(a)
|
||||
b := vget_high_p8(b)
|
||||
return vmull_p8(a, b)
|
||||
}
|
||||
|
||||
// Polynomial multiply long
|
||||
//
|
||||
// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)
|
||||
@(require_results, enable_target_feature = "neon,aes")
|
||||
vmull_p64 :: #force_inline proc "c" (a, b: poly64_t) -> poly128_t {
|
||||
return transmute(poly128_t)_vmull_p64(a, b)
|
||||
}
|
||||
|
||||
// Polynomial multiply long
|
||||
//
|
||||
// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)
|
||||
@(require_results, enable_target_feature = "neon,aes")
|
||||
vmull_high_p64 :: #force_inline proc "c" (a, b: poly64x2_t) -> poly128_t {
|
||||
return vmull_p64(vgetq_lane_p64(a, 1), vgetq_lane_p64(b, 1))
|
||||
}
|
||||
}
|
||||
|
||||
@(private, default_calling_convention = "none")
|
||||
foreign _ {
|
||||
@(link_name = "llvm.aarch64.neon.pmul.v8i8" when ODIN_ARCH == .arm64 else "llvm.arm.neon.vmulp.v8i8")
|
||||
_vmul_p8 :: proc(a, b: poly8x8_t) -> poly8x8_t ---
|
||||
@(link_name = "llvm.aarch64.neon.pmul.v16i8" when ODIN_ARCH == .arm64 else "llvm.arm.neon.vmulp.v16i8")
|
||||
_vmulq_p8 :: proc(a, b: poly8x16_t) -> poly8x16_t ---
|
||||
@(link_name = "llvm.aarch64.neon.pmull.v8i16" when ODIN_ARCH == .arm64 else "llvm.arm.neon.vmullp.v8i16")
|
||||
_vmull_p8 :: proc(a, b: poly8x8_t) -> poly16x8_t ---
|
||||
}
|
||||
|
||||
when ODIN_ARCH == .arm64 {
|
||||
@(private, default_calling_convention = "none")
|
||||
foreign _ {
|
||||
@(link_name = "llvm.aarch64.neon.pmull64")
|
||||
_vmull_p64 :: proc(a, b: poly64_t) -> int8x16_t ---
|
||||
}
|
||||
}
|
||||
@@ -7,6 +7,21 @@ uint16_t :: u16
|
||||
uint32_t :: u32
|
||||
uint64_t :: u64
|
||||
|
||||
poly8_t :: u8
|
||||
poly16_t :: u16
|
||||
poly64_t :: u64
|
||||
poly128_t :: u128
|
||||
|
||||
uint8x16_t :: #simd[16]u8
|
||||
uint32x4_t :: #simd[4]u32
|
||||
uint64x2_t :: #simd[2]u64
|
||||
|
||||
int32_t :: i32
|
||||
int8x16_t :: #simd[16]i8
|
||||
|
||||
poly8x8_t :: #simd[8]poly8_t
|
||||
poly8x16_t :: #simd[16]poly8_t
|
||||
poly16x4_t :: #simd[4]poly16_t
|
||||
poly16x8_t :: #simd[8]poly16_t
|
||||
poly64x1_t :: #simd[1]poly64_t
|
||||
poly64x2_t :: #simd[2]poly64_t
|
||||
|
||||
Reference in New Issue
Block a user