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rexcode/arm32: masks that let one form answer for another, and four missing shapes
The one-register-and-modified-immediate forms left the op bit and the Q
bit out of their masks. Those two bits are the whole difference between
VMOV and VMVN and between the D and Q widths, so a handful of D-form
entries answered for words that were neither -- a Q-width VMOV decoded
as a D-width VMVN. With them pinned the matrix has to be complete, and
it was not: only four of the ten cmodes had Q forms at all. Both
mnemonics now carry the full set, with cmode 1110 going to VMOV.I64
rather than VMVN when op is set, and cmode 1111 belonging to VMOV
alone.
VLDM and VSTM name their addressing mode, as LDM and STM do, so they
are VLDMIA and VLDMDB rather than one mnemonic apiece -- and the
decrement-before forms, which always write back, had no entries at all.
The broadcast structure loads are not mnemonics of their own. VLD2R and
friends are how the encoding is named, not how it is written: an
assembler writes `vld2.8 {d0[], d1[]}, [r0]`, a VLD2 with an all-lanes
list. They join VLD2, VLD3 and VLD4 as the forms they are, and the list
carries the spacing bit 5 gives it.
VFMA against bfloat16 names which half of each pair it takes on the
mnemonic, bottom or top. It had one form covering the top half under
the plain name and none for the bottom.
Every word the A32 sweep produces now round-trips through llvm-mc or is
one llvm's own disassembly cannot: 985 exact, 177 with no assemblable
text, 38 reserved, and PSB CSYNC and TSB CSYNC, which llvm does not
implement for AArch32.
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA
This commit is contained in:
Brendan Punsky
@@ -497,6 +497,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
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case .NEON_D_LIST_ALL:
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n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
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return op_reg_run(Register(REG_DPR | u16(n)), 1, 1, true)
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case .NEON_D_LIST_ALL_2, .NEON_D_LIST_ALL_3, .NEON_D_LIST_ALL_4:
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n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
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count := u8(2 + (int(enc) - int(Operand_Encoding.NEON_D_LIST_ALL_2)))
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return op_reg_run(Register(REG_DPR | u16(n)), count,
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((word >> 5) & 1) != 0 ? 2 : 1, true)
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case .NEON_LANE_D_8, .NEON_LANE_D_16, .NEON_LANE_D_32, .NEON_LANE_D_8_2, .NEON_LANE_D_16_2, .NEON_LANE_D_32_2, .NEON_LANE_D_8_3, .NEON_LANE_D_16_3, .NEON_LANE_D_32_3, .NEON_LANE_D_8_4, .NEON_LANE_D_16_4, .NEON_LANE_D_32_4:
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n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)
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shift, mask, count := neon_lane_shape(enc)
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@@ -541,6 +541,10 @@ pack_operand_inline :: #force_inline proc(
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// Only Vd; the count lives in the form's type field.
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n := u32(reg_hw(op.reg)) & 0x1F
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return ((n >> 4) & 1) << 22 | (n & 0xF) << 12
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case .NEON_D_LIST_ALL_2, .NEON_D_LIST_ALL_3, .NEON_D_LIST_ALL_4:
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// Same, plus the spacing, which bit 5 carries.
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n := u32(reg_hw(op.reg)) & 0x1F
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return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | (op.list.stride > 1 ? u32(1) : 0) << 5
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case .NEON_LANE_D_8, .NEON_LANE_D_16, .NEON_LANE_D_32, .NEON_LANE_D_8_2, .NEON_LANE_D_16_2, .NEON_LANE_D_32_2, .NEON_LANE_D_8_3, .NEON_LANE_D_16_3, .NEON_LANE_D_32_3, .NEON_LANE_D_8_4, .NEON_LANE_D_16_4, .NEON_LANE_D_32_4:
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n := u32(reg_hw(op.reg)) & 0x1F
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shift, mask, _ := neon_lane_shape(enc)
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@@ -367,6 +367,9 @@ Operand_Encoding :: enum u8 {
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NEON_D_LIST_3X, // {d2, d4, d6} -- spaced
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NEON_D_LIST_4X, // {d2, d4, d6, d8} -- spaced
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NEON_D_LIST_ALL, // {d2[]} -- to all lanes
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// The structure loads that broadcast take a list of two, three or four,
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// and bit 5 spaces it -- `{d0[], d2[]}` rather than `{d0[], d1[]}`.
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NEON_D_LIST_ALL_2, NEON_D_LIST_ALL_3, NEON_D_LIST_ALL_4,
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// VLD1/VST1 single-lane: Vd plus the lane index, whose width and position
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// follow the element size -- bits 7:5 for .8, 7:6 for .16, bit 7 for .32.
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// Verified against llvm-mc.
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@@ -708,6 +708,10 @@ inst_vfnma_s_s_s :: #force_inline proc "contextless" (dst: Register, s
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emit_vfnma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnma_s_s_s(dst, src, src2)) }
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inst_vfnms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfnms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnms_s_s_s(dst, src, src2)) }
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inst_vfmab_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfmab_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmab_q_q_q(dst, src, src2)) }
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inst_vfmat_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMAT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
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emit_vfmat_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmat_q_q_q(dst, src, src2)) }
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inst_vabs_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VABS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vabs_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vabs_s_s(dst, src)) }
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inst_vneg_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VNEG, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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@@ -762,10 +766,14 @@ inst_vldr_s_mem :: #force_inline proc "contextless" (dst: Register, s
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emit_vldr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldr_s_mem(dst, src)) }
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inst_vstr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} }
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emit_vstr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstr_s_mem(dst, src)) }
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inst_vldm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VLDM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_vldm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vldm_r_slist(dst, regs)) }
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inst_vstm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VSTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_vstm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vstm_r_slist(dst, regs)) }
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inst_vldmia_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VLDMIA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_vldmia_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vldmia_r_slist(dst, regs)) }
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inst_vldmdb_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VLDMDB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_vldmdb_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vldmdb_r_slist(dst, regs)) }
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inst_vstmia_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VSTMIA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_vstmia_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vstmia_r_slist(dst, regs)) }
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inst_vstmdb_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VSTMDB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} }
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emit_vstmdb_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vstmdb_r_slist(dst, regs)) }
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inst_vpush_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} }
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emit_vpush_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpush_slist(regs)) }
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inst_vpop_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPOP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} }
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@@ -1100,12 +1108,6 @@ inst_vmovx_s_s :: #force_inline proc "contextless" (dst: Register, s
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emit_vmovx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovx_s_s(dst, src)) }
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inst_vins_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VINS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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emit_vins_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vins_s_s(dst, src)) }
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inst_vld2r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld2r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2r_dlist_mem(regs, src)) }
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inst_vld3r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld3r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3r_dlist_mem(regs, src)) }
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inst_vld4r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
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emit_vld4r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4r_dlist_mem(regs, src)) }
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inst_it_cond_imm4 :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .IT, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_imm(imm), op_imm(imm2), {}, {}}} }
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emit_it_cond_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_it_cond_imm4(imm, imm2)) }
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inst_tt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
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@@ -1983,6 +1985,10 @@ inst_vfnma :: inst_vfnma_s_s_s
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emit_vfnma :: emit_vfnma_s_s_s
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inst_vfnms :: inst_vfnms_s_s_s
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emit_vfnms :: emit_vfnms_s_s_s
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inst_vfmab :: inst_vfmab_q_q_q
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emit_vfmab :: emit_vfmab_q_q_q
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inst_vfmat :: inst_vfmat_q_q_q
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emit_vfmat :: emit_vfmat_q_q_q
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inst_vabs :: inst_vabs_s_s
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emit_vabs :: emit_vabs_s_s
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inst_vneg :: inst_vneg_s_s
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@@ -2019,10 +2025,14 @@ inst_vldr :: inst_vldr_s_mem
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emit_vldr :: emit_vldr_s_mem
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inst_vstr :: inst_vstr_s_mem
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emit_vstr :: emit_vstr_s_mem
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inst_vldm :: inst_vldm_r_slist
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emit_vldm :: emit_vldm_r_slist
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inst_vstm :: inst_vstm_r_slist
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emit_vstm :: emit_vstm_r_slist
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inst_vldmia :: inst_vldmia_r_slist
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emit_vldmia :: emit_vldmia_r_slist
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inst_vldmdb :: inst_vldmdb_r_slist
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emit_vldmdb :: emit_vldmdb_r_slist
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inst_vstmia :: inst_vstmia_r_slist
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emit_vstmia :: emit_vstmia_r_slist
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inst_vstmdb :: inst_vstmdb_r_slist
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emit_vstmdb :: emit_vstmdb_r_slist
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inst_vpush :: inst_vpush_slist
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emit_vpush :: emit_vpush_slist
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inst_vpop :: inst_vpop_slist
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@@ -2303,12 +2313,6 @@ inst_vmovx :: inst_vmovx_s_s
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emit_vmovx :: emit_vmovx_s_s
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inst_vins :: inst_vins_s_s
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emit_vins :: emit_vins_s_s
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inst_vld2r :: inst_vld2r_dlist_mem
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emit_vld2r :: emit_vld2r_dlist_mem
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inst_vld3r :: inst_vld3r_dlist_mem
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emit_vld3r :: emit_vld3r_dlist_mem
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inst_vld4r :: inst_vld4r_dlist_mem
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emit_vld4r :: emit_vld4r_dlist_mem
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inst_it :: inst_it_cond_imm4
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emit_it :: emit_it_cond_imm4
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inst_tt :: inst_tt_r_r
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@@ -232,6 +232,9 @@ Mnemonic :: enum u16 {
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VADD, VSUB, VMUL, VDIV,
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VMLA, VMLS, VNMUL, VNMLA, VNMLS,
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VFMA, VFMS, VFNMA, VFNMS,
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// The bfloat16 multiply-accumulates name which half of each pair they
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// take, bottom or top, on the mnemonic.
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VFMAB, VFMAT,
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VABS, VNEG, VSQRT,
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VCMP, VCMPE,
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@@ -243,7 +246,8 @@ Mnemonic :: enum u16 {
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VMOV, // many forms (reg-reg, reg-imm, GPR-FPR)
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VMRS, VMSR, // FPSCR/coprocessor access
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VLDR, VSTR,
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VLDM, VSTM,
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// The addressing mode is part of the name, as it is for LDM and STM.
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VLDMIA, VLDMDB, VSTMIA, VSTMDB,
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VPUSH, VPOP,
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VSEL, // ARMv8 conditional select
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@@ -346,8 +350,8 @@ Mnemonic :: enum u16 {
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// -- MVE gather/scatter (vector offset addressing) ----------------------
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// -- NEON compare-with-zero (distinct encodings from reg-vs-reg) --------
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// -- NEON replicate loads (broadcast one element to all lanes) ----------
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// VLD1R already covered in VLD1; these are the 2/3/4 variants.
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VLD2R, VLD3R, VLD4R,
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// The broadcast structure loads are VLD2/VLD3/VLD4 with an all-lanes
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// list, not mnemonics of their own -- that is how they are written.
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// -- NEON single-element-lane load/store (lane form, not multi-vec) -----
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// -- VFP fixed-point conversions (with #fbits operand) ------------------
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@@ -1402,7 +1402,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
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// MVE FP vector + scalar
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{.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
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{.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
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{.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}},
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},
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.VFMAB = {
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{.VFMAB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300810, 0xFFB00F70, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}},
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},
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.VFMAT = {
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{.VFMAT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F70, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}},
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},
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.VFMS = {
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{.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}},
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@@ -1468,23 +1473,31 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
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// 1110 .I8 → 0xF2800E10
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// 1111 .F32 (special: high bit = 0) → 0xF2800F10 (limited to specific imm patterns)
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// 1110 op=1 + bit 5 set → .I64 → 0xF2800E30
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{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000
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{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1)
|
||||
// One register and a modified immediate: the cmode picks how the
|
||||
// eight-bit field expands, and op tells VMOV from VMVN.
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800010, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800210, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800250, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800410, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800450, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800610, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800650, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800810, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800A10, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800A50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800C10, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800C50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800D10, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800D50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E10, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800F10, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
|
||||
{.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E30, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}},
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}},
|
||||
// Q forms (Q=1, bit 6 = 1)
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q
|
||||
{.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q
|
||||
// ---- VMOV scalar to/from GPR (lane access) ----
|
||||
// VMOV.<size> Rt, Dn[idx]: cond 1110 U opc1 1 Vn Rt 1011 N opc2 1 0000
|
||||
// VMOV.<size> Dn[idx], Rt: cond 1110 0 opc1 0 Vn Rt 1011 N opc2 1 0000
|
||||
@@ -1507,17 +1520,25 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VMVN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}},
|
||||
{.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}},
|
||||
// VMVN immediate: 1111 0010 1 D 000 imm3 Vd cmode 0 Q 1 1 imm4 (op=1)
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
// One register and a modified immediate: the cmode picks how the
|
||||
// eight-bit field expands, and op tells VMOV from VMVN.
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800030, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800070, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800230, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800270, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800430, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800470, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800630, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800670, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800830, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800870, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800A30, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800A70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800C30, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800C70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800D30, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800D70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
// Q forms
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
|
||||
{.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}},
|
||||
// MVE VMVN Qd, Qm
|
||||
{.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}},
|
||||
},
|
||||
@@ -1646,13 +1667,25 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
|
||||
// VLDM / VSTM (multiple S or D regs): cond 110 P U D W L Rn Vd 101 sz imm8
|
||||
// IA = P=0 U=1 ; DB = P=1 U=0 ; W=1 writeback; L=1 load / 0 store.
|
||||
.VLDM = {
|
||||
{.VLDM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {}},
|
||||
{.VLDM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {}},
|
||||
.VLDMIA = {
|
||||
{.VLDMIA, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_S_LIST, .NONE, .NONE}, 0x0C900A00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
{.VLDMIA, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_D_LIST, .NONE, .NONE}, 0x0C900B00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
{.VLDMIA, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_S_LIST, .NONE, .NONE}, 0x0CB00A00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
{.VLDMIA, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_D_LIST, .NONE, .NONE}, 0x0CB00B00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
},
|
||||
.VSTM = {
|
||||
{.VSTM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {}},
|
||||
{.VSTM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {}},
|
||||
.VLDMDB = {
|
||||
{.VLDMDB, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_S_LIST, .NONE, .NONE}, 0x0D300A00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
{.VLDMDB, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_D_LIST, .NONE, .NONE}, 0x0D300B00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
},
|
||||
.VSTMIA = {
|
||||
{.VSTMIA, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_S_LIST, .NONE, .NONE}, 0x0C800A00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
{.VSTMIA, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_D_LIST, .NONE, .NONE}, 0x0C800B00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
{.VSTMIA, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_S_LIST, .NONE, .NONE}, 0x0CA00A00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
{.VSTMIA, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_D_LIST, .NONE, .NONE}, 0x0CA00B00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
},
|
||||
.VSTMDB = {
|
||||
{.VSTMDB, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_S_LIST, .NONE, .NONE}, 0x0D200A00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
{.VSTMDB, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32_WB, .VFP_D_LIST, .NONE, .NONE}, 0x0D200B00, 0x0FB00F00, .VFPV2, .A32, {}, {}},
|
||||
},
|
||||
.VPUSH = {
|
||||
{.VPUSH, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {}},
|
||||
@@ -2403,6 +2436,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_2, .RN_A32, .NONE, .NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_2, .RN_A32, .NONE, .NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_2, .RN_A32, .NONE, .NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
// The broadcast form: one element to every lane.
|
||||
{.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_ALL_2, .RN_A32, .NONE, .NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
},
|
||||
.VST2 = {
|
||||
{.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
@@ -2418,6 +2453,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_3, .RN_A32, .NONE, .NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_3, .RN_A32, .NONE, .NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_3, .RN_A32, .NONE, .NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
// The broadcast form: one element to every lane.
|
||||
{.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_ALL_3, .RN_A32, .NONE, .NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
},
|
||||
.VST3 = {
|
||||
{.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
@@ -2432,6 +2469,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_4, .RN_A32, .NONE, .NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_4, .RN_A32, .NONE, .NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}},
|
||||
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_4, .RN_A32, .NONE, .NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}},
|
||||
// The broadcast form: one element to every lane.
|
||||
{.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_ALL_4, .RN_A32, .NONE, .NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
},
|
||||
.VST4 = {
|
||||
{.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
@@ -2938,23 +2977,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
|
||||
// 1111 0011 1011 size 10 Vd op 0 0 1 Q M 0 Vm (float; op selects EQ/GE/GT/LE/LT)
|
||||
|
||||
// =========================================================================
|
||||
// NEON replicate loads (broadcast single element to all lanes)
|
||||
// =========================================================================
|
||||
// 1111 0100 1 D 10 Rn Vd 11 N size T a Rm
|
||||
// N=00 VLD1R, 01 VLD2R, 10 VLD3R, 11 VLD4R
|
||||
// VLD{2,3,4}R replicate forms (LLVM-verified for .8 element size):
|
||||
// vld2.8 {d1[], d2[]}, [r2] = 0xF4A2_1D0F -> base 0xF4A0_0D0F
|
||||
// vld3.8 {d1[], d2[], d3[]}, [r2] = 0xF4A2_1E0F -> base 0xF4A0_0E0F
|
||||
// vld4.8 {d1[], d2[], d3[], d4[]}, [r2] = 0xF4A2_1F0F -> base 0xF4A0_0F0F
|
||||
.VLD2R = {
|
||||
{.VLD2R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
},
|
||||
.VLD3R = {
|
||||
{.VLD3R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
},
|
||||
.VLD4R = {
|
||||
{.VLD4R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}},
|
||||
},
|
||||
|
||||
// =========================================================================
|
||||
// NEON single-element-lane load/store (one element, with lane index)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -8,7 +8,7 @@ package rexcode_arm32_generated
|
||||
import lib "../.."
|
||||
|
||||
@(rodata)
|
||||
ENCODE_FORMS := [1701]lib.Encoding{
|
||||
ENCODE_FORMS := [1722]lib.Encoding{
|
||||
// .AND
|
||||
{ .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
|
||||
@@ -1013,7 +1013,6 @@ ENCODE_FORMS := [1701]lib.Encoding{
|
||||
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
|
||||
{ .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
|
||||
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} },
|
||||
// .VFMS
|
||||
{ .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} },
|
||||
{ .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} },
|
||||
@@ -1029,6 +1028,10 @@ ENCODE_FORMS := [1701]lib.Encoding{
|
||||
{ .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} },
|
||||
{ .VFNMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} },
|
||||
{ .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} },
|
||||
// .VFMAB
|
||||
{ .VFMAB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300810, 0xFFB00F70, .BF16, .A32, {}, {.BF16,.NONE} },
|
||||
// .VFMAT
|
||||
{ .VFMAT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F70, .BF16, .A32, {}, {.BF16,.NONE} },
|
||||
// .VABS
|
||||
{ .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} },
|
||||
{ .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} },
|
||||
@@ -1143,21 +1146,27 @@ ENCODE_FORMS := [1701]lib.Encoding{
|
||||
{ .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.VM_S_PLUS1}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.VM_S_PLUS1,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800010, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800210, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800250, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800410, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800450, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800610, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800650, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800810, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A10, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A50, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C10, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C50, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D10, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D50, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E10, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F10, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} },
|
||||
{ .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E30, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
{ .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} },
|
||||
{ .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.NEON_LANE_VN_32,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} },
|
||||
@@ -1176,12 +1185,22 @@ ENCODE_FORMS := [1701]lib.Encoding{
|
||||
// .VSTR
|
||||
{ .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
// .VLDM
|
||||
{ .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
// .VSTM
|
||||
{ .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
// .VLDMIA
|
||||
{ .VLDMIA, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VLDMIA, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VLDMIA, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_S_LIST,.NONE,.NONE}, 0x0CB00A00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VLDMIA, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_D_LIST,.NONE,.NONE}, 0x0CB00B00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
// .VLDMDB
|
||||
{ .VLDMDB, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_S_LIST,.NONE,.NONE}, 0x0D300A00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VLDMDB, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_D_LIST,.NONE,.NONE}, 0x0D300B00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
// .VSTMIA
|
||||
{ .VSTMIA, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VSTMIA, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VSTMIA, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_S_LIST,.NONE,.NONE}, 0x0CA00A00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VSTMIA, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_D_LIST,.NONE,.NONE}, 0x0CA00B00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
// .VSTMDB
|
||||
{ .VSTMDB, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_S_LIST,.NONE,.NONE}, 0x0D200A00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VSTMDB, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32_WB,.VFP_D_LIST,.NONE,.NONE}, 0x0D200B00, 0x0FB00F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
// .VPUSH
|
||||
{ .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} },
|
||||
@@ -1475,16 +1494,22 @@ ENCODE_FORMS := [1701]lib.Encoding{
|
||||
// .VMVN
|
||||
{ .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800030, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800070, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800230, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800270, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800430, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800470, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800630, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800670, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800830, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800870, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A30, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A70, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C30, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C70, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D30, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D70, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} },
|
||||
{ .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} },
|
||||
// .VMOVN
|
||||
{ .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} },
|
||||
@@ -1856,18 +1881,21 @@ ENCODE_FORMS := [1701]lib.Encoding{
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL_2,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .VLD3
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL_3,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .VLD4
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
|
||||
{ .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL_4,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .VST1
|
||||
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
{ .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
@@ -1977,12 +2005,6 @@ ENCODE_FORMS := [1701]lib.Encoding{
|
||||
{ .VMOVX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true}, {.F16,.NONE} },
|
||||
// .VINS
|
||||
{ .VINS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true}, {.F16,.NONE} },
|
||||
// .VLD2R
|
||||
{ .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .VLD3R
|
||||
{ .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .VLD4R
|
||||
{ .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} },
|
||||
// .IT
|
||||
{ .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {}, {.NONE,.NONE} },
|
||||
// .TT
|
||||
@@ -2576,323 +2598,324 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
|
||||
.VNMUL = { 718, 2},
|
||||
.VNMLA = { 720, 2},
|
||||
.VNMLS = { 722, 2},
|
||||
.VFMA = { 724, 8},
|
||||
.VFMS = { 732, 6},
|
||||
.VFNMA = { 738, 3},
|
||||
.VFNMS = { 741, 3},
|
||||
.VABS = { 744, 12},
|
||||
.VNEG = { 756, 12},
|
||||
.VSQRT = { 768, 3},
|
||||
.VCMP = { 771, 8},
|
||||
.VCMPE = { 779, 4},
|
||||
.VCVT = { 783, 35},
|
||||
.VCVTB = { 818, 2},
|
||||
.VCVTT = { 820, 2},
|
||||
.VCVTA = { 822, 2},
|
||||
.VCVTN = { 824, 2},
|
||||
.VCVTP = { 826, 2},
|
||||
.VCVTM = { 828, 2},
|
||||
.VCVTR = { 830, 4},
|
||||
.VMOV = { 834, 33},
|
||||
.VMRS = { 867, 1},
|
||||
.VMSR = { 868, 1},
|
||||
.VLDR = { 869, 2},
|
||||
.VSTR = { 871, 2},
|
||||
.VLDM = { 873, 2},
|
||||
.VSTM = { 875, 2},
|
||||
.VPUSH = { 877, 2},
|
||||
.VPOP = { 879, 2},
|
||||
.VSEL = { 881, 2},
|
||||
.VMAXNM = { 883, 2},
|
||||
.VMINNM = { 885, 2},
|
||||
.VRINTA = { 887, 3},
|
||||
.VRINTN = { 890, 3},
|
||||
.VRINTP = { 893, 3},
|
||||
.VRINTM = { 896, 3},
|
||||
.VRINTR = { 899, 2},
|
||||
.VRINTZ = { 901, 3},
|
||||
.VRINTX = { 904, 3},
|
||||
.VADDL = { 907, 6},
|
||||
.VADDW = { 913, 6},
|
||||
.VSUBL = { 919, 6},
|
||||
.VSUBW = { 925, 6},
|
||||
.VHADD = { 931, 9},
|
||||
.VHSUB = { 940, 9},
|
||||
.VRHADD = { 949, 3},
|
||||
.VQADD = { 952, 11},
|
||||
.VQSUB = { 963, 11},
|
||||
.VMULL = { 974, 11},
|
||||
.VMLAL = { 985, 10},
|
||||
.VMLSL = { 995, 10},
|
||||
.VQDMULL = { 1005, 4},
|
||||
.VQDMLAL = { 1009, 4},
|
||||
.VQDMLSL = { 1013, 4},
|
||||
.VQDMULH = { 1017, 8},
|
||||
.VQRDMULH = { 1025, 8},
|
||||
.VQRDMLAH = { 1033, 8},
|
||||
.VQRDMLSH = { 1041, 8},
|
||||
.VABA = { 1049, 8},
|
||||
.VABAL = { 1057, 6},
|
||||
.VABD = { 1063, 10},
|
||||
.VABDL = { 1073, 6},
|
||||
.VAND = { 1079, 3},
|
||||
.VBIC = { 1082, 15},
|
||||
.VORR = { 1097, 15},
|
||||
.VORN = { 1112, 3},
|
||||
.VEOR = { 1115, 3},
|
||||
.VBSL = { 1118, 2},
|
||||
.VBIT = { 1120, 2},
|
||||
.VBIF = { 1122, 2},
|
||||
.VMVN = { 1124, 13},
|
||||
.VMOVN = { 1137, 3},
|
||||
.VQMOVN = { 1140, 6},
|
||||
.VQMOVUN = { 1146, 3},
|
||||
.VMOVL = { 1149, 6},
|
||||
.VTST = { 1155, 6},
|
||||
.VCEQ = { 1161, 14},
|
||||
.VCGE = { 1175, 16},
|
||||
.VCGT = { 1191, 16},
|
||||
.VCLE = { 1207, 18},
|
||||
.VCLT = { 1225, 18},
|
||||
.VACGE = { 1243, 2},
|
||||
.VACGT = { 1245, 2},
|
||||
.VACLE = { 1247, 2},
|
||||
.VACLT = { 1249, 2},
|
||||
.VMAX = { 1251, 13},
|
||||
.VMIN = { 1264, 13},
|
||||
.VPMAX = { 1277, 5},
|
||||
.VPMIN = { 1282, 5},
|
||||
.VPADD = { 1287, 5},
|
||||
.VPADDL = { 1292, 6},
|
||||
.VPADAL = { 1298, 4},
|
||||
.VRECPE = { 1302, 4},
|
||||
.VRECPS = { 1306, 2},
|
||||
.VRSQRTE = { 1308, 4},
|
||||
.VRSQRTS = { 1312, 2},
|
||||
.VSHL = { 1314, 9},
|
||||
.VSHR = { 1323, 3},
|
||||
.VSRA = { 1326, 3},
|
||||
.VRSHL = { 1329, 5},
|
||||
.VRSHR = { 1334, 3},
|
||||
.VRSRA = { 1337, 2},
|
||||
.VSLI = { 1339, 2},
|
||||
.VSRI = { 1341, 2},
|
||||
.VQSHL = { 1343, 7},
|
||||
.VQSHRN = { 1350, 1},
|
||||
.VQSHRUN = { 1351, 1},
|
||||
.VQRSHL = { 1352, 16},
|
||||
.VQRSHRN = { 1368, 1},
|
||||
.VQRSHRUN = { 1369, 1},
|
||||
.VSHRN = { 1370, 1},
|
||||
.VRSHRN = { 1371, 1},
|
||||
.VSHLL = { 1372, 4},
|
||||
.VCLS = { 1376, 6},
|
||||
.VCLZ = { 1382, 6},
|
||||
.VCNT = { 1388, 2},
|
||||
.VREV16 = { 1390, 2},
|
||||
.VREV32 = { 1392, 4},
|
||||
.VREV64 = { 1396, 6},
|
||||
.VEXT = { 1402, 2},
|
||||
.VTBL = { 1404, 4},
|
||||
.VTBX = { 1408, 4},
|
||||
.VTRN = { 1412, 6},
|
||||
.VUZP = { 1418, 5},
|
||||
.VZIP = { 1423, 5},
|
||||
.VDUP = { 1428, 5},
|
||||
.VSWP = { 1433, 2},
|
||||
.VLD1 = { 1435, 8},
|
||||
.VLD2 = { 1443, 6},
|
||||
.VLD3 = { 1449, 5},
|
||||
.VLD4 = { 1454, 5},
|
||||
.VST1 = { 1459, 7},
|
||||
.VST2 = { 1466, 6},
|
||||
.VST3 = { 1472, 5},
|
||||
.VST4 = { 1477, 5},
|
||||
.AESE = { 1482, 1},
|
||||
.AESD = { 1483, 1},
|
||||
.AESMC = { 1484, 1},
|
||||
.AESIMC = { 1485, 1},
|
||||
.SHA1H = { 1486, 1},
|
||||
.SHA1SU0 = { 1487, 1},
|
||||
.SHA1SU1 = { 1488, 1},
|
||||
.SHA1C = { 1489, 1},
|
||||
.SHA1M = { 1490, 1},
|
||||
.SHA1P = { 1491, 1},
|
||||
.SHA256H = { 1492, 1},
|
||||
.SHA256H2 = { 1493, 1},
|
||||
.SHA256SU0 = { 1494, 1},
|
||||
.SHA256SU1 = { 1495, 1},
|
||||
.VJCVT = { 1496, 1},
|
||||
.VSDOT = { 1497, 4},
|
||||
.VUDOT = { 1501, 4},
|
||||
.VDOT = { 1505, 2},
|
||||
.VMMLA = { 1507, 1},
|
||||
.VFMAL = { 1508, 2},
|
||||
.VFMSL = { 1510, 2},
|
||||
.VCMLA = { 1512, 5},
|
||||
.VCADD = { 1517, 2},
|
||||
.VSMMLA = { 1519, 1},
|
||||
.VUMMLA = { 1520, 1},
|
||||
.VUSMMLA = { 1521, 1},
|
||||
.VSUDOT = { 1522, 2},
|
||||
.VUSDOT = { 1524, 4},
|
||||
.VQABS = { 1528, 1},
|
||||
.VQNEG = { 1529, 1},
|
||||
.VMOVX = { 1530, 1},
|
||||
.VINS = { 1531, 1},
|
||||
.VLD2R = { 1532, 1},
|
||||
.VLD3R = { 1533, 1},
|
||||
.VLD4R = { 1534, 1},
|
||||
.IT = { 1535, 1},
|
||||
.TT = { 1536, 1},
|
||||
.TTT = { 1537, 1},
|
||||
.TTA = { 1538, 1},
|
||||
.TTAT = { 1539, 1},
|
||||
.SG = { 1540, 1},
|
||||
.BXNS = { 1541, 1},
|
||||
.BLXNS = { 1542, 1},
|
||||
.PAC = { 1543, 1},
|
||||
.PACBTI = { 1544, 1},
|
||||
.AUT = { 1545, 1},
|
||||
.AUTG = { 1546, 1},
|
||||
.BTI = { 1547, 1},
|
||||
.WLS = { 1548, 1},
|
||||
.WLSTP = { 1549, 1},
|
||||
.DLS = { 1550, 1},
|
||||
.DLSTP = { 1551, 1},
|
||||
.LE = { 1552, 1},
|
||||
.LETP = { 1553, 1},
|
||||
.LCTP = { 1554, 1},
|
||||
.BF = { 1555, 1},
|
||||
.BFX = { 1556, 1},
|
||||
.BFL = { 1557, 1},
|
||||
.BFLX = { 1558, 1},
|
||||
.BFCSEL = { 1559, 1},
|
||||
.CX1 = { 1560, 1},
|
||||
.CX1A = { 1561, 1},
|
||||
.CX1D = { 1562, 1},
|
||||
.CX1DA = { 1563, 1},
|
||||
.CX2 = { 1564, 1},
|
||||
.CX2A = { 1565, 1},
|
||||
.CX2D = { 1566, 1},
|
||||
.CX2DA = { 1567, 1},
|
||||
.CX3 = { 1568, 1},
|
||||
.CX3A = { 1569, 1},
|
||||
.CX3D = { 1570, 1},
|
||||
.CX3DA = { 1571, 1},
|
||||
.VCX1 = { 1572, 2},
|
||||
.VCX1A = { 1574, 2},
|
||||
.VCX2 = { 1576, 2},
|
||||
.VCX2A = { 1578, 2},
|
||||
.VCX3 = { 1580, 2},
|
||||
.VCX3A = { 1582, 2},
|
||||
.VPT = { 1584, 1},
|
||||
.VPST = { 1585, 1},
|
||||
.VPSEL = { 1586, 1},
|
||||
.VPNOT = { 1587, 1},
|
||||
.VCTP = { 1588, 1},
|
||||
.VADDV = { 1589, 1},
|
||||
.VADDVA = { 1590, 1},
|
||||
.VADDLV = { 1591, 1},
|
||||
.VADDLVA = { 1592, 1},
|
||||
.VMAXV = { 1593, 1},
|
||||
.VMAXAV = { 1594, 1},
|
||||
.VMINV = { 1595, 1},
|
||||
.VMINAV = { 1596, 1},
|
||||
.VMAXNMV = { 1597, 1},
|
||||
.VMAXNMAV = { 1598, 1},
|
||||
.VMINNMV = { 1599, 1},
|
||||
.VMINNMAV = { 1600, 1},
|
||||
.VABAV = { 1601, 1},
|
||||
.VMLADAV = { 1602, 1},
|
||||
.VMLADAVA = { 1603, 1},
|
||||
.VMLADAVX = { 1604, 1},
|
||||
.VMLADAVAX = { 1605, 1},
|
||||
.VMLALDAV = { 1606, 1},
|
||||
.VMLALDAVA = { 1607, 1},
|
||||
.VMLALDAVX = { 1608, 1},
|
||||
.VMLALDAVAX = { 1609, 1},
|
||||
.VMLSDAV = { 1610, 1},
|
||||
.VMLSDAVA = { 1611, 1},
|
||||
.VMLSDAVX = { 1612, 1},
|
||||
.VMLSDAVAX = { 1613, 1},
|
||||
.VMLSLDAV = { 1614, 1},
|
||||
.VMLSLDAVA = { 1615, 1},
|
||||
.VMLSLDAVX = { 1616, 1},
|
||||
.VMLSLDAVAX = { 1617, 1},
|
||||
.VRMLALDAVH = { 1618, 1},
|
||||
.VRMLALDAVHA = { 1619, 1},
|
||||
.VRMLALDAVHX = { 1620, 1},
|
||||
.VRMLALDAVHAX = { 1621, 1},
|
||||
.VRMLSLDAVH = { 1622, 1},
|
||||
.VRMLSLDAVHA = { 1623, 1},
|
||||
.VRMLSLDAVHX = { 1624, 1},
|
||||
.VRMLSLDAVHAX = { 1625, 1},
|
||||
.VMLAV = { 1626, 1},
|
||||
.VMLAVA = { 1627, 1},
|
||||
.VMLSV = { 1628, 1},
|
||||
.VMLSVA = { 1629, 1},
|
||||
.VCMUL = { 1630, 1},
|
||||
.VHCADD = { 1631, 2},
|
||||
.VBRSR = { 1633, 1},
|
||||
.VSHLC = { 1634, 1},
|
||||
.VDDUP = { 1635, 1},
|
||||
.VIDUP = { 1636, 1},
|
||||
.VDWDUP = { 1637, 1},
|
||||
.VIWDUP = { 1638, 1},
|
||||
.VMOVNB = { 1639, 1},
|
||||
.VMOVNT = { 1640, 1},
|
||||
.VQMOVNB = { 1641, 1},
|
||||
.VQMOVNT = { 1642, 1},
|
||||
.VQMOVUNB = { 1643, 1},
|
||||
.VQMOVUNT = { 1644, 1},
|
||||
.VSHLLB = { 1645, 1},
|
||||
.VSHLLT = { 1646, 1},
|
||||
.VMULLB = { 1647, 1},
|
||||
.VMULLT = { 1648, 1},
|
||||
.VMLALB = { 1649, 1},
|
||||
.VMLALT = { 1650, 1},
|
||||
.VMLSLB = { 1651, 1},
|
||||
.VMLSLT = { 1652, 1},
|
||||
.VSHRNB = { 1653, 1},
|
||||
.VSHRNT = { 1654, 1},
|
||||
.VRSHRNB = { 1655, 1},
|
||||
.VRSHRNT = { 1656, 1},
|
||||
.VQSHRNB = { 1657, 1},
|
||||
.VQSHRNT = { 1658, 1},
|
||||
.VQRSHRNB = { 1659, 1},
|
||||
.VQRSHRNT = { 1660, 1},
|
||||
.VQSHRUNB = { 1661, 1},
|
||||
.VQSHRUNT = { 1662, 1},
|
||||
.VQRSHRUNB = { 1663, 1},
|
||||
.VQRSHRUNT = { 1664, 1},
|
||||
.VQDMLADH = { 1665, 1},
|
||||
.VQDMLADHX = { 1666, 1},
|
||||
.VQDMLSDH = { 1667, 1},
|
||||
.VQDMLSDHX = { 1668, 1},
|
||||
.VQRDMLADH = { 1669, 1},
|
||||
.VQRDMLADHX = { 1670, 1},
|
||||
.VQRDMLSDH = { 1671, 1},
|
||||
.VQRDMLSDHX = { 1672, 1},
|
||||
.VLDRB = { 1673, 2},
|
||||
.VLDRH = { 1675, 2},
|
||||
.VLDRW = { 1677, 2},
|
||||
.VLDRD = { 1679, 2},
|
||||
.VSTRB = { 1681, 2},
|
||||
.VSTRH = { 1683, 2},
|
||||
.VSTRW = { 1685, 2},
|
||||
.VSTRD = { 1687, 2},
|
||||
.VLD20 = { 1689, 1},
|
||||
.VLD21 = { 1690, 1},
|
||||
.VLD40 = { 1691, 1},
|
||||
.VLD41 = { 1692, 1},
|
||||
.VLD42 = { 1693, 1},
|
||||
.VLD43 = { 1694, 1},
|
||||
.VST20 = { 1695, 1},
|
||||
.VST21 = { 1696, 1},
|
||||
.VST40 = { 1697, 1},
|
||||
.VST41 = { 1698, 1},
|
||||
.VST42 = { 1699, 1},
|
||||
.VST43 = { 1700, 1},
|
||||
._COUNT = { 1701, 0},
|
||||
.VFMA = { 724, 7},
|
||||
.VFMS = { 731, 6},
|
||||
.VFNMA = { 737, 3},
|
||||
.VFNMS = { 740, 3},
|
||||
.VFMAB = { 743, 1},
|
||||
.VFMAT = { 744, 1},
|
||||
.VABS = { 745, 12},
|
||||
.VNEG = { 757, 12},
|
||||
.VSQRT = { 769, 3},
|
||||
.VCMP = { 772, 8},
|
||||
.VCMPE = { 780, 4},
|
||||
.VCVT = { 784, 35},
|
||||
.VCVTB = { 819, 2},
|
||||
.VCVTT = { 821, 2},
|
||||
.VCVTA = { 823, 2},
|
||||
.VCVTN = { 825, 2},
|
||||
.VCVTP = { 827, 2},
|
||||
.VCVTM = { 829, 2},
|
||||
.VCVTR = { 831, 4},
|
||||
.VMOV = { 835, 39},
|
||||
.VMRS = { 874, 1},
|
||||
.VMSR = { 875, 1},
|
||||
.VLDR = { 876, 2},
|
||||
.VSTR = { 878, 2},
|
||||
.VLDMIA = { 880, 4},
|
||||
.VLDMDB = { 884, 2},
|
||||
.VSTMIA = { 886, 4},
|
||||
.VSTMDB = { 890, 2},
|
||||
.VPUSH = { 892, 2},
|
||||
.VPOP = { 894, 2},
|
||||
.VSEL = { 896, 2},
|
||||
.VMAXNM = { 898, 2},
|
||||
.VMINNM = { 900, 2},
|
||||
.VRINTA = { 902, 3},
|
||||
.VRINTN = { 905, 3},
|
||||
.VRINTP = { 908, 3},
|
||||
.VRINTM = { 911, 3},
|
||||
.VRINTR = { 914, 2},
|
||||
.VRINTZ = { 916, 3},
|
||||
.VRINTX = { 919, 3},
|
||||
.VADDL = { 922, 6},
|
||||
.VADDW = { 928, 6},
|
||||
.VSUBL = { 934, 6},
|
||||
.VSUBW = { 940, 6},
|
||||
.VHADD = { 946, 9},
|
||||
.VHSUB = { 955, 9},
|
||||
.VRHADD = { 964, 3},
|
||||
.VQADD = { 967, 11},
|
||||
.VQSUB = { 978, 11},
|
||||
.VMULL = { 989, 11},
|
||||
.VMLAL = { 1000, 10},
|
||||
.VMLSL = { 1010, 10},
|
||||
.VQDMULL = { 1020, 4},
|
||||
.VQDMLAL = { 1024, 4},
|
||||
.VQDMLSL = { 1028, 4},
|
||||
.VQDMULH = { 1032, 8},
|
||||
.VQRDMULH = { 1040, 8},
|
||||
.VQRDMLAH = { 1048, 8},
|
||||
.VQRDMLSH = { 1056, 8},
|
||||
.VABA = { 1064, 8},
|
||||
.VABAL = { 1072, 6},
|
||||
.VABD = { 1078, 10},
|
||||
.VABDL = { 1088, 6},
|
||||
.VAND = { 1094, 3},
|
||||
.VBIC = { 1097, 15},
|
||||
.VORR = { 1112, 15},
|
||||
.VORN = { 1127, 3},
|
||||
.VEOR = { 1130, 3},
|
||||
.VBSL = { 1133, 2},
|
||||
.VBIT = { 1135, 2},
|
||||
.VBIF = { 1137, 2},
|
||||
.VMVN = { 1139, 19},
|
||||
.VMOVN = { 1158, 3},
|
||||
.VQMOVN = { 1161, 6},
|
||||
.VQMOVUN = { 1167, 3},
|
||||
.VMOVL = { 1170, 6},
|
||||
.VTST = { 1176, 6},
|
||||
.VCEQ = { 1182, 14},
|
||||
.VCGE = { 1196, 16},
|
||||
.VCGT = { 1212, 16},
|
||||
.VCLE = { 1228, 18},
|
||||
.VCLT = { 1246, 18},
|
||||
.VACGE = { 1264, 2},
|
||||
.VACGT = { 1266, 2},
|
||||
.VACLE = { 1268, 2},
|
||||
.VACLT = { 1270, 2},
|
||||
.VMAX = { 1272, 13},
|
||||
.VMIN = { 1285, 13},
|
||||
.VPMAX = { 1298, 5},
|
||||
.VPMIN = { 1303, 5},
|
||||
.VPADD = { 1308, 5},
|
||||
.VPADDL = { 1313, 6},
|
||||
.VPADAL = { 1319, 4},
|
||||
.VRECPE = { 1323, 4},
|
||||
.VRECPS = { 1327, 2},
|
||||
.VRSQRTE = { 1329, 4},
|
||||
.VRSQRTS = { 1333, 2},
|
||||
.VSHL = { 1335, 9},
|
||||
.VSHR = { 1344, 3},
|
||||
.VSRA = { 1347, 3},
|
||||
.VRSHL = { 1350, 5},
|
||||
.VRSHR = { 1355, 3},
|
||||
.VRSRA = { 1358, 2},
|
||||
.VSLI = { 1360, 2},
|
||||
.VSRI = { 1362, 2},
|
||||
.VQSHL = { 1364, 7},
|
||||
.VQSHRN = { 1371, 1},
|
||||
.VQSHRUN = { 1372, 1},
|
||||
.VQRSHL = { 1373, 16},
|
||||
.VQRSHRN = { 1389, 1},
|
||||
.VQRSHRUN = { 1390, 1},
|
||||
.VSHRN = { 1391, 1},
|
||||
.VRSHRN = { 1392, 1},
|
||||
.VSHLL = { 1393, 4},
|
||||
.VCLS = { 1397, 6},
|
||||
.VCLZ = { 1403, 6},
|
||||
.VCNT = { 1409, 2},
|
||||
.VREV16 = { 1411, 2},
|
||||
.VREV32 = { 1413, 4},
|
||||
.VREV64 = { 1417, 6},
|
||||
.VEXT = { 1423, 2},
|
||||
.VTBL = { 1425, 4},
|
||||
.VTBX = { 1429, 4},
|
||||
.VTRN = { 1433, 6},
|
||||
.VUZP = { 1439, 5},
|
||||
.VZIP = { 1444, 5},
|
||||
.VDUP = { 1449, 5},
|
||||
.VSWP = { 1454, 2},
|
||||
.VLD1 = { 1456, 8},
|
||||
.VLD2 = { 1464, 7},
|
||||
.VLD3 = { 1471, 6},
|
||||
.VLD4 = { 1477, 6},
|
||||
.VST1 = { 1483, 7},
|
||||
.VST2 = { 1490, 6},
|
||||
.VST3 = { 1496, 5},
|
||||
.VST4 = { 1501, 5},
|
||||
.AESE = { 1506, 1},
|
||||
.AESD = { 1507, 1},
|
||||
.AESMC = { 1508, 1},
|
||||
.AESIMC = { 1509, 1},
|
||||
.SHA1H = { 1510, 1},
|
||||
.SHA1SU0 = { 1511, 1},
|
||||
.SHA1SU1 = { 1512, 1},
|
||||
.SHA1C = { 1513, 1},
|
||||
.SHA1M = { 1514, 1},
|
||||
.SHA1P = { 1515, 1},
|
||||
.SHA256H = { 1516, 1},
|
||||
.SHA256H2 = { 1517, 1},
|
||||
.SHA256SU0 = { 1518, 1},
|
||||
.SHA256SU1 = { 1519, 1},
|
||||
.VJCVT = { 1520, 1},
|
||||
.VSDOT = { 1521, 4},
|
||||
.VUDOT = { 1525, 4},
|
||||
.VDOT = { 1529, 2},
|
||||
.VMMLA = { 1531, 1},
|
||||
.VFMAL = { 1532, 2},
|
||||
.VFMSL = { 1534, 2},
|
||||
.VCMLA = { 1536, 5},
|
||||
.VCADD = { 1541, 2},
|
||||
.VSMMLA = { 1543, 1},
|
||||
.VUMMLA = { 1544, 1},
|
||||
.VUSMMLA = { 1545, 1},
|
||||
.VSUDOT = { 1546, 2},
|
||||
.VUSDOT = { 1548, 4},
|
||||
.VQABS = { 1552, 1},
|
||||
.VQNEG = { 1553, 1},
|
||||
.VMOVX = { 1554, 1},
|
||||
.VINS = { 1555, 1},
|
||||
.IT = { 1556, 1},
|
||||
.TT = { 1557, 1},
|
||||
.TTT = { 1558, 1},
|
||||
.TTA = { 1559, 1},
|
||||
.TTAT = { 1560, 1},
|
||||
.SG = { 1561, 1},
|
||||
.BXNS = { 1562, 1},
|
||||
.BLXNS = { 1563, 1},
|
||||
.PAC = { 1564, 1},
|
||||
.PACBTI = { 1565, 1},
|
||||
.AUT = { 1566, 1},
|
||||
.AUTG = { 1567, 1},
|
||||
.BTI = { 1568, 1},
|
||||
.WLS = { 1569, 1},
|
||||
.WLSTP = { 1570, 1},
|
||||
.DLS = { 1571, 1},
|
||||
.DLSTP = { 1572, 1},
|
||||
.LE = { 1573, 1},
|
||||
.LETP = { 1574, 1},
|
||||
.LCTP = { 1575, 1},
|
||||
.BF = { 1576, 1},
|
||||
.BFX = { 1577, 1},
|
||||
.BFL = { 1578, 1},
|
||||
.BFLX = { 1579, 1},
|
||||
.BFCSEL = { 1580, 1},
|
||||
.CX1 = { 1581, 1},
|
||||
.CX1A = { 1582, 1},
|
||||
.CX1D = { 1583, 1},
|
||||
.CX1DA = { 1584, 1},
|
||||
.CX2 = { 1585, 1},
|
||||
.CX2A = { 1586, 1},
|
||||
.CX2D = { 1587, 1},
|
||||
.CX2DA = { 1588, 1},
|
||||
.CX3 = { 1589, 1},
|
||||
.CX3A = { 1590, 1},
|
||||
.CX3D = { 1591, 1},
|
||||
.CX3DA = { 1592, 1},
|
||||
.VCX1 = { 1593, 2},
|
||||
.VCX1A = { 1595, 2},
|
||||
.VCX2 = { 1597, 2},
|
||||
.VCX2A = { 1599, 2},
|
||||
.VCX3 = { 1601, 2},
|
||||
.VCX3A = { 1603, 2},
|
||||
.VPT = { 1605, 1},
|
||||
.VPST = { 1606, 1},
|
||||
.VPSEL = { 1607, 1},
|
||||
.VPNOT = { 1608, 1},
|
||||
.VCTP = { 1609, 1},
|
||||
.VADDV = { 1610, 1},
|
||||
.VADDVA = { 1611, 1},
|
||||
.VADDLV = { 1612, 1},
|
||||
.VADDLVA = { 1613, 1},
|
||||
.VMAXV = { 1614, 1},
|
||||
.VMAXAV = { 1615, 1},
|
||||
.VMINV = { 1616, 1},
|
||||
.VMINAV = { 1617, 1},
|
||||
.VMAXNMV = { 1618, 1},
|
||||
.VMAXNMAV = { 1619, 1},
|
||||
.VMINNMV = { 1620, 1},
|
||||
.VMINNMAV = { 1621, 1},
|
||||
.VABAV = { 1622, 1},
|
||||
.VMLADAV = { 1623, 1},
|
||||
.VMLADAVA = { 1624, 1},
|
||||
.VMLADAVX = { 1625, 1},
|
||||
.VMLADAVAX = { 1626, 1},
|
||||
.VMLALDAV = { 1627, 1},
|
||||
.VMLALDAVA = { 1628, 1},
|
||||
.VMLALDAVX = { 1629, 1},
|
||||
.VMLALDAVAX = { 1630, 1},
|
||||
.VMLSDAV = { 1631, 1},
|
||||
.VMLSDAVA = { 1632, 1},
|
||||
.VMLSDAVX = { 1633, 1},
|
||||
.VMLSDAVAX = { 1634, 1},
|
||||
.VMLSLDAV = { 1635, 1},
|
||||
.VMLSLDAVA = { 1636, 1},
|
||||
.VMLSLDAVX = { 1637, 1},
|
||||
.VMLSLDAVAX = { 1638, 1},
|
||||
.VRMLALDAVH = { 1639, 1},
|
||||
.VRMLALDAVHA = { 1640, 1},
|
||||
.VRMLALDAVHX = { 1641, 1},
|
||||
.VRMLALDAVHAX = { 1642, 1},
|
||||
.VRMLSLDAVH = { 1643, 1},
|
||||
.VRMLSLDAVHA = { 1644, 1},
|
||||
.VRMLSLDAVHX = { 1645, 1},
|
||||
.VRMLSLDAVHAX = { 1646, 1},
|
||||
.VMLAV = { 1647, 1},
|
||||
.VMLAVA = { 1648, 1},
|
||||
.VMLSV = { 1649, 1},
|
||||
.VMLSVA = { 1650, 1},
|
||||
.VCMUL = { 1651, 1},
|
||||
.VHCADD = { 1652, 2},
|
||||
.VBRSR = { 1654, 1},
|
||||
.VSHLC = { 1655, 1},
|
||||
.VDDUP = { 1656, 1},
|
||||
.VIDUP = { 1657, 1},
|
||||
.VDWDUP = { 1658, 1},
|
||||
.VIWDUP = { 1659, 1},
|
||||
.VMOVNB = { 1660, 1},
|
||||
.VMOVNT = { 1661, 1},
|
||||
.VQMOVNB = { 1662, 1},
|
||||
.VQMOVNT = { 1663, 1},
|
||||
.VQMOVUNB = { 1664, 1},
|
||||
.VQMOVUNT = { 1665, 1},
|
||||
.VSHLLB = { 1666, 1},
|
||||
.VSHLLT = { 1667, 1},
|
||||
.VMULLB = { 1668, 1},
|
||||
.VMULLT = { 1669, 1},
|
||||
.VMLALB = { 1670, 1},
|
||||
.VMLALT = { 1671, 1},
|
||||
.VMLSLB = { 1672, 1},
|
||||
.VMLSLT = { 1673, 1},
|
||||
.VSHRNB = { 1674, 1},
|
||||
.VSHRNT = { 1675, 1},
|
||||
.VRSHRNB = { 1676, 1},
|
||||
.VRSHRNT = { 1677, 1},
|
||||
.VQSHRNB = { 1678, 1},
|
||||
.VQSHRNT = { 1679, 1},
|
||||
.VQRSHRNB = { 1680, 1},
|
||||
.VQRSHRNT = { 1681, 1},
|
||||
.VQSHRUNB = { 1682, 1},
|
||||
.VQSHRUNT = { 1683, 1},
|
||||
.VQRSHRUNB = { 1684, 1},
|
||||
.VQRSHRUNT = { 1685, 1},
|
||||
.VQDMLADH = { 1686, 1},
|
||||
.VQDMLADHX = { 1687, 1},
|
||||
.VQDMLSDH = { 1688, 1},
|
||||
.VQDMLSDHX = { 1689, 1},
|
||||
.VQRDMLADH = { 1690, 1},
|
||||
.VQRDMLADHX = { 1691, 1},
|
||||
.VQRDMLSDH = { 1692, 1},
|
||||
.VQRDMLSDHX = { 1693, 1},
|
||||
.VLDRB = { 1694, 2},
|
||||
.VLDRH = { 1696, 2},
|
||||
.VLDRW = { 1698, 2},
|
||||
.VLDRD = { 1700, 2},
|
||||
.VSTRB = { 1702, 2},
|
||||
.VSTRH = { 1704, 2},
|
||||
.VSTRW = { 1706, 2},
|
||||
.VSTRD = { 1708, 2},
|
||||
.VLD20 = { 1710, 1},
|
||||
.VLD21 = { 1711, 1},
|
||||
.VLD40 = { 1712, 1},
|
||||
.VLD41 = { 1713, 1},
|
||||
.VLD42 = { 1714, 1},
|
||||
.VLD43 = { 1715, 1},
|
||||
.VST20 = { 1716, 1},
|
||||
.VST21 = { 1717, 1},
|
||||
.VST40 = { 1718, 1},
|
||||
.VST41 = { 1719, 1},
|
||||
.VST42 = { 1720, 1},
|
||||
.VST43 = { 1721, 1},
|
||||
._COUNT = { 1722, 0},
|
||||
}
|
||||
|
||||
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@@ -392,7 +392,9 @@ run_smoke :: proc() {
|
||||
check("VFMSL Q", .VFMSL, 1, 0xFCA00850, 0xFFB00F50)
|
||||
check("VCVT BF16", .VCVT, 10, 0xF3B60600, 0xFFBF0FD0)
|
||||
check("VDOT BF16 D", .VDOT, 0, 0xFC000D00, 0xFFB00F10)
|
||||
check("VFMA BF16 Q", .VFMA, 7, 0xFC300850, 0xFFB00F50)
|
||||
// Bfloat16 names which half of each pair it takes on the mnemonic.
|
||||
check("VFMAB BF16 Q", .VFMAB, 0, 0xFC300810, 0xFFB00F70)
|
||||
check("VFMAT BF16 Q", .VFMAT, 0, 0xFC300850, 0xFFB00F70)
|
||||
check("VMMLA BF16 Q", .VMMLA, 0, 0xFC000C40, 0xFFB00F50)
|
||||
|
||||
// ---- Barriers / hints: ESB, PSB CSYNC, TSB CSYNC, CSDB, SB ----
|
||||
@@ -553,9 +555,11 @@ run_smoke :: proc() {
|
||||
check("VCLT D", .VCLT, 14, 0xF3B10200, 0xFFBB0FD0)
|
||||
|
||||
// ---- NEON replicate loads ----
|
||||
check("VLD2R", .VLD2R, 0, 0xF4A00D0F, 0xFFB00F0F)
|
||||
check("VLD3R", .VLD3R, 0, 0xF4A00E0F, 0xFFB00F0F)
|
||||
check("VLD4R", .VLD4R, 0, 0xF4A00F0F, 0xFFB00F0F)
|
||||
// The broadcast loads are VLD2/VLD3/VLD4 with an all-lanes list, and
|
||||
// that form leads each of their entry lists.
|
||||
check("VLD2 all-lanes", .VLD2, 6, 0xF4A00D0F, 0xFFB00F0F)
|
||||
check("VLD3 all-lanes", .VLD3, 5, 0xF4A00E0F, 0xFFB00F0F)
|
||||
check("VLD4 all-lanes", .VLD4, 5, 0xF4A00F0F, 0xFFB00F0F)
|
||||
|
||||
// ---- NEON single-element lane loads/stores ----
|
||||
check("VLD1 lane .8", .VLD1, 5, 0xF4A0000F, 0xFFB00F1F)
|
||||
|
||||
Reference in New Issue
Block a user