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rexcode/arm32: the fixed-point VCVT matrix, and three fields read as themselves

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The VFP fixed-point conversions were a handful of forms whose comments
named the 32-bit fixed-point variants but whose encodings all had `sx`
clear, so they were the 16-bit ones; two of them were duplicates
distinguished only by a looser mask. None of them decoded the fraction
width at all, because the operand slot had no encoding, so every one of
them printed `#0` -- and a `#0` fraction is not what any of these words
mean. The block is now the full matrix the architecture defines: three
floating-point widths by two fixed-point widths by four directions,
twenty-four forms. The fraction is the fixed-point width less the
imm4:i field, so the widest fraction is what a zero field encodes.

LSR and ASR reach a shift of 32 through a zero field -- a shift of zero
would be a MOV, so the encoding spends that value on the one amount
five bits cannot otherwise name. Both the standalone mnemonics and the
shifted operand of a data-processing instruction printed `#0`, which is
not the same instruction; PKHTB dropped its `asr #32` entirely, since a
zero amount prints as no shift at all.

USAT and USAT16 saturate to an unsigned width of zero to 31 and store
it as it stands, unlike SSAT and SSAT16, which store one less than a
signed width of one to 32. They had been sharing the signed encoding
and so read one too high.

The AES and SHA forms carry a bare element size -- `aese.8`,
`sha1c.32` -- and had no data type at all.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA
This commit is contained in:
Brendan Punsky
2026-08-29 00:42:57 -04:00
committed by Flāvius
parent 421262e84e
commit 9964798390
16 changed files with 1274 additions and 1198 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
core/rexcode/isa/arm32/decoder.odin
View File

@@ -269,6 +269,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
amt := u8((word >> 7) & 0x1F)
if st == .ROR && amt == 0 { return op_reg_shifted(reg, .RRX, 0) }
if st == .LSL && amt == 0 { return op_reg(reg) }
// A shift of zero is not a shift, so the field spends that
// spare value on 32 instead -- the one amount five bits cannot
// otherwise reach. LSL has no use for it and ROR spends it on
// RRX, so only these two.
if (st == .LSR || st == .ASR) && amt == 0 { return op_reg_shifted(reg, st, 32) }
return op_reg_shifted(reg, st, amt)
}
return op_reg(reg)
@@ -311,6 +316,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
// ---- A32 immediates ----
case .A32_IMM12: return op_imm(i64(word & 0xFFF))
case .A32_IMM_SHIFT: return op_imm(i64((word >> 7) & 0x1F))
case .A32_IMM_SHIFT_32:
// The LSR and ASR mnemonics reach 32 the same way a shifted operand
// does: a field of zero, since a shift of zero would be a MOV.
amt := (word >> 7) & 0x1F
return op_imm(i64(amt == 0 ? 32 : amt))
case .A32_SHIFT_TYPE: return op_imm(i64((word >> 5) & 0x3))
case .A32_IMM24:
// Ambiguous: A32_IMM24 is used both for branch displacements (B/BL,
@@ -537,9 +547,18 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
return op_imm(i64((word >> 18) & 0xF))
// ---- Saturate / bit field ----
case .VFP_FBITS:
// The fixed-point width is 16 or 32 by the sx bit, and the fraction
// is that less imm4:i -- so the widest fraction encodes as zero.
width: u32 = ((word >> 7) & 1) != 0 ? 32 : 16
return op_imm(i64(width - (((word & 0xF) << 1) | ((word >> 5) & 1))))
case .SAT_IMM5, .SAT_IMM5_T32:
// The field holds one less than the saturate position it names.
// SSAT and SSAT16 saturate to a signed width of one to 32, and the
// field holds one less than that. USAT and USAT16 saturate to an
// unsigned width of zero to 31, which the field holds as it stands.
return op_imm(i64(((word >> 16) & 0x1F) + 1))
case .SAT_IMM5_U, .SAT_IMM5_U_T32:
return op_imm(i64((word >> 16) & 0x1F))
case .BFX_WIDTH:
// One less than the width.
return op_imm(i64(((word >> 16) & 0x1F) + 1))

8
core/rexcode/isa/arm32/encoder.odin
View File

@@ -426,6 +426,7 @@ pack_operand_inline :: #force_inline proc(
// ---- A32 immediate field placements ----
case .A32_IMM12: return u32(op.immediate) & 0xFFF
case .A32_IMM_SHIFT: return (u32(op.immediate) & 0x1F) << 7
case .A32_IMM_SHIFT_32: return (u32(op.immediate) & 0x1F) << 7 // 32 wraps to 0, which is what encodes it
case .A32_SHIFT_TYPE: return (u32(op.immediate) & 0x3) << 5
case .A32_RS_SHIFT: return (u32(reg_hw(op.reg)) & 0xF) << 8
case .A32_IMM24:
@@ -660,8 +661,15 @@ pack_operand_inline :: #force_inline proc(
case .IT_MASK: return u32(op.immediate) & 0xFF
case .CPS_IFLAGS: return u32(op.immediate) & 0x1FF
case .HINT_FIELD: return u32(op.immediate) & 0xFF
case .VFP_FBITS:
// sx is a fixed bit of the form, so the width comes from its pattern.
width: u32 = ((form.bits >> 7) & 1) != 0 ? 32 : 16
imm := width - (u32(op.immediate) & 0x3F)
return ((imm >> 1) & 0xF) | (imm & 1) << 5
case .SAT_IMM5, .SAT_IMM5_T32, .BFX_WIDTH:
return ((u32(op.immediate) - 1) & 0x1F) << 16
case .SAT_IMM5_U, .SAT_IMM5_U_T32:
return (u32(op.immediate) & 0x1F) << 16
case .BFI_MSB:
// msb = lsb + width - 1; the lsb rides in whichever slot carries it.
lsb: u32 = 0

8
core/rexcode/isa/arm32/encoding_types.odin
View File

@@ -282,6 +282,7 @@ Operand_Encoding :: enum u8 {
// ---- Immediate field placements (A32) ----
A32_IMM12, // bits 11-0 (LDR/STR offset)
A32_IMM_SHIFT, // bits 11-7 (data-proc shift_imm)
A32_IMM_SHIFT_32, // same field, but a zero means 32 (LSR/ASR)
A32_SHIFT_TYPE, // bits 6-5
A32_RS_SHIFT, // bits 11-8 (RSR uses Rs register)
A32_IMM24, // bits 23-0 (B/BL/SVC)
@@ -410,8 +411,11 @@ Operand_Encoding :: enum u8 {
HINT_FIELD, // hint imm
// ---- Saturate ----
SAT_IMM5, // bits 20-16: SSAT/USAT saturate-to width
SAT_IMM5_T32, // Thumb-2 saturate amount
VFP_FBITS, // VCVT fixed-point fraction bits: width - (imm4:i)
SAT_IMM5, // bits 20-16: SSAT/SSAT16 saturate-to width, less one
SAT_IMM5_T32, // Thumb-2 signed saturate amount, less one
SAT_IMM5_U, // bits 20-16: USAT/USAT16 width, which is not biased
SAT_IMM5_U_T32, // Thumb-2 unsigned saturate amount
// ---- BFC/BFI/SBFX/UBFX ----
// SBFX/UBFX hold the width less one, where BFI/BFC hold the top bit's

86
core/rexcode/isa/arm32/tablegen/encoding_table.odin
View File

@@ -614,8 +614,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.USAT = {
{.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {}},
{.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
{.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5_U, .RM_A32, .NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {}},
{.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_U_T32, .RN_T32, .NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.SSAT16 = {
{.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}, {}},
@@ -623,8 +623,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.USAT16 = {
{.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {}},
{.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
{.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5_U, .RM_A32, .NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {}},
{.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_U_T32, .RN_T32, .NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
// ARMv6 USAD8 / USADA8
@@ -1547,24 +1547,34 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// VCVT.BF16.F32 D, Q
// vcvt.bf16.f32 d0, q1 = 0xF3B6_0642 -> base 0xF3B60600
{.VCVT, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {cond_in_28=false}, {.F16, .F32}},
// VCVT.S32.F32 Sd, Sd, #fbits -- to signed 32-bit fixed-point
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F32}},
// VCVT.U32.F32 Sd, Sd, #fbits
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16, .F32}},
// VCVT.F32.S32 Sd, Sd, #fbits -- from signed 32-bit fixed
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .S16}},
// VCVT.F32.U32 Sd, Sd, #fbits
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .U16}},
// VCVT.S16.F32 Sd, Sd, #fbits (sx=0 selects 16-bit fixed-point)
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16, .F32}},
// VCVT.F32.S16 Sd, Sd, #fbits
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32, .S16}},
// F64 variants (sz=1): change cp to 1011 (bit 8 = 1)
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F64}},
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .S16}},
// F16 variants (cp=1001, FEAT_FP16)
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16, .F16}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .S16}},
// VCVT between floating point and fixed point. The `sx` bit picks the
// fixed-point width -- clear for 16-bit, set for 32-bit -- and the
// number of fraction bits is that width less the imm4:i field, so a
// field of zero is the widest fraction rather than none at all.
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .S16}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBB0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .U16}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16, .F16}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBF0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U16, .F16}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBA09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .S32}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBB09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .U32}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBE09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S32, .F16}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBF09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U32, .F16}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .S16}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .U16}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F32}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16, .F32}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBA0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .S32}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBB0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .U32}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBE0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32, .F32}},
{.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBF0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32, .F32}},
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .S16}},
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBB0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .U16}},
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F64}},
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBF0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16, .F64}},
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBA0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .S32}},
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBB0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .U32}},
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBE0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32, .F64}},
{.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBF0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32, .F64}},
},
.VCVTB = {
// VCVTB.F32.F16 / .F16.F32
@@ -2610,21 +2620,21 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// NEON crypto (ARMv8 FEAT_AES / FEAT_SHA1 / FEAT_SHA256)
// AESE/AESD/AESMC/AESIMC: 1111 0011 1011 size 00 Vd 0011 op M 0 Vm (op=0 AESE, 1 AESD; bit 7 selects MC)
.AESE = { {.AESE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.AESD = { {.AESD, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.AESMC = { {.AESMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.AESIMC = { {.AESIMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.AESE = { {.AESE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ8, .NONE}} },
.AESD = { {.AESD, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ8, .NONE}} },
.AESMC = { {.AESMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ8, .NONE}} },
.AESIMC = { {.AESIMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ8, .NONE}} },
// SHA1 family
.SHA1H = { {.SHA1H, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA1SU1 = { {.SHA1SU1, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA256SU0 = { {.SHA256SU0, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA1C = { {.SHA1C, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA1P = { {.SHA1P, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA1M = { {.SHA1M, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA1SU0 = { {.SHA1SU0, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA256H = { {.SHA256H, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA256H2 = { {.SHA256H2, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA256SU1 = { {.SHA256SU1, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} },
.SHA1H = { {.SHA1H, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
.SHA1SU1 = { {.SHA1SU1, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
.SHA256SU0 = { {.SHA256SU0, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
.SHA1C = { {.SHA1C, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
.SHA1P = { {.SHA1P, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
.SHA1M = { {.SHA1M, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
.SHA1SU0 = { {.SHA1SU0, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
.SHA256H = { {.SHA256H, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
.SHA256H2 = { {.SHA256H2, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
.SHA256SU1 = { {.SHA256SU1, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} },
// =========================================================================
// §11 -- T16 Thumb-1 + T32 Thumb-2 (Thumb-only mnemonics)
@@ -2660,7 +2670,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.LSR = {
{.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {}},
{.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT_32, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {}},
{.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {}},
// T16 Format 1: LSR imm
{.LSR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}},
@@ -2672,7 +2682,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}},
},
.ASR = {
{.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {}},
{.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT_32, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {}},
{.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {}},
// T16 Format 1: ASR imm
{.ASR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}},

1638
core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin
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File diff suppressed because it is too large Load Diff

696
core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin
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@@ -8,7 +8,7 @@ package rexcode_arm32_generated
import lib "../.."
@(rodata)
ENCODE_FORMS := [1649]lib.Encoding{
ENCODE_FORMS := [1663]lib.Encoding{
// .AND
{ .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
@@ -171,14 +171,14 @@ ENCODE_FORMS := [1649]lib.Encoding{
{ .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .LSR
{ .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT_32,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .LSR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LSR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .ASR
{ .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} },
{ .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT_32,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} },
{ .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} },
{ .ASR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} },
{ .ASR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} },
@@ -286,14 +286,14 @@ ENCODE_FORMS := [1649]lib.Encoding{
{ .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} },
{ .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .USAT
{ .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} },
{ .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5_U,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} },
{ .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_U_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .SSAT16
{ .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} },
{ .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .USAT16
{ .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} },
{ .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
{ .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5_U,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} },
{ .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_U_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
// .QADD
{ .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} },
{ .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} },
@@ -1065,16 +1065,30 @@ ENCODE_FORMS := [1649]lib.Encoding{
{ .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} },
{ .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} },
{ .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16,.F32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.U16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U16,.F16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.U32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S32,.F16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U32,.F16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F32} },
{ .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F32} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U16} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F64} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S32} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U32} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F64} },
{ .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F64} },
// .VCVTB
{ .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} },
{ .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} },
@@ -1838,33 +1852,33 @@ ENCODE_FORMS := [1649]lib.Encoding{
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} },
{ .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} },
// .AESE
{ .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} },
// .AESD
{ .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} },
// .AESMC
{ .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} },
// .AESIMC
{ .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} },
// .SHA1H
{ .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .SHA1SU0
{ .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .SHA1SU1
{ .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .SHA1C
{ .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .SHA1M
{ .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .SHA1P
{ .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .SHA256H
{ .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .SHA256H2
{ .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .SHA256SU0
{ .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .SHA256SU1
{ .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} },
{ .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} },
// .VJCVT
{ .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} },
// .VSDOT
@@ -2521,314 +2535,314 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
.VSQRT = { 754, 3},
.VCMP = { 757, 8},
.VCMPE = { 765, 4},
.VCVT = { 769, 21},
.VCVTB = { 790, 2},
.VCVTT = { 792, 2},
.VCVTA = { 794, 2},
.VCVTN = { 796, 2},
.VCVTP = { 798, 2},
.VCVTM = { 800, 2},
.VCVTR = { 802, 4},
.VMOV = { 806, 33},
.VMRS = { 839, 1},
.VMSR = { 840, 1},
.VLDR = { 841, 2},
.VSTR = { 843, 2},
.VLDM = { 845, 2},
.VSTM = { 847, 2},
.VPUSH = { 849, 2},
.VPOP = { 851, 2},
.VSEL = { 853, 2},
.VMAXNM = { 855, 2},
.VMINNM = { 857, 2},
.VRINTA = { 859, 3},
.VRINTN = { 862, 3},
.VRINTP = { 865, 3},
.VRINTM = { 868, 3},
.VRINTR = { 871, 2},
.VRINTZ = { 873, 3},
.VRINTX = { 876, 3},
.VADDL = { 879, 6},
.VADDW = { 885, 6},
.VSUBL = { 891, 6},
.VSUBW = { 897, 6},
.VHADD = { 903, 9},
.VHSUB = { 912, 9},
.VRHADD = { 921, 3},
.VQADD = { 924, 11},
.VQSUB = { 935, 11},
.VMULL = { 946, 11},
.VMLAL = { 957, 10},
.VMLSL = { 967, 10},
.VQDMULL = { 977, 4},
.VQDMLAL = { 981, 4},
.VQDMLSL = { 985, 4},
.VQDMULH = { 989, 8},
.VQRDMULH = { 997, 8},
.VQRDMLAH = { 1005, 8},
.VQRDMLSH = { 1013, 8},
.VABA = { 1021, 8},
.VABAL = { 1029, 6},
.VABD = { 1035, 10},
.VABDL = { 1045, 6},
.VAND = { 1051, 3},
.VBIC = { 1054, 3},
.VORR = { 1057, 3},
.VORN = { 1060, 3},
.VEOR = { 1063, 3},
.VBSL = { 1066, 2},
.VBIT = { 1068, 2},
.VBIF = { 1070, 2},
.VMVN = { 1072, 13},
.VMOVN = { 1085, 3},
.VQMOVN = { 1088, 6},
.VQMOVUN = { 1094, 3},
.VMOVL = { 1097, 6},
.VTST = { 1103, 6},
.VCEQ = { 1109, 14},
.VCGE = { 1123, 16},
.VCGT = { 1139, 16},
.VCLE = { 1155, 18},
.VCLT = { 1173, 18},
.VACGE = { 1191, 2},
.VACGT = { 1193, 2},
.VACLE = { 1195, 2},
.VACLT = { 1197, 2},
.VMAX = { 1199, 13},
.VMIN = { 1212, 13},
.VPMAX = { 1225, 5},
.VPMIN = { 1230, 5},
.VPADD = { 1235, 5},
.VPADDL = { 1240, 6},
.VPADAL = { 1246, 4},
.VRECPE = { 1250, 4},
.VRECPS = { 1254, 2},
.VRSQRTE = { 1256, 4},
.VRSQRTS = { 1260, 2},
.VSHL = { 1262, 9},
.VSHR = { 1271, 3},
.VSRA = { 1274, 3},
.VRSHL = { 1277, 5},
.VRSHR = { 1282, 3},
.VRSRA = { 1285, 2},
.VSLI = { 1287, 2},
.VSRI = { 1289, 2},
.VQSHL = { 1291, 7},
.VQSHRN = { 1298, 1},
.VQSHRUN = { 1299, 1},
.VQRSHL = { 1300, 16},
.VQRSHRN = { 1316, 1},
.VQRSHRUN = { 1317, 1},
.VSHRN = { 1318, 1},
.VRSHRN = { 1319, 1},
.VSHLL = { 1320, 4},
.VCLS = { 1324, 6},
.VCLZ = { 1330, 6},
.VCNT = { 1336, 2},
.VREV16 = { 1338, 2},
.VREV32 = { 1340, 4},
.VREV64 = { 1344, 6},
.VEXT = { 1350, 2},
.VTBL = { 1352, 4},
.VTBX = { 1356, 4},
.VTRN = { 1360, 6},
.VUZP = { 1366, 5},
.VZIP = { 1371, 5},
.VDUP = { 1376, 5},
.VSWP = { 1381, 2},
.VLD1 = { 1383, 8},
.VLD2 = { 1391, 6},
.VLD3 = { 1397, 5},
.VLD4 = { 1402, 5},
.VST1 = { 1407, 7},
.VST2 = { 1414, 6},
.VST3 = { 1420, 5},
.VST4 = { 1425, 5},
.AESE = { 1430, 1},
.AESD = { 1431, 1},
.AESMC = { 1432, 1},
.AESIMC = { 1433, 1},
.SHA1H = { 1434, 1},
.SHA1SU0 = { 1435, 1},
.SHA1SU1 = { 1436, 1},
.SHA1C = { 1437, 1},
.SHA1M = { 1438, 1},
.SHA1P = { 1439, 1},
.SHA256H = { 1440, 1},
.SHA256H2 = { 1441, 1},
.SHA256SU0 = { 1442, 1},
.SHA256SU1 = { 1443, 1},
.VJCVT = { 1444, 1},
.VSDOT = { 1445, 4},
.VUDOT = { 1449, 4},
.VDOT = { 1453, 2},
.VMMLA = { 1455, 1},
.VFMAL = { 1456, 2},
.VFMSL = { 1458, 2},
.VCMLA = { 1460, 5},
.VCADD = { 1465, 2},
.VSMMLA = { 1467, 1},
.VUMMLA = { 1468, 1},
.VUSMMLA = { 1469, 1},
.VSUDOT = { 1470, 2},
.VUSDOT = { 1472, 4},
.VQABS = { 1476, 1},
.VQNEG = { 1477, 1},
.VMOVX = { 1478, 1},
.VINS = { 1479, 1},
.VLD2R = { 1480, 1},
.VLD3R = { 1481, 1},
.VLD4R = { 1482, 1},
.IT = { 1483, 1},
.TT = { 1484, 1},
.TTT = { 1485, 1},
.TTA = { 1486, 1},
.TTAT = { 1487, 1},
.SG = { 1488, 1},
.BXNS = { 1489, 1},
.BLXNS = { 1490, 1},
.PAC = { 1491, 1},
.PACBTI = { 1492, 1},
.AUT = { 1493, 1},
.AUTG = { 1494, 1},
.BTI = { 1495, 1},
.WLS = { 1496, 1},
.WLSTP = { 1497, 1},
.DLS = { 1498, 1},
.DLSTP = { 1499, 1},
.LE = { 1500, 1},
.LETP = { 1501, 1},
.LCTP = { 1502, 1},
.BF = { 1503, 1},
.BFX = { 1504, 1},
.BFL = { 1505, 1},
.BFLX = { 1506, 1},
.BFCSEL = { 1507, 1},
.CX1 = { 1508, 1},
.CX1A = { 1509, 1},
.CX1D = { 1510, 1},
.CX1DA = { 1511, 1},
.CX2 = { 1512, 1},
.CX2A = { 1513, 1},
.CX2D = { 1514, 1},
.CX2DA = { 1515, 1},
.CX3 = { 1516, 1},
.CX3A = { 1517, 1},
.CX3D = { 1518, 1},
.CX3DA = { 1519, 1},
.VCX1 = { 1520, 2},
.VCX1A = { 1522, 2},
.VCX2 = { 1524, 2},
.VCX2A = { 1526, 2},
.VCX3 = { 1528, 2},
.VCX3A = { 1530, 2},
.VPT = { 1532, 1},
.VPST = { 1533, 1},
.VPSEL = { 1534, 1},
.VPNOT = { 1535, 1},
.VCTP = { 1536, 1},
.VADDV = { 1537, 1},
.VADDVA = { 1538, 1},
.VADDLV = { 1539, 1},
.VADDLVA = { 1540, 1},
.VMAXV = { 1541, 1},
.VMAXAV = { 1542, 1},
.VMINV = { 1543, 1},
.VMINAV = { 1544, 1},
.VMAXNMV = { 1545, 1},
.VMAXNMAV = { 1546, 1},
.VMINNMV = { 1547, 1},
.VMINNMAV = { 1548, 1},
.VABAV = { 1549, 1},
.VMLADAV = { 1550, 1},
.VMLADAVA = { 1551, 1},
.VMLADAVX = { 1552, 1},
.VMLADAVAX = { 1553, 1},
.VMLALDAV = { 1554, 1},
.VMLALDAVA = { 1555, 1},
.VMLALDAVX = { 1556, 1},
.VMLALDAVAX = { 1557, 1},
.VMLSDAV = { 1558, 1},
.VMLSDAVA = { 1559, 1},
.VMLSDAVX = { 1560, 1},
.VMLSDAVAX = { 1561, 1},
.VMLSLDAV = { 1562, 1},
.VMLSLDAVA = { 1563, 1},
.VMLSLDAVX = { 1564, 1},
.VMLSLDAVAX = { 1565, 1},
.VRMLALDAVH = { 1566, 1},
.VRMLALDAVHA = { 1567, 1},
.VRMLALDAVHX = { 1568, 1},
.VRMLALDAVHAX = { 1569, 1},
.VRMLSLDAVH = { 1570, 1},
.VRMLSLDAVHA = { 1571, 1},
.VRMLSLDAVHX = { 1572, 1},
.VRMLSLDAVHAX = { 1573, 1},
.VMLAV = { 1574, 1},
.VMLAVA = { 1575, 1},
.VMLSV = { 1576, 1},
.VMLSVA = { 1577, 1},
.VCMUL = { 1578, 1},
.VHCADD = { 1579, 2},
.VBRSR = { 1581, 1},
.VSHLC = { 1582, 1},
.VDDUP = { 1583, 1},
.VIDUP = { 1584, 1},
.VDWDUP = { 1585, 1},
.VIWDUP = { 1586, 1},
.VMOVNB = { 1587, 1},
.VMOVNT = { 1588, 1},
.VQMOVNB = { 1589, 1},
.VQMOVNT = { 1590, 1},
.VQMOVUNB = { 1591, 1},
.VQMOVUNT = { 1592, 1},
.VSHLLB = { 1593, 1},
.VSHLLT = { 1594, 1},
.VMULLB = { 1595, 1},
.VMULLT = { 1596, 1},
.VMLALB = { 1597, 1},
.VMLALT = { 1598, 1},
.VMLSLB = { 1599, 1},
.VMLSLT = { 1600, 1},
.VSHRNB = { 1601, 1},
.VSHRNT = { 1602, 1},
.VRSHRNB = { 1603, 1},
.VRSHRNT = { 1604, 1},
.VQSHRNB = { 1605, 1},
.VQSHRNT = { 1606, 1},
.VQRSHRNB = { 1607, 1},
.VQRSHRNT = { 1608, 1},
.VQSHRUNB = { 1609, 1},
.VQSHRUNT = { 1610, 1},
.VQRSHRUNB = { 1611, 1},
.VQRSHRUNT = { 1612, 1},
.VQDMLADH = { 1613, 1},
.VQDMLADHX = { 1614, 1},
.VQDMLSDH = { 1615, 1},
.VQDMLSDHX = { 1616, 1},
.VQRDMLADH = { 1617, 1},
.VQRDMLADHX = { 1618, 1},
.VQRDMLSDH = { 1619, 1},
.VQRDMLSDHX = { 1620, 1},
.VLDRB = { 1621, 2},
.VLDRH = { 1623, 2},
.VLDRW = { 1625, 2},
.VLDRD = { 1627, 2},
.VSTRB = { 1629, 2},
.VSTRH = { 1631, 2},
.VSTRW = { 1633, 2},
.VSTRD = { 1635, 2},
.VLD20 = { 1637, 1},
.VLD21 = { 1638, 1},
.VLD40 = { 1639, 1},
.VLD41 = { 1640, 1},
.VLD42 = { 1641, 1},
.VLD43 = { 1642, 1},
.VST20 = { 1643, 1},
.VST21 = { 1644, 1},
.VST40 = { 1645, 1},
.VST41 = { 1646, 1},
.VST42 = { 1647, 1},
.VST43 = { 1648, 1},
._COUNT = { 1649, 0},
.VCVT = { 769, 35},
.VCVTB = { 804, 2},
.VCVTT = { 806, 2},
.VCVTA = { 808, 2},
.VCVTN = { 810, 2},
.VCVTP = { 812, 2},
.VCVTM = { 814, 2},
.VCVTR = { 816, 4},
.VMOV = { 820, 33},
.VMRS = { 853, 1},
.VMSR = { 854, 1},
.VLDR = { 855, 2},
.VSTR = { 857, 2},
.VLDM = { 859, 2},
.VSTM = { 861, 2},
.VPUSH = { 863, 2},
.VPOP = { 865, 2},
.VSEL = { 867, 2},
.VMAXNM = { 869, 2},
.VMINNM = { 871, 2},
.VRINTA = { 873, 3},
.VRINTN = { 876, 3},
.VRINTP = { 879, 3},
.VRINTM = { 882, 3},
.VRINTR = { 885, 2},
.VRINTZ = { 887, 3},
.VRINTX = { 890, 3},
.VADDL = { 893, 6},
.VADDW = { 899, 6},
.VSUBL = { 905, 6},
.VSUBW = { 911, 6},
.VHADD = { 917, 9},
.VHSUB = { 926, 9},
.VRHADD = { 935, 3},
.VQADD = { 938, 11},
.VQSUB = { 949, 11},
.VMULL = { 960, 11},
.VMLAL = { 971, 10},
.VMLSL = { 981, 10},
.VQDMULL = { 991, 4},
.VQDMLAL = { 995, 4},
.VQDMLSL = { 999, 4},
.VQDMULH = { 1003, 8},
.VQRDMULH = { 1011, 8},
.VQRDMLAH = { 1019, 8},
.VQRDMLSH = { 1027, 8},
.VABA = { 1035, 8},
.VABAL = { 1043, 6},
.VABD = { 1049, 10},
.VABDL = { 1059, 6},
.VAND = { 1065, 3},
.VBIC = { 1068, 3},
.VORR = { 1071, 3},
.VORN = { 1074, 3},
.VEOR = { 1077, 3},
.VBSL = { 1080, 2},
.VBIT = { 1082, 2},
.VBIF = { 1084, 2},
.VMVN = { 1086, 13},
.VMOVN = { 1099, 3},
.VQMOVN = { 1102, 6},
.VQMOVUN = { 1108, 3},
.VMOVL = { 1111, 6},
.VTST = { 1117, 6},
.VCEQ = { 1123, 14},
.VCGE = { 1137, 16},
.VCGT = { 1153, 16},
.VCLE = { 1169, 18},
.VCLT = { 1187, 18},
.VACGE = { 1205, 2},
.VACGT = { 1207, 2},
.VACLE = { 1209, 2},
.VACLT = { 1211, 2},
.VMAX = { 1213, 13},
.VMIN = { 1226, 13},
.VPMAX = { 1239, 5},
.VPMIN = { 1244, 5},
.VPADD = { 1249, 5},
.VPADDL = { 1254, 6},
.VPADAL = { 1260, 4},
.VRECPE = { 1264, 4},
.VRECPS = { 1268, 2},
.VRSQRTE = { 1270, 4},
.VRSQRTS = { 1274, 2},
.VSHL = { 1276, 9},
.VSHR = { 1285, 3},
.VSRA = { 1288, 3},
.VRSHL = { 1291, 5},
.VRSHR = { 1296, 3},
.VRSRA = { 1299, 2},
.VSLI = { 1301, 2},
.VSRI = { 1303, 2},
.VQSHL = { 1305, 7},
.VQSHRN = { 1312, 1},
.VQSHRUN = { 1313, 1},
.VQRSHL = { 1314, 16},
.VQRSHRN = { 1330, 1},
.VQRSHRUN = { 1331, 1},
.VSHRN = { 1332, 1},
.VRSHRN = { 1333, 1},
.VSHLL = { 1334, 4},
.VCLS = { 1338, 6},
.VCLZ = { 1344, 6},
.VCNT = { 1350, 2},
.VREV16 = { 1352, 2},
.VREV32 = { 1354, 4},
.VREV64 = { 1358, 6},
.VEXT = { 1364, 2},
.VTBL = { 1366, 4},
.VTBX = { 1370, 4},
.VTRN = { 1374, 6},
.VUZP = { 1380, 5},
.VZIP = { 1385, 5},
.VDUP = { 1390, 5},
.VSWP = { 1395, 2},
.VLD1 = { 1397, 8},
.VLD2 = { 1405, 6},
.VLD3 = { 1411, 5},
.VLD4 = { 1416, 5},
.VST1 = { 1421, 7},
.VST2 = { 1428, 6},
.VST3 = { 1434, 5},
.VST4 = { 1439, 5},
.AESE = { 1444, 1},
.AESD = { 1445, 1},
.AESMC = { 1446, 1},
.AESIMC = { 1447, 1},
.SHA1H = { 1448, 1},
.SHA1SU0 = { 1449, 1},
.SHA1SU1 = { 1450, 1},
.SHA1C = { 1451, 1},
.SHA1M = { 1452, 1},
.SHA1P = { 1453, 1},
.SHA256H = { 1454, 1},
.SHA256H2 = { 1455, 1},
.SHA256SU0 = { 1456, 1},
.SHA256SU1 = { 1457, 1},
.VJCVT = { 1458, 1},
.VSDOT = { 1459, 4},
.VUDOT = { 1463, 4},
.VDOT = { 1467, 2},
.VMMLA = { 1469, 1},
.VFMAL = { 1470, 2},
.VFMSL = { 1472, 2},
.VCMLA = { 1474, 5},
.VCADD = { 1479, 2},
.VSMMLA = { 1481, 1},
.VUMMLA = { 1482, 1},
.VUSMMLA = { 1483, 1},
.VSUDOT = { 1484, 2},
.VUSDOT = { 1486, 4},
.VQABS = { 1490, 1},
.VQNEG = { 1491, 1},
.VMOVX = { 1492, 1},
.VINS = { 1493, 1},
.VLD2R = { 1494, 1},
.VLD3R = { 1495, 1},
.VLD4R = { 1496, 1},
.IT = { 1497, 1},
.TT = { 1498, 1},
.TTT = { 1499, 1},
.TTA = { 1500, 1},
.TTAT = { 1501, 1},
.SG = { 1502, 1},
.BXNS = { 1503, 1},
.BLXNS = { 1504, 1},
.PAC = { 1505, 1},
.PACBTI = { 1506, 1},
.AUT = { 1507, 1},
.AUTG = { 1508, 1},
.BTI = { 1509, 1},
.WLS = { 1510, 1},
.WLSTP = { 1511, 1},
.DLS = { 1512, 1},
.DLSTP = { 1513, 1},
.LE = { 1514, 1},
.LETP = { 1515, 1},
.LCTP = { 1516, 1},
.BF = { 1517, 1},
.BFX = { 1518, 1},
.BFL = { 1519, 1},
.BFLX = { 1520, 1},
.BFCSEL = { 1521, 1},
.CX1 = { 1522, 1},
.CX1A = { 1523, 1},
.CX1D = { 1524, 1},
.CX1DA = { 1525, 1},
.CX2 = { 1526, 1},
.CX2A = { 1527, 1},
.CX2D = { 1528, 1},
.CX2DA = { 1529, 1},
.CX3 = { 1530, 1},
.CX3A = { 1531, 1},
.CX3D = { 1532, 1},
.CX3DA = { 1533, 1},
.VCX1 = { 1534, 2},
.VCX1A = { 1536, 2},
.VCX2 = { 1538, 2},
.VCX2A = { 1540, 2},
.VCX3 = { 1542, 2},
.VCX3A = { 1544, 2},
.VPT = { 1546, 1},
.VPST = { 1547, 1},
.VPSEL = { 1548, 1},
.VPNOT = { 1549, 1},
.VCTP = { 1550, 1},
.VADDV = { 1551, 1},
.VADDVA = { 1552, 1},
.VADDLV = { 1553, 1},
.VADDLVA = { 1554, 1},
.VMAXV = { 1555, 1},
.VMAXAV = { 1556, 1},
.VMINV = { 1557, 1},
.VMINAV = { 1558, 1},
.VMAXNMV = { 1559, 1},
.VMAXNMAV = { 1560, 1},
.VMINNMV = { 1561, 1},
.VMINNMAV = { 1562, 1},
.VABAV = { 1563, 1},
.VMLADAV = { 1564, 1},
.VMLADAVA = { 1565, 1},
.VMLADAVX = { 1566, 1},
.VMLADAVAX = { 1567, 1},
.VMLALDAV = { 1568, 1},
.VMLALDAVA = { 1569, 1},
.VMLALDAVX = { 1570, 1},
.VMLALDAVAX = { 1571, 1},
.VMLSDAV = { 1572, 1},
.VMLSDAVA = { 1573, 1},
.VMLSDAVX = { 1574, 1},
.VMLSDAVAX = { 1575, 1},
.VMLSLDAV = { 1576, 1},
.VMLSLDAVA = { 1577, 1},
.VMLSLDAVX = { 1578, 1},
.VMLSLDAVAX = { 1579, 1},
.VRMLALDAVH = { 1580, 1},
.VRMLALDAVHA = { 1581, 1},
.VRMLALDAVHX = { 1582, 1},
.VRMLALDAVHAX = { 1583, 1},
.VRMLSLDAVH = { 1584, 1},
.VRMLSLDAVHA = { 1585, 1},
.VRMLSLDAVHX = { 1586, 1},
.VRMLSLDAVHAX = { 1587, 1},
.VMLAV = { 1588, 1},
.VMLAVA = { 1589, 1},
.VMLSV = { 1590, 1},
.VMLSVA = { 1591, 1},
.VCMUL = { 1592, 1},
.VHCADD = { 1593, 2},
.VBRSR = { 1595, 1},
.VSHLC = { 1596, 1},
.VDDUP = { 1597, 1},
.VIDUP = { 1598, 1},
.VDWDUP = { 1599, 1},
.VIWDUP = { 1600, 1},
.VMOVNB = { 1601, 1},
.VMOVNT = { 1602, 1},
.VQMOVNB = { 1603, 1},
.VQMOVNT = { 1604, 1},
.VQMOVUNB = { 1605, 1},
.VQMOVUNT = { 1606, 1},
.VSHLLB = { 1607, 1},
.VSHLLT = { 1608, 1},
.VMULLB = { 1609, 1},
.VMULLT = { 1610, 1},
.VMLALB = { 1611, 1},
.VMLALT = { 1612, 1},
.VMLSLB = { 1613, 1},
.VMLSLT = { 1614, 1},
.VSHRNB = { 1615, 1},
.VSHRNT = { 1616, 1},
.VRSHRNB = { 1617, 1},
.VRSHRNT = { 1618, 1},
.VQSHRNB = { 1619, 1},
.VQSHRNT = { 1620, 1},
.VQRSHRNB = { 1621, 1},
.VQRSHRNT = { 1622, 1},
.VQSHRUNB = { 1623, 1},
.VQSHRUNT = { 1624, 1},
.VQRSHRUNB = { 1625, 1},
.VQRSHRUNT = { 1626, 1},
.VQDMLADH = { 1627, 1},
.VQDMLADHX = { 1628, 1},
.VQDMLSDH = { 1629, 1},
.VQDMLSDHX = { 1630, 1},
.VQRDMLADH = { 1631, 1},
.VQRDMLADHX = { 1632, 1},
.VQRDMLSDH = { 1633, 1},
.VQRDMLSDHX = { 1634, 1},
.VLDRB = { 1635, 2},
.VLDRH = { 1637, 2},
.VLDRW = { 1639, 2},
.VLDRD = { 1641, 2},
.VSTRB = { 1643, 2},
.VSTRH = { 1645, 2},
.VSTRW = { 1647, 2},
.VSTRD = { 1649, 2},
.VLD20 = { 1651, 1},
.VLD21 = { 1652, 1},
.VLD40 = { 1653, 1},
.VLD41 = { 1654, 1},
.VLD42 = { 1655, 1},
.VLD43 = { 1656, 1},
.VST20 = { 1657, 1},
.VST21 = { 1658, 1},
.VST40 = { 1659, 1},
.VST41 = { 1660, 1},
.VST42 = { 1661, 1},
.VST43 = { 1662, 1},
._COUNT = { 1663, 0},
}

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15
core/rexcode/isa/arm32/tests/smoke.odin
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@@ -530,11 +530,16 @@ run_smoke :: proc() {
check("VSTRB", .VSTRB, 1, 0xEC600E00, 0xFEF00FD1)
// ---- VFP fixed-point conversions (VCVT with #fbits) ----
check("VCVT S32.F32", .VCVT, 11, 0x0EBE0A40, 0x0FBF0FD0)
check("VCVT U32.F32", .VCVT, 12, 0x0EBF0A40, 0x0FBF0FD0)
check("VCVT F32.S32", .VCVT, 13, 0x0EBA0A40, 0x0FBF0FD0)
check("VCVT F64", .VCVT, 17, 0x0EBE0B40, 0x0FBF0FD0)
check("VCVT F16", .VCVT, 19, 0x0EBE0940, 0x0FBF0FD0)
// The matrix runs cp (F16, F32, F64) outermost, then sx (16- then 32-bit
// fixed point), then opc2 (F<-S, F<-U, S<-F, U<-F).
check("VCVT F16.S16", .VCVT, 11, 0x0EBA0940, 0x0FBF0FD0)
check("VCVT S32.F16", .VCVT, 17, 0x0EBE09C0, 0x0FBF0FD0)
check("VCVT F32.S16", .VCVT, 19, 0x0EBA0A40, 0x0FBF0FD0)
check("VCVT S16.F32", .VCVT, 21, 0x0EBE0A40, 0x0FBF0FD0)
check("VCVT F32.S32", .VCVT, 23, 0x0EBA0AC0, 0x0FBF0FD0)
check("VCVT S32.F32", .VCVT, 25, 0x0EBE0AC0, 0x0FBF0FD0)
check("VCVT F64.S16", .VCVT, 27, 0x0EBA0B40, 0x0FBF0FD0)
check("VCVT S32.F64", .VCVT, 33, 0x0EBE0BC0, 0x0FBF0FD0)
// ---- NEON compare-with-zero ----
check("VCEQ D .I8", .VCEQ, 10, 0xF3B10100, 0xFFBB0FD0)