mirror of
https://github.com/odin-lang/Odin.git
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feat(arm32 cdecl): Added thumb as the triple for cortex-m7. Updated the calling convention for cortex-m7 arm32 micro processors as the soft float register was being used when calling across the C ABI boundary causing guff data to be passed.
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@@ -1072,6 +1072,12 @@ gb_internal bool is_arch_wasm(void) {
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return false;
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}
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gb_internal bool is_cortex_m7(void) {
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return build_context.metrics.os == TargetOs_freestanding &&
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build_context.metrics.arch == TargetArch_arm32 &&
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build_context.microarch == str_lit("cortex-m7");
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}
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gb_internal bool is_arch_x86(void) {
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switch (build_context.metrics.arch) {
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case TargetArch_i386:
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@@ -1832,9 +1838,7 @@ gb_internal void init_build_context(TargetMetrics *cross_target, Subtarget subta
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bc->metrics = *metrics;
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if (bc->metrics.os == TargetOs_freestanding &&
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bc->metrics.arch == TargetArch_arm32 &&
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bc->microarch == str_lit("cortex-m7")) {
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if (is_cortex_m7()) {
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bc->metrics.target_triplet = str_lit("thumbv7em-none-eabihf");
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}
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@@ -186,9 +186,11 @@ gb_internal void lb_add_function_type_attributes(LLVMValueRef fn, lbFunctionType
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lbCallingConventionKind cc_kind = lbCallingConvention_C;
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// TODO(bill): Clean up this logic
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if (!is_arch_wasm()) {
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if (is_cortex_m7()) {
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cc_kind = lbCallingConvention_ARM_AAPCS_VFP;
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} else if (!is_arch_wasm()) {
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cc_kind = lb_calling_convention_map[calling_convention];
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}
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}
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// if (build_context.metrics.arch == TargetArch_amd64) {
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// if (build_context.metrics.os == TargetOs_windows) {
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// if (cc_kind == lbCallingConvention_C) {
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@@ -1554,14 +1556,14 @@ namespace lbAbiWasm {
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namespace lbAbiArm32 {
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gb_internal Array<lbArgType> compute_arg_types(LLVMContextRef c, LLVMTypeRef *arg_types, unsigned arg_count, ProcCallingConvention calling_convention);
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gb_internal lbArgType compute_return_type(LLVMContextRef c, LLVMTypeRef return_type, bool return_is_defined);
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gb_internal lbArgType compute_return_type(LLVMContextRef c, LLVMTypeRef return_type, bool return_is_defined, ProcCallingConvention calling_convention);
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gb_internal LB_ABI_INFO(abi_info) {
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LLVMContextRef c = m->ctx;
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lbFunctionType *ft = permanent_alloc_item<lbFunctionType>();
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ft->ctx = c;
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ft->args = compute_arg_types(c, arg_types, arg_count, calling_convention);
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ft->ret = compute_return_type(c, return_type, return_is_defined);
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ft->ret = compute_return_type(c, return_type, return_is_defined, calling_convention);
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ft->calling_convention = calling_convention;
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return ft;
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}
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@@ -1604,7 +1606,10 @@ namespace lbAbiArm32 {
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} else {
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i64 sz = lb_sizeof(t);
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i64 a = lb_alignof(t);
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if (is_calling_convention_odin(calling_convention) && sz > 8) {
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// Added to support hard floats included in the playdates cortex-m7.
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if (calling_convention == ProcCC_CDecl && is_cortex_m7()) {
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args[i] = lb_arg_type_direct(t);
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} else if (is_calling_convention_odin(calling_convention) && sz > 8) {
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// Minor change to improve performance using the Odin calling conventions
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args[i] = lb_arg_type_indirect(t, nullptr);
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} else if (a <= 4) {
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@@ -1619,10 +1624,13 @@ namespace lbAbiArm32 {
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return args;
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}
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gb_internal lbArgType compute_return_type(LLVMContextRef c, LLVMTypeRef return_type, bool return_is_defined) {
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gb_internal lbArgType compute_return_type(LLVMContextRef c, LLVMTypeRef return_type, bool return_is_defined, ProcCallingConvention calling_convention) {
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if (!return_is_defined) {
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return lb_arg_type_direct(LLVMVoidTypeInContext(c));
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} else if (!is_register(return_type, true)) {
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if (calling_convention == ProcCC_CDecl && is_cortex_m7()) {
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return lb_arg_type_direct(return_type);
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}
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switch (lb_sizeof(return_type)) {
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case 1: return lb_arg_type_direct(LLVMIntTypeInContext(c, 8), return_type, nullptr, nullptr);
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case 2: return lb_arg_type_direct(LLVMIntTypeInContext(c, 16), return_type, nullptr, nullptr);
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@@ -452,7 +452,9 @@ gb_internal lbProcedure *lb_create_dummy_procedure(lbModule *m, String link_name
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Type *pt = p->type;
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lbCallingConventionKind cc_kind = lbCallingConvention_C;
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if (!is_arch_wasm()) {
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if (is_cortex_m7()) {
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cc_kind = lbCallingConvention_ARM_AAPCS_VFP;
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} else if (!is_arch_wasm()) {
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cc_kind = lb_calling_convention_map[pt->Proc.calling_convention];
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}
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LLVMSetFunctionCallConv(p->value, cc_kind);
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@@ -994,6 +996,9 @@ gb_internal lbValue lb_emit_call_internal(lbProcedure *p, lbValue value, lbValue
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LLVMValueRef ret = LLVMBuildCall2(p->builder, fnp, fn, args, arg_count, "");
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auto llvm_cc = lb_calling_convention_map[proc_type->Proc.calling_convention];
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if (is_cortex_m7()) {
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llvm_cc = lbCallingConvention_ARM_AAPCS_VFP;
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}
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LLVMSetInstructionCallConv(ret, llvm_cc);
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LLVMAttributeIndex param_offset = LLVMAttributeIndex_FirstArgIndex;
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