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default NATIVE_SIMD_BIT_WIDTH to 128
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@@ -17,20 +17,18 @@ RUNTIME_REQUIRE :: false // !ODIN_TILDE
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@(private)
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__float16 :: f16 when __ODIN_LLVM_F16_SUPPORTED else u16
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HAS_HARDWARE_SIMD :: NATIVE_SIMD_BIT_WIDTH != 0
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HAS_HARDWARE_SIMD :: false when (ODIN_ARCH == .amd64 || ODIN_ARCH == .i386) && !intrinsics.has_target_feature("sse2") else
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false when (ODIN_ARCH == .arm64 || ODIN_ARCH == .arm32) && !intrinsics.has_target_feature("neon") else
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false when (ODIN_ARCH == .wasm64p32 || ODIN_ARCH == .wasm32) && !intrinsics.has_target_feature("simd128") else
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false when (ODIN_ARCH == .riscv64) && !intrinsics.has_target_feature("v") else
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true
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// Number of bits in the largest native SIMD register.
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// 0 when target doesn't support hardware SIMD.
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// Size of a native SIMD register for the current compilation target
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NATIVE_SIMD_BIT_WIDTH ::
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512 when (ODIN_ARCH == .amd64) && intrinsics.has_target_feature("avx512f") else
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256 when (ODIN_ARCH == .amd64) && (intrinsics.has_target_feature("avx2") || intrinsics.has_target_feature("avx")) else
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128 when (ODIN_ARCH == .amd64 || ODIN_ARCH == .i386) && intrinsics.has_target_feature("sse") else
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// ARM: SVE can be larger, but NEON is always 128
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128 when (ODIN_ARCH == .arm64 || ODIN_ARCH == .arm32) && intrinsics.has_target_feature("neon") else
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// VLEN can be between 32 and thousands of bits. 128 is a safe bet.
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128 when (ODIN_ARCH == .riscv64) && intrinsics.has_target_feature("v") else
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128 when (ODIN_ARCH == .wasm64p32 || ODIN_ARCH == .wasm32) && intrinsics.has_target_feature("simd128") else
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0
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// Fallback for no hardware SIMD, but also SSE, NEON, SVE, RVV and WASM SIMD128.
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128
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@(private)
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byte_slice :: #force_inline proc "contextless" (data: rawptr, len: int) -> []byte #no_bounds_check {
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