Add new SVE mnemonics and IMM_MUL4 operand and encoding type

core/rexcode/isa/arm64/encoder.odin

@@ -277,7 +277,8 @@ operand_matches_inline :: #force_inline proc "contextless" (
 		return op.kind == .IMMEDIATE
 
 	case .IMM_12, .IMM_16, .IMM_8, .IMM_6, .IMM_5, .IMM_4, .IMM_3, .IMM_2,
-		 .NZCV_IMM, .PSTATE_FIELD, .HW_SHIFT, .LSE_SIZE, .VEC_SHIFT, .VEC_INDEX:
+	     .NZCV_IMM, .PSTATE_FIELD, .HW_SHIFT, .LSE_SIZE, .VEC_SHIFT, .VEC_INDEX,
+	     .IMM_MUL4:
 		return op.kind == .IMMEDIATE
 	case .SYS_REG:
 		return op.kind == .SYSTEM_REGISTER
@@ -664,6 +665,16 @@ pack_operand_inline :: #force_inline proc(
 	case .SVE_PATTERN:
 		return (u32(op.immediate) & 0x1F) << 5
 
+	case .IMM_MUL4:
+		// SVE element-count multiplier "MUL #imm" (INCW/DECW/CNTW/SQINCW/...).
+		// imm4 field at bits 19:16 encodes (imm - 1); asm range MUL #1..#16
+		// maps to 0..15. The operand carries the architectural multiplier
+		// (1..16), so subtract one here, matching the ENC_LSL_IMM_* /
+		// NEON_SHR_IMM convention of encoding the adjusted value.
+		mul := u32(op.immediate)
+		if mul == 0 { mul = 1 }
+		return ((mul - 1) & 0xF) << 16
+
 	// SVE memory operands
 	case .SVE_OFFSET_BASE_SS:
 		// [Xn, Xm, LSL #s] scalar+scalar. Base at 9:5, index at 20:16;

core/rexcode/isa/arm64/encoding_types.odin

@@ -156,6 +156,7 @@ Operand_Type :: enum u8 {
 	HW_SHIFT,      // 2-bit LSL hw (0/16/32/48) for MOV-immediate
 	BITMASK_IMM,   // Logical immediate (bitmask-encoded N:imms:immr)
 	LSE_SIZE,      // 2-bit size selector for LSE atomics (00=B 01=H 10=W 11=X)
+	IMM_MUL4,
 
 	// ---- PC-relative ----
 	REL_26,        // B / BL (signed 26-bit << 2)
@@ -349,6 +350,7 @@ Operand_Encoding :: enum u8 {
 	SVE_IMM5,             // 5-bit at bits 20-16 (INDEX imm, etc.)
 	SVE_SHIFT_TSZ_IMM,    // tsz:imm3 at bits 22:16, encodes element-size + shift amount
 	SVE_PATTERN,          // 5-bit pattern (POW2/VL1.../ALL) at bits 9-5 (PTRUE)
+	IMM_MUL4,
 
 	// ---- SVE memory operands ---------------------------------------------
 	SVE_OFFSET_BASE_SS,   // [Xn, Xm, LSL #s] -- scalar+scalar contiguous

core/rexcode/isa/arm64/mnemonics.odin

@@ -392,6 +392,14 @@ Mnemonic :: enum u16 {
 	BFMOPA, BFMOPS,
 	SMOPA, SMOPS, UMOPA, UMOPS,
 	USMOPA, SUMOPA,
+	CNTB, CNTH, CNTW, CNTD,
+	INCB, INCH, INCW, INCD,
+	DECB, DECH, DECW, DECD,
+	SQINCB, SQINCH, SQINCW, SQINCD, SQDECB, SQDECH, SQDECW, SQDECD,
+	UQINCB, UQINCH, UQINCW, UQINCD, UQDECB, UQDECH, UQDECW, UQDECD,
+	CNTP, INCP, DECP,
+	SQINCP, SQDECP,
+	UQINCP, UQDECP,
 
 	// -------------------------------------------------------------------------
 	// SME tile slice load/store (LD1B/H/W/D/Q to ZA tile slice; ST1 reverse)