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rexcode/arm32: VFMA/VFMS carried VMLA/VMLS encodings; drop three duplicate mnemonics

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Asking for a VFMA with a lane operand emitted a VMLA. NEON's fused multiply-add
has no by-element form at all -- llvm-mc rejects `vfma.f32 d0, d1, d2[0]` -- and
the four rows sitting under VFMA/VFMS held VMLA/VMLS's lane encodings, which
VMLA and VMLS already own. Their data type gave it away too: `.I32` on a
fused multiply-add, which is float-only. Deleted.

They were also the reason `bits & ~mask` looked wrong on those rows: as
authored they were F2A000C0, and clearing the Vn high bit -- correct, since
bit 7 is the top of the register number -- landed them exactly on VMLA's
F2A00040.

Found by asking which (bits, mask, mode) triples more than one mnemonic
claims. That check found 18; this commit takes it to 9.

Three of the eighteen were whole mnemonics duplicating a base:

  VRECPE_F, VRSQRTE_F   every form already present under VRECPE / VRSQRTE,
                        which carry both the U32 and F32 variants.
  VPADD_F               its F32 form duplicated VPADD's; its F16 form was the
                        only thing it owned, so that moves to VPADD, where the
                        data type now selects it.

All three were on the list of names no assembler spells, so that count goes
from 14 to 11 -- and nine of the remaining eleven are the *_LANE group, still
waiting on register-list and lane-index modelling. The other two are
`psb csync` and `tsb csync`, which are correct as they are.

Two smoke checks asserted the VFMA/VFMS by-element forms and are gone with
them; a third moved index.

Verified against llvm-mc: vpadd.i8/.f32/.f16, vrecpe.u32/.f32 and vrsqrte.f32
all byte-exact, 1656/1656 decode sweep, every suite at baseline.

Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
This commit is contained in:
Brendan Punsky
2026-08-27 08:42:04 -04:00
committed by Flāvius
parent a2cd94f406
commit d951ee9963
15 changed files with 1460 additions and 1519 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
core/rexcode/isa/arm32/mnemonic_builders.odin
View File

@@ -693,13 +693,9 @@ emit_vnmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruc
inst_vnmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vnmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmls_s_s_s(dst, src, src2)) }
inst_vfma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
inst_vfma_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
emit_vfma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_s_s_s(dst, src, src2)) }
emit_vfma_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfma_d_d_dlane(dst, src, src2, lane)) }
inst_vfms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
inst_vfms_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
emit_vfms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfms_s_s_s(dst, src, src2)) }
emit_vfms_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfms_d_d_dlane(dst, src, src2, lane)) }
inst_vfnma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vfnma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnma_s_s_s(dst, src, src2)) }
inst_vfnms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
@@ -976,12 +972,6 @@ inst_vclz_d_d :: #force_inline proc "contextless" (dst: Register, s
emit_vclz_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclz_d_d(dst, src)) }
inst_vcnt_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCNT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
emit_vcnt_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcnt_d_d(dst, src)) }
inst_vpadd_f_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD_F, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vpadd_f_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_f_d_d_d(dst, src, src2)) }
inst_vrecpe_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
emit_vrecpe_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_f_d_d(dst, src)) }
inst_vrsqrte_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
emit_vrsqrte_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_f_d_d(dst, src)) }
inst_vrev16_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
emit_vrev16_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev16_d_d(dst, src)) }
inst_vrev32_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV32, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
@@ -1985,10 +1975,10 @@ inst_vnmla :: inst_vnmla_s_s_s
emit_vnmla :: emit_vnmla_s_s_s
inst_vnmls :: inst_vnmls_s_s_s
emit_vnmls :: emit_vnmls_s_s_s
inst_vfma :: proc{ inst_vfma_s_s_s, inst_vfma_d_d_dlane }
emit_vfma :: proc{ emit_vfma_s_s_s, emit_vfma_d_d_dlane }
inst_vfms :: proc{ inst_vfms_s_s_s, inst_vfms_d_d_dlane }
emit_vfms :: proc{ emit_vfms_s_s_s, emit_vfms_d_d_dlane }
inst_vfma :: inst_vfma_s_s_s
emit_vfma :: emit_vfma_s_s_s
inst_vfms :: inst_vfms_s_s_s
emit_vfms :: emit_vfms_s_s_s
inst_vfnma :: inst_vfnma_s_s_s
emit_vfnma :: emit_vfnma_s_s_s
inst_vfnms :: inst_vfnms_s_s_s
@@ -2211,12 +2201,6 @@ inst_vclz :: inst_vclz_d_d
emit_vclz :: emit_vclz_d_d
inst_vcnt :: inst_vcnt_d_d
emit_vcnt :: emit_vcnt_d_d
inst_vpadd_f :: inst_vpadd_f_d_d_d
emit_vpadd_f :: emit_vpadd_f_d_d_d
inst_vrecpe_f :: inst_vrecpe_f_d_d
emit_vrecpe_f :: emit_vrecpe_f_d_d
inst_vrsqrte_f :: inst_vrsqrte_f_d_d
emit_vrsqrte_f :: emit_vrsqrte_f_d_d
inst_vrev16 :: inst_vrev16_d_d
emit_vrev16 :: emit_vrev16_d_d
inst_vrev32 :: inst_vrev32_d_d

2
core/rexcode/isa/arm32/mnemonics.odin
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@@ -290,7 +290,7 @@ Mnemonic :: enum u16 {
VSHLL, // shift-left long
VCLS, VCLZ, VCNT,
VPADD_F, VRECPE_F, VRSQRTE_F, // (placeholders; canonical via operand types)
// (placeholders; canonical via operand types)
VREV16, VREV32, VREV64,
VEXT, // vector extract

17
core/rexcode/isa/arm32/tablegen/encoding_table.odin
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@@ -1376,8 +1376,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// MVE FP vector + scalar
{.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
{.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
{.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}},
},
.VFMS = {
@@ -1390,8 +1388,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
// MVE FP vector
{.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}},
{.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}},
},
.VFNMS = {
{.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}},
@@ -2005,6 +2001,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
// F32
{.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
// (VPADD MVE form doesn't exist; MVE uses VADDV reduction instead)
{.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}},
},
// ---- VPMAX / VPMIN (D-form only) ----
.VPMAX = {
@@ -3556,18 +3553,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VRSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
{.VRSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}},
},
.VRECPE_F = {
{.VRECPE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
{.VRECPE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
},
.VRSQRTE_F = {
{.VRSQRTE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
{.VRSQRTE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
},
.VPADD_F = {
{.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}},
{.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}},
},
.VCVTR = {
{.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F32}},
{.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F32}},

2257
core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin
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File diff suppressed because it is too large Load Diff

675
core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin
View File

@@ -8,7 +8,7 @@ package rexcode_arm32_generated
import lib "../.."
@(rodata)
ENCODE_FORMS := [1665]lib.Encoding{
ENCODE_FORMS := [1656]lib.Encoding{
// .AND
{ .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} },
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} },
@@ -993,8 +993,6 @@ ENCODE_FORMS := [1665]lib.Encoding{
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
{ .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
{ .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} },
// .VFMS
{ .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} },
@@ -1003,8 +1001,6 @@ ENCODE_FORMS := [1665]lib.Encoding{
{ .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} },
{ .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} },
{ .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
{ .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} },
// .VFNMA
{ .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} },
{ .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} },
@@ -1603,6 +1599,7 @@ ENCODE_FORMS := [1665]lib.Encoding{
{ .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} },
{ .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} },
{ .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
// .VPADDL
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} },
{ .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} },
@@ -1727,15 +1724,6 @@ ENCODE_FORMS := [1665]lib.Encoding{
// .VCNT
{ .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
// .VPADD_F
{ .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} },
{ .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} },
// .VRECPE_F
{ .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
// .VRSQRTE_F
{ .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
{ .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} },
// .VREV16
{ .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
{ .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} },
@@ -2540,335 +2528,332 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
.VNMUL = { 704, 2},
.VNMLA = { 706, 2},
.VNMLS = { 708, 2},
.VFMA = { 710, 10},
.VFMS = { 720, 8},
.VFNMA = { 728, 3},
.VFNMS = { 731, 3},
.VABS = { 734, 12},
.VNEG = { 746, 12},
.VSQRT = { 758, 3},
.VCMP = { 761, 8},
.VCMPE = { 769, 4},
.VCVT = { 773, 21},
.VCVTB = { 794, 2},
.VCVTT = { 796, 2},
.VCVTA = { 798, 2},
.VCVTN = { 800, 2},
.VCVTP = { 802, 2},
.VCVTM = { 804, 2},
.VCVTR = { 806, 4},
.VMOV = { 810, 31},
.VMRS = { 841, 1},
.VMSR = { 842, 1},
.VLDR = { 843, 2},
.VSTR = { 845, 2},
.VLDM = { 847, 2},
.VSTM = { 849, 2},
.VPUSH = { 851, 2},
.VPOP = { 853, 2},
.VSEL = { 855, 2},
.VMAXNM = { 857, 2},
.VMINNM = { 859, 2},
.VRINTA = { 861, 3},
.VRINTN = { 864, 3},
.VRINTP = { 867, 3},
.VRINTM = { 870, 3},
.VRINTR = { 873, 2},
.VRINTZ = { 875, 3},
.VRINTX = { 878, 3},
.VADDL = { 881, 6},
.VADDW = { 887, 6},
.VSUBL = { 893, 6},
.VSUBW = { 899, 6},
.VHADD = { 905, 9},
.VHSUB = { 914, 9},
.VRHADD = { 923, 3},
.VQADD = { 926, 11},
.VQSUB = { 937, 11},
.VMULL = { 948, 11},
.VMLAL = { 959, 10},
.VMLSL = { 969, 10},
.VQDMULL = { 979, 4},
.VQDMLAL = { 983, 4},
.VQDMLSL = { 987, 4},
.VQDMULH = { 991, 8},
.VQRDMULH = { 999, 8},
.VQRDMLAH = { 1007, 8},
.VQRDMLSH = { 1015, 8},
.VABA = { 1023, 8},
.VABAL = { 1031, 6},
.VABD = { 1037, 10},
.VABDL = { 1047, 6},
.VAND = { 1053, 3},
.VBIC = { 1056, 3},
.VORR = { 1059, 3},
.VORN = { 1062, 3},
.VEOR = { 1065, 3},
.VBSL = { 1068, 2},
.VBIT = { 1070, 2},
.VBIF = { 1072, 2},
.VMVN = { 1074, 13},
.VMOVN = { 1087, 3},
.VQMOVN = { 1090, 6},
.VQMOVUN = { 1096, 3},
.VMOVL = { 1099, 6},
.VTST = { 1105, 6},
.VCEQ = { 1111, 14},
.VCGE = { 1125, 16},
.VCGT = { 1141, 16},
.VCLE = { 1157, 18},
.VCLT = { 1175, 18},
.VACGE = { 1193, 2},
.VACGT = { 1195, 2},
.VACLE = { 1197, 2},
.VACLT = { 1199, 2},
.VMAX = { 1201, 13},
.VMIN = { 1214, 13},
.VPMAX = { 1227, 5},
.VPMIN = { 1232, 5},
.VPADD = { 1237, 4},
.VPADDL = { 1241, 6},
.VPADAL = { 1247, 4},
.VRECPE = { 1251, 4},
.VRECPS = { 1255, 2},
.VRSQRTE = { 1257, 4},
.VRSQRTS = { 1261, 2},
.VSHL = { 1263, 9},
.VSHR = { 1272, 3},
.VSRA = { 1275, 3},
.VRSHL = { 1278, 5},
.VRSHR = { 1283, 3},
.VRSRA = { 1286, 2},
.VSLI = { 1288, 2},
.VSRI = { 1290, 2},
.VQSHL = { 1292, 7},
.VQSHRN = { 1299, 1},
.VQSHRUN = { 1300, 1},
.VQRSHL = { 1301, 16},
.VQRSHRN = { 1317, 1},
.VQRSHRUN = { 1318, 1},
.VSHRN = { 1319, 1},
.VRSHRN = { 1320, 1},
.VSHLL = { 1321, 4},
.VCLS = { 1325, 6},
.VCLZ = { 1331, 6},
.VCNT = { 1337, 2},
.VPADD_F = { 1339, 2},
.VRECPE_F = { 1341, 2},
.VRSQRTE_F = { 1343, 2},
.VREV16 = { 1345, 2},
.VREV32 = { 1347, 4},
.VREV64 = { 1351, 6},
.VEXT = { 1357, 2},
.VTBL = { 1359, 4},
.VTBX = { 1363, 4},
.VTRN = { 1367, 6},
.VUZP = { 1373, 5},
.VZIP = { 1378, 5},
.VDUP = { 1383, 5},
.VSWP = { 1388, 2},
.VMOV_LANE = { 1390, 3},
.VLD1 = { 1393, 8},
.VLD2 = { 1401, 3},
.VLD3 = { 1404, 2},
.VLD4 = { 1406, 2},
.VST1 = { 1408, 7},
.VST2 = { 1415, 3},
.VST3 = { 1418, 2},
.VST4 = { 1420, 2},
.AESE = { 1422, 1},
.AESD = { 1423, 1},
.AESMC = { 1424, 1},
.AESIMC = { 1425, 1},
.SHA1H = { 1426, 1},
.SHA1SU0 = { 1427, 1},
.SHA1SU1 = { 1428, 1},
.SHA1C = { 1429, 1},
.SHA1M = { 1430, 1},
.SHA1P = { 1431, 1},
.SHA256H = { 1432, 1},
.SHA256H2 = { 1433, 1},
.SHA256SU0 = { 1434, 1},
.SHA256SU1 = { 1435, 1},
.VJCVT = { 1436, 1},
.VSDOT = { 1437, 4},
.VUDOT = { 1441, 4},
.VDOT = { 1445, 2},
.VMMLA = { 1447, 1},
.VFMAL = { 1448, 2},
.VFMSL = { 1450, 2},
.VCMLA = { 1452, 5},
.VCADD = { 1457, 2},
.VSMMLA = { 1459, 1},
.VUMMLA = { 1460, 1},
.VUSMMLA = { 1461, 1},
.VSUDOT = { 1462, 2},
.VUSDOT = { 1464, 4},
.VQABS = { 1468, 1},
.VQNEG = { 1469, 1},
.VMOVX = { 1470, 1},
.VINS = { 1471, 1},
.VLD2R = { 1472, 1},
.VLD3R = { 1473, 1},
.VLD4R = { 1474, 1},
.VLD1_LANE = { 1475, 3},
.VLD2_LANE = { 1478, 3},
.VLD3_LANE = { 1481, 3},
.VLD4_LANE = { 1484, 3},
.VST1_LANE = { 1487, 3},
.VST2_LANE = { 1490, 3},
.VST3_LANE = { 1493, 3},
.VST4_LANE = { 1496, 3},
.IT = { 1499, 1},
.TT = { 1500, 1},
.TTT = { 1501, 1},
.TTA = { 1502, 1},
.TTAT = { 1503, 1},
.SG = { 1504, 1},
.BXNS = { 1505, 1},
.BLXNS = { 1506, 1},
.PAC = { 1507, 1},
.PACBTI = { 1508, 1},
.AUT = { 1509, 1},
.AUTG = { 1510, 1},
.BTI = { 1511, 1},
.WLS = { 1512, 1},
.WLSTP = { 1513, 1},
.DLS = { 1514, 1},
.DLSTP = { 1515, 1},
.LE = { 1516, 1},
.LETP = { 1517, 1},
.LCTP = { 1518, 1},
.BF = { 1519, 1},
.BFX = { 1520, 1},
.BFL = { 1521, 1},
.BFLX = { 1522, 1},
.BFCSEL = { 1523, 1},
.CX1 = { 1524, 1},
.CX1A = { 1525, 1},
.CX1D = { 1526, 1},
.CX1DA = { 1527, 1},
.CX2 = { 1528, 1},
.CX2A = { 1529, 1},
.CX2D = { 1530, 1},
.CX2DA = { 1531, 1},
.CX3 = { 1532, 1},
.CX3A = { 1533, 1},
.CX3D = { 1534, 1},
.CX3DA = { 1535, 1},
.VCX1 = { 1536, 2},
.VCX1A = { 1538, 2},
.VCX2 = { 1540, 2},
.VCX2A = { 1542, 2},
.VCX3 = { 1544, 2},
.VCX3A = { 1546, 2},
.VPT = { 1548, 1},
.VPST = { 1549, 1},
.VPSEL = { 1550, 1},
.VPNOT = { 1551, 1},
.VCTP = { 1552, 1},
.VADDV = { 1553, 1},
.VADDVA = { 1554, 1},
.VADDLV = { 1555, 1},
.VADDLVA = { 1556, 1},
.VMAXV = { 1557, 1},
.VMAXAV = { 1558, 1},
.VMINV = { 1559, 1},
.VMINAV = { 1560, 1},
.VMAXNMV = { 1561, 1},
.VMAXNMAV = { 1562, 1},
.VMINNMV = { 1563, 1},
.VMINNMAV = { 1564, 1},
.VABAV = { 1565, 1},
.VMLADAV = { 1566, 1},
.VMLADAVA = { 1567, 1},
.VMLADAVX = { 1568, 1},
.VMLADAVAX = { 1569, 1},
.VMLALDAV = { 1570, 1},
.VMLALDAVA = { 1571, 1},
.VMLALDAVX = { 1572, 1},
.VMLALDAVAX = { 1573, 1},
.VMLSDAV = { 1574, 1},
.VMLSDAVA = { 1575, 1},
.VMLSDAVX = { 1576, 1},
.VMLSDAVAX = { 1577, 1},
.VMLSLDAV = { 1578, 1},
.VMLSLDAVA = { 1579, 1},
.VMLSLDAVX = { 1580, 1},
.VMLSLDAVAX = { 1581, 1},
.VRMLALDAVH = { 1582, 1},
.VRMLALDAVHA = { 1583, 1},
.VRMLALDAVHX = { 1584, 1},
.VRMLALDAVHAX = { 1585, 1},
.VRMLSLDAVH = { 1586, 1},
.VRMLSLDAVHA = { 1587, 1},
.VRMLSLDAVHX = { 1588, 1},
.VRMLSLDAVHAX = { 1589, 1},
.VMLAV = { 1590, 1},
.VMLAVA = { 1591, 1},
.VMLSV = { 1592, 1},
.VMLSVA = { 1593, 1},
.VCMUL = { 1594, 1},
.VHCADD = { 1595, 2},
.VBRSR = { 1597, 1},
.VSHLC = { 1598, 1},
.VDDUP = { 1599, 1},
.VIDUP = { 1600, 1},
.VDWDUP = { 1601, 1},
.VIWDUP = { 1602, 1},
.VMOVNB = { 1603, 1},
.VMOVNT = { 1604, 1},
.VQMOVNB = { 1605, 1},
.VQMOVNT = { 1606, 1},
.VQMOVUNB = { 1607, 1},
.VQMOVUNT = { 1608, 1},
.VSHLLB = { 1609, 1},
.VSHLLT = { 1610, 1},
.VMULLB = { 1611, 1},
.VMULLT = { 1612, 1},
.VMLALB = { 1613, 1},
.VMLALT = { 1614, 1},
.VMLSLB = { 1615, 1},
.VMLSLT = { 1616, 1},
.VSHRNB = { 1617, 1},
.VSHRNT = { 1618, 1},
.VRSHRNB = { 1619, 1},
.VRSHRNT = { 1620, 1},
.VQSHRNB = { 1621, 1},
.VQSHRNT = { 1622, 1},
.VQRSHRNB = { 1623, 1},
.VQRSHRNT = { 1624, 1},
.VQSHRUNB = { 1625, 1},
.VQSHRUNT = { 1626, 1},
.VQRSHRUNB = { 1627, 1},
.VQRSHRUNT = { 1628, 1},
.VQDMLADH = { 1629, 1},
.VQDMLADHX = { 1630, 1},
.VQDMLSDH = { 1631, 1},
.VQDMLSDHX = { 1632, 1},
.VQRDMLADH = { 1633, 1},
.VQRDMLADHX = { 1634, 1},
.VQRDMLSDH = { 1635, 1},
.VQRDMLSDHX = { 1636, 1},
.VLDRB = { 1637, 2},
.VLDRH = { 1639, 2},
.VLDRW = { 1641, 2},
.VLDRD = { 1643, 2},
.VSTRB = { 1645, 2},
.VSTRH = { 1647, 2},
.VSTRW = { 1649, 2},
.VSTRD = { 1651, 2},
.VLD20 = { 1653, 1},
.VLD21 = { 1654, 1},
.VLD40 = { 1655, 1},
.VLD41 = { 1656, 1},
.VLD42 = { 1657, 1},
.VLD43 = { 1658, 1},
.VST20 = { 1659, 1},
.VST21 = { 1660, 1},
.VST40 = { 1661, 1},
.VST41 = { 1662, 1},
.VST42 = { 1663, 1},
.VST43 = { 1664, 1},
._COUNT = { 1665, 0},
.VFMA = { 710, 8},
.VFMS = { 718, 6},
.VFNMA = { 724, 3},
.VFNMS = { 727, 3},
.VABS = { 730, 12},
.VNEG = { 742, 12},
.VSQRT = { 754, 3},
.VCMP = { 757, 8},
.VCMPE = { 765, 4},
.VCVT = { 769, 21},
.VCVTB = { 790, 2},
.VCVTT = { 792, 2},
.VCVTA = { 794, 2},
.VCVTN = { 796, 2},
.VCVTP = { 798, 2},
.VCVTM = { 800, 2},
.VCVTR = { 802, 4},
.VMOV = { 806, 31},
.VMRS = { 837, 1},
.VMSR = { 838, 1},
.VLDR = { 839, 2},
.VSTR = { 841, 2},
.VLDM = { 843, 2},
.VSTM = { 845, 2},
.VPUSH = { 847, 2},
.VPOP = { 849, 2},
.VSEL = { 851, 2},
.VMAXNM = { 853, 2},
.VMINNM = { 855, 2},
.VRINTA = { 857, 3},
.VRINTN = { 860, 3},
.VRINTP = { 863, 3},
.VRINTM = { 866, 3},
.VRINTR = { 869, 2},
.VRINTZ = { 871, 3},
.VRINTX = { 874, 3},
.VADDL = { 877, 6},
.VADDW = { 883, 6},
.VSUBL = { 889, 6},
.VSUBW = { 895, 6},
.VHADD = { 901, 9},
.VHSUB = { 910, 9},
.VRHADD = { 919, 3},
.VQADD = { 922, 11},
.VQSUB = { 933, 11},
.VMULL = { 944, 11},
.VMLAL = { 955, 10},
.VMLSL = { 965, 10},
.VQDMULL = { 975, 4},
.VQDMLAL = { 979, 4},
.VQDMLSL = { 983, 4},
.VQDMULH = { 987, 8},
.VQRDMULH = { 995, 8},
.VQRDMLAH = { 1003, 8},
.VQRDMLSH = { 1011, 8},
.VABA = { 1019, 8},
.VABAL = { 1027, 6},
.VABD = { 1033, 10},
.VABDL = { 1043, 6},
.VAND = { 1049, 3},
.VBIC = { 1052, 3},
.VORR = { 1055, 3},
.VORN = { 1058, 3},
.VEOR = { 1061, 3},
.VBSL = { 1064, 2},
.VBIT = { 1066, 2},
.VBIF = { 1068, 2},
.VMVN = { 1070, 13},
.VMOVN = { 1083, 3},
.VQMOVN = { 1086, 6},
.VQMOVUN = { 1092, 3},
.VMOVL = { 1095, 6},
.VTST = { 1101, 6},
.VCEQ = { 1107, 14},
.VCGE = { 1121, 16},
.VCGT = { 1137, 16},
.VCLE = { 1153, 18},
.VCLT = { 1171, 18},
.VACGE = { 1189, 2},
.VACGT = { 1191, 2},
.VACLE = { 1193, 2},
.VACLT = { 1195, 2},
.VMAX = { 1197, 13},
.VMIN = { 1210, 13},
.VPMAX = { 1223, 5},
.VPMIN = { 1228, 5},
.VPADD = { 1233, 5},
.VPADDL = { 1238, 6},
.VPADAL = { 1244, 4},
.VRECPE = { 1248, 4},
.VRECPS = { 1252, 2},
.VRSQRTE = { 1254, 4},
.VRSQRTS = { 1258, 2},
.VSHL = { 1260, 9},
.VSHR = { 1269, 3},
.VSRA = { 1272, 3},
.VRSHL = { 1275, 5},
.VRSHR = { 1280, 3},
.VRSRA = { 1283, 2},
.VSLI = { 1285, 2},
.VSRI = { 1287, 2},
.VQSHL = { 1289, 7},
.VQSHRN = { 1296, 1},
.VQSHRUN = { 1297, 1},
.VQRSHL = { 1298, 16},
.VQRSHRN = { 1314, 1},
.VQRSHRUN = { 1315, 1},
.VSHRN = { 1316, 1},
.VRSHRN = { 1317, 1},
.VSHLL = { 1318, 4},
.VCLS = { 1322, 6},
.VCLZ = { 1328, 6},
.VCNT = { 1334, 2},
.VREV16 = { 1336, 2},
.VREV32 = { 1338, 4},
.VREV64 = { 1342, 6},
.VEXT = { 1348, 2},
.VTBL = { 1350, 4},
.VTBX = { 1354, 4},
.VTRN = { 1358, 6},
.VUZP = { 1364, 5},
.VZIP = { 1369, 5},
.VDUP = { 1374, 5},
.VSWP = { 1379, 2},
.VMOV_LANE = { 1381, 3},
.VLD1 = { 1384, 8},
.VLD2 = { 1392, 3},
.VLD3 = { 1395, 2},
.VLD4 = { 1397, 2},
.VST1 = { 1399, 7},
.VST2 = { 1406, 3},
.VST3 = { 1409, 2},
.VST4 = { 1411, 2},
.AESE = { 1413, 1},
.AESD = { 1414, 1},
.AESMC = { 1415, 1},
.AESIMC = { 1416, 1},
.SHA1H = { 1417, 1},
.SHA1SU0 = { 1418, 1},
.SHA1SU1 = { 1419, 1},
.SHA1C = { 1420, 1},
.SHA1M = { 1421, 1},
.SHA1P = { 1422, 1},
.SHA256H = { 1423, 1},
.SHA256H2 = { 1424, 1},
.SHA256SU0 = { 1425, 1},
.SHA256SU1 = { 1426, 1},
.VJCVT = { 1427, 1},
.VSDOT = { 1428, 4},
.VUDOT = { 1432, 4},
.VDOT = { 1436, 2},
.VMMLA = { 1438, 1},
.VFMAL = { 1439, 2},
.VFMSL = { 1441, 2},
.VCMLA = { 1443, 5},
.VCADD = { 1448, 2},
.VSMMLA = { 1450, 1},
.VUMMLA = { 1451, 1},
.VUSMMLA = { 1452, 1},
.VSUDOT = { 1453, 2},
.VUSDOT = { 1455, 4},
.VQABS = { 1459, 1},
.VQNEG = { 1460, 1},
.VMOVX = { 1461, 1},
.VINS = { 1462, 1},
.VLD2R = { 1463, 1},
.VLD3R = { 1464, 1},
.VLD4R = { 1465, 1},
.VLD1_LANE = { 1466, 3},
.VLD2_LANE = { 1469, 3},
.VLD3_LANE = { 1472, 3},
.VLD4_LANE = { 1475, 3},
.VST1_LANE = { 1478, 3},
.VST2_LANE = { 1481, 3},
.VST3_LANE = { 1484, 3},
.VST4_LANE = { 1487, 3},
.IT = { 1490, 1},
.TT = { 1491, 1},
.TTT = { 1492, 1},
.TTA = { 1493, 1},
.TTAT = { 1494, 1},
.SG = { 1495, 1},
.BXNS = { 1496, 1},
.BLXNS = { 1497, 1},
.PAC = { 1498, 1},
.PACBTI = { 1499, 1},
.AUT = { 1500, 1},
.AUTG = { 1501, 1},
.BTI = { 1502, 1},
.WLS = { 1503, 1},
.WLSTP = { 1504, 1},
.DLS = { 1505, 1},
.DLSTP = { 1506, 1},
.LE = { 1507, 1},
.LETP = { 1508, 1},
.LCTP = { 1509, 1},
.BF = { 1510, 1},
.BFX = { 1511, 1},
.BFL = { 1512, 1},
.BFLX = { 1513, 1},
.BFCSEL = { 1514, 1},
.CX1 = { 1515, 1},
.CX1A = { 1516, 1},
.CX1D = { 1517, 1},
.CX1DA = { 1518, 1},
.CX2 = { 1519, 1},
.CX2A = { 1520, 1},
.CX2D = { 1521, 1},
.CX2DA = { 1522, 1},
.CX3 = { 1523, 1},
.CX3A = { 1524, 1},
.CX3D = { 1525, 1},
.CX3DA = { 1526, 1},
.VCX1 = { 1527, 2},
.VCX1A = { 1529, 2},
.VCX2 = { 1531, 2},
.VCX2A = { 1533, 2},
.VCX3 = { 1535, 2},
.VCX3A = { 1537, 2},
.VPT = { 1539, 1},
.VPST = { 1540, 1},
.VPSEL = { 1541, 1},
.VPNOT = { 1542, 1},
.VCTP = { 1543, 1},
.VADDV = { 1544, 1},
.VADDVA = { 1545, 1},
.VADDLV = { 1546, 1},
.VADDLVA = { 1547, 1},
.VMAXV = { 1548, 1},
.VMAXAV = { 1549, 1},
.VMINV = { 1550, 1},
.VMINAV = { 1551, 1},
.VMAXNMV = { 1552, 1},
.VMAXNMAV = { 1553, 1},
.VMINNMV = { 1554, 1},
.VMINNMAV = { 1555, 1},
.VABAV = { 1556, 1},
.VMLADAV = { 1557, 1},
.VMLADAVA = { 1558, 1},
.VMLADAVX = { 1559, 1},
.VMLADAVAX = { 1560, 1},
.VMLALDAV = { 1561, 1},
.VMLALDAVA = { 1562, 1},
.VMLALDAVX = { 1563, 1},
.VMLALDAVAX = { 1564, 1},
.VMLSDAV = { 1565, 1},
.VMLSDAVA = { 1566, 1},
.VMLSDAVX = { 1567, 1},
.VMLSDAVAX = { 1568, 1},
.VMLSLDAV = { 1569, 1},
.VMLSLDAVA = { 1570, 1},
.VMLSLDAVX = { 1571, 1},
.VMLSLDAVAX = { 1572, 1},
.VRMLALDAVH = { 1573, 1},
.VRMLALDAVHA = { 1574, 1},
.VRMLALDAVHX = { 1575, 1},
.VRMLALDAVHAX = { 1576, 1},
.VRMLSLDAVH = { 1577, 1},
.VRMLSLDAVHA = { 1578, 1},
.VRMLSLDAVHX = { 1579, 1},
.VRMLSLDAVHAX = { 1580, 1},
.VMLAV = { 1581, 1},
.VMLAVA = { 1582, 1},
.VMLSV = { 1583, 1},
.VMLSVA = { 1584, 1},
.VCMUL = { 1585, 1},
.VHCADD = { 1586, 2},
.VBRSR = { 1588, 1},
.VSHLC = { 1589, 1},
.VDDUP = { 1590, 1},
.VIDUP = { 1591, 1},
.VDWDUP = { 1592, 1},
.VIWDUP = { 1593, 1},
.VMOVNB = { 1594, 1},
.VMOVNT = { 1595, 1},
.VQMOVNB = { 1596, 1},
.VQMOVNT = { 1597, 1},
.VQMOVUNB = { 1598, 1},
.VQMOVUNT = { 1599, 1},
.VSHLLB = { 1600, 1},
.VSHLLT = { 1601, 1},
.VMULLB = { 1602, 1},
.VMULLT = { 1603, 1},
.VMLALB = { 1604, 1},
.VMLALT = { 1605, 1},
.VMLSLB = { 1606, 1},
.VMLSLT = { 1607, 1},
.VSHRNB = { 1608, 1},
.VSHRNT = { 1609, 1},
.VRSHRNB = { 1610, 1},
.VRSHRNT = { 1611, 1},
.VQSHRNB = { 1612, 1},
.VQSHRNT = { 1613, 1},
.VQRSHRNB = { 1614, 1},
.VQRSHRNT = { 1615, 1},
.VQSHRUNB = { 1616, 1},
.VQSHRUNT = { 1617, 1},
.VQRSHRUNB = { 1618, 1},
.VQRSHRUNT = { 1619, 1},
.VQDMLADH = { 1620, 1},
.VQDMLADHX = { 1621, 1},
.VQDMLSDH = { 1622, 1},
.VQDMLSDHX = { 1623, 1},
.VQRDMLADH = { 1624, 1},
.VQRDMLADHX = { 1625, 1},
.VQRDMLSDH = { 1626, 1},
.VQRDMLSDHX = { 1627, 1},
.VLDRB = { 1628, 2},
.VLDRH = { 1630, 2},
.VLDRW = { 1632, 2},
.VLDRD = { 1634, 2},
.VSTRB = { 1636, 2},
.VSTRH = { 1638, 2},
.VSTRW = { 1640, 2},
.VSTRD = { 1642, 2},
.VLD20 = { 1644, 1},
.VLD21 = { 1645, 1},
.VLD40 = { 1646, 1},
.VLD41 = { 1647, 1},
.VLD42 = { 1648, 1},
.VLD43 = { 1649, 1},
.VST20 = { 1650, 1},
.VST21 = { 1651, 1},
.VST40 = { 1652, 1},
.VST41 = { 1653, 1},
.VST42 = { 1654, 1},
.VST43 = { 1655, 1},
._COUNT = { 1656, 0},
}

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core/rexcode/isa/arm32/tables/arm32.bucket_list.bin
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core/rexcode/isa/arm32/tests/smoke.odin
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@@ -389,7 +389,7 @@ run_smoke :: proc() {
check("VFMSL Q", .VFMSL, 1, 0xFCA00850, 0xFFB00F50)
check("VCVT BF16", .VCVT, 10, 0xF3B60600, 0xFFBF0FD0)
check("VDOT BF16 D", .VDOT, 0, 0xFC000D00, 0xFFB00F10)
check("VFMA BF16 Q", .VFMA, 9, 0xFC300850, 0xFFB00F50)
check("VFMA BF16 Q", .VFMA, 7, 0xFC300850, 0xFFB00F50)
check("VMMLA BF16 Q", .VMMLA, 0, 0xFC000C40, 0xFFB00F50)
// ---- Barriers / hints: ESB, PSB CSYNC, TSB CSYNC, CSDB, SB ----
@@ -513,8 +513,6 @@ run_smoke :: proc() {
check("VQDMULL lane .S16",.VQDMULL, 2, 0xF2900B40, 0xFFB00F50)
check("VQDMLAL lane .S32",.VQDMLAL, 3, 0xF2A00340, 0xFFB00F50)
check("VQDMLSL lane", .VQDMLSL, 2, 0xF2900740, 0xFFB00F50)
check("VFMA lane D", .VFMA, 7, 0xF2A00040, 0xFFB00F50)
check("VFMS lane Q", .VFMS, 7, 0xF3A00440, 0xFFB00F50)
check("VQRDMLAH lane", .VQRDMLAH, 4, 0xF2900E40, 0xFFB00F50)
check("VQRDMLSH lane", .VQRDMLSH, 4, 0xF2900F40, 0xFFB00F50)
check("VCMLA lane D", .VCMLA, 2, 0xFE000800, 0xFFB00F10)