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asm: reenable riscv64

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This commit is contained in:
gingerBill
2026-08-25 19:30:38 +01:00
parent ee68d39c20
commit f7f3d3f198
5 changed files with 76 additions and 2 deletions
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33
core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin
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@@ -128,6 +128,17 @@ main :: proc() {
ClobberFlag_NX = 1<<4, // inexact
};
char const *clobber_flag_bit_name(u16 bit) {
switch (bit) {
case ClobberFlag_NV: return "nv";
case ClobberFlag_DZ: return "dz";
case ClobberFlag_OF: return "of";
case ClobberFlag_UF: return "uf";
case ClobberFlag_NX: return "nx";
}
return "?";
}
enum ClobberRegs : u8 {
ClobberReg_RA = 1<<0, // x1, implicit link on C.JAL / C.JALR
ClobberReg_SP = 1<<1, // x2, implicit base on the *SP compressed forms
@@ -174,6 +185,24 @@ main :: proc() {
return \"<reg>\";
}
u16 flag_from_name(String const &name) {
static const struct {String name; ClobberFlags flag; } table[] = {
{str_lit("nv"), ClobberFlag_NV},
{str_lit("dz"), ClobberFlag_DZ},
{str_lit("of"), ClobberFlag_OF},
{str_lit("uf"), ClobberFlag_UF},
{str_lit("nx"), ClobberFlag_NX},
};
for (auto const &t : table) {
if (name == t.name) {
return cast(u16)t.flag;
}
}
return 0;
}
u16 flags_from_name(String const &name) {
static const struct { String name; ClobberFlags flag; } table[] = {
// flags: accrued FP exception flags (fcsr[4:0])
@@ -232,6 +261,10 @@ main :: proc() {
bool reads_mem;
SideEffectFlags side_effects;
ClobberFlags flags_rd_call() const {
return {};
}
bool implies_clobber_flags() const {
return (flags_wr != 0);
}

4
core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin
View File

@@ -306,6 +306,10 @@ main :: proc() {
bool reads_mem;
SideEffectFlags side_effects;
ClobberFlags flags_rd_call() const {
return flags_rd;
}
bool implies_clobber_flags() const {
u16 const FLAGS_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF|
ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF;

4
src/asm_tables_amd64.cpp
View File

@@ -309,6 +309,10 @@ struct Asm_amd64 {
bool reads_mem;
SideEffectFlags side_effects;
ClobberFlags flags_rd_call() const {
return flags_rd;
}
bool implies_clobber_flags() const {
u16 const FLAGS_MASK = ClobberFlag_CF|ClobberFlag_PF|ClobberFlag_AF|
ClobberFlag_ZF|ClobberFlag_SF|ClobberFlag_OF;

33
src/asm_tables_riscv.cpp
View File

@@ -76,6 +76,17 @@ struct Asm_riscv {
ClobberFlag_NX = 1<<4, // inexact
};
char const *clobber_flag_bit_name(u16 bit) {
switch (bit) {
case ClobberFlag_NV: return "nv";
case ClobberFlag_DZ: return "dz";
case ClobberFlag_OF: return "of";
case ClobberFlag_UF: return "uf";
case ClobberFlag_NX: return "nx";
}
return "?";
}
enum ClobberRegs : u8 {
ClobberReg_RA = 1<<0, // x1, implicit link on C.JAL / C.JALR
ClobberReg_SP = 1<<1, // x2, implicit base on the *SP compressed forms
@@ -122,6 +133,24 @@ struct Asm_riscv {
return "<reg>";
}
u16 flag_from_name(String const &name) {
static const struct {String name; ClobberFlags flag; } table[] = {
{str_lit("nv"), ClobberFlag_NV},
{str_lit("dz"), ClobberFlag_DZ},
{str_lit("of"), ClobberFlag_OF},
{str_lit("uf"), ClobberFlag_UF},
{str_lit("nx"), ClobberFlag_NX},
};
for (auto const &t : table) {
if (name == t.name) {
return cast(u16)t.flag;
}
}
return 0;
}
u16 flags_from_name(String const &name) {
static const struct { String name; ClobberFlags flag; } table[] = {
// flags: accrued FP exception flags (fcsr[4:0])
@@ -180,6 +209,10 @@ struct Asm_riscv {
bool reads_mem;
SideEffectFlags side_effects;
ClobberFlags flags_rd_call() const {
return {};
}
bool implies_clobber_flags() const {
return (flags_wr != 0);
}

4
src/check_asm.cpp
View File

@@ -1632,7 +1632,7 @@ gb_internal bool check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm
facts->gen_regs = produced | pinned_param_writes;
facts->gen_flags = cast(u16)clobber.flags_wr;
facts->read_flags = cast(u16)clobber.flags_rd;
facts->read_flags = cast(u16)clobber.flags_rd_call();
// NOTE(bill): mnemonics such as `xor r, r` / `sub r, r` act as zeroing the destination
// independent of its prior value: the read is architecturally dead, so it must not count as a use.
@@ -2813,7 +2813,7 @@ gb_internal void check_asm_template_from_entity(CheckerContext *c, Entity *e, De
if (build_context.metrics.arch == TargetArch_amd64) {
check_asm_template(&g_asm_amd64, c, e, d);
} else if (build_context.metrics.arch == TargetArch_riscv64) {
// check_asm_template(&g_asm_riscv, c, e, d);
check_asm_template(&g_asm_riscv, c, e, d);
} else {
error(e->token, "asm templates are not currently supported for this target");
}