252 Commits

Author SHA1 Message Date
gingerBill
f7f3d3f198 asm: reenable riscv64 2026-08-25 19:30:38 +01:00
gingerBill
032566714c asm: correctly handle flags in the CFG 2026-08-24 22:56:49 +01:00
gingerBill
322f59dae0 Implement a CFG for the assembler to improve the soundness of the checks 2026-08-24 21:49:32 +01:00
gingerBill
9ae9a9bf99 asm: Add support for constraint checks such as division by zero or overshifting 2026-08-24 18:18:28 +01:00
gingerBill
2f588e0329 Correct clobbering for instructions which did not write actually write to memory 2026-08-24 12:20:45 +01:00
gingerBill
39afdfc609 Begin work on improving #pure error handling 2026-08-24 12:13:24 +01:00
gingerBill
c3c3aa1533 Add #pure directive for asm templates 2026-08-24 11:46:07 +01:00
gingerBill
34e7a3bb58 Update binary tables 2026-08-24 11:02:06 +01:00
gingerBill
c41c0fb376 Add non-deterministic flags to x86 2026-08-24 11:01:22 +01:00
kalsprite
deb45f3e6a asm named slots 2026-08-23 21:34:31 -07:00
gingerBill
648c418fc4 Restrict riscv to only allow [base + disp] (i.e. disallow index*scale style things) 2026-08-21 14:31:58 +01:00
gingerBill
4a4a5045f8 Check for float register width exactly for risc-v frontend 2026-08-21 12:19:02 +01:00
gingerBill
a604ddceb1 Support pseudo macro mnemonics (for RISC-V) in the frontend 2026-08-21 11:47:41 +01:00
gingerBill
d0fb380c20 Support riscv _aq _rl _aqrl suffixes for mnemonics 2026-08-21 01:05:47 +01:00
gingerBill
de8c0dc4fe Fix register width test for risc-v, and improve operand slot type inference for risc-v 2026-08-21 00:38:34 +01:00
gingerBill
7a7bfea0bd Begin work on pseudo mnemonics in the checker 2026-08-20 19:12:44 +01:00
gingerBill
cfb8a109b6 Begin work on pseudo-aliases 2026-08-20 17:51:47 +01:00
gingerBill
84f9bc76f9 Mockout inline asm for riscv 2026-08-20 14:42:42 +01:00
gingerBill
1009ab0c62 Add riscv.clobber_forms.bin 2026-08-20 11:45:50 +01:00
gingerBill
f3899c1825 rexcode: riscv INSTRUCTION_TABLE which includes the clobber information 2026-08-20 11:43:26 +01:00
gingerBill
2ebc25001d Add missing risc-v instructions to rexcode 2026-08-20 11:08:03 +01:00
gingerBill
ce6ad239bf Merge pull request #7362 from odin-lang/bill/rexcode
`core:rexcode` improvements
2026-08-20 10:54:07 +02:00
gingerBill
baae2636b8 Add support for x86 mnenomics in and out 2026-08-20 09:53:28 +01:00
gingerBill
ea04ce30e4 Remove dead comment 2026-08-19 16:45:23 +01:00
gingerBill
22bdf11436 Rename to instruction_table.odin 2026-08-19 16:44:42 +01:00
gingerBill
bda4c2cd95 Merge ENCODING_TABLE and CLOBBER_TABLE into a single INSTRUCTION_TABLE 2026-08-19 16:44:19 +01:00
gingerBill
7a01de6a45 Add extra tables to cpp-gen.odin 2026-08-19 16:08:02 +01:00
gingerBill
8956deb322 Check for implicitly read registers which have not be handled 2026-08-19 12:29:54 +01:00
gingerBill
4cf22b3efa Merge pull request #7380 from dbriemann/dlb/vpdpwssd
Add AVX-512 VNNI VPDPWSSD support to inline assembly
2026-08-19 12:53:41 +02:00
gingerBill
8d0cc4d64b Clobber implicit_wr and implicit_rd 2026-08-19 11:03:50 +01:00
David Linus Briemann
36af738347 core:rexcode: regenerate x86 encoding tables 2026-08-19 09:09:58 +02:00
David Linus Briemann
8370fdaf7c core:rexcode: add AVX-512 VNNI VPDPWSSD 2026-08-19 09:09:50 +02:00
gingerBill
587f030cbf Remove use of do 2026-08-18 18:23:42 +01:00
gingerBill
65ddd08984 Merge branch 'master' into bill/rexcode 2026-08-18 18:23:03 +01:00
gingerBill
14184744ee Add missing x86.clobber_forms.bin 2026-08-18 15:13:37 +01:00
gingerBill
6e17e7a2de Add missing x86 instructions 2026-08-18 13:19:23 +01:00
gingerBill
8d33a47fab Improve comment for the CLOBBER_TABLE 2026-08-18 11:54:45 +01:00
gingerBill
18df1ed23e Correct clobber_table.odin 2026-08-18 11:44:35 +01:00
gingerBill
80d7f6462a Minor clean up 2026-08-18 11:33:49 +01:00
gingerBill
35ae861ff6 Use number rather than enum 2026-08-18 11:28:54 +01:00
gingerBill
8e807fb7aa Use new clobber forms in check_asm.cpp 2026-08-18 11:23:20 +01:00
gingerBill
b1b08c13c0 Update clobber table to encode the clobbering for each of the forms 2026-08-18 11:20:30 +01:00
gingerBill
a2bcf3177a Improve error messages for register class printing 2026-08-17 21:10:24 +01:00
gingerBill
8f2a4346fc Handle _SSE edge cases 2026-08-17 19:31:38 +01:00
gingerBill
e2e4a61003 Remove suffixes 2026-08-17 19:29:42 +01:00
gingerBill
db94c5a6cb Begin work in %flags.zf et al 2026-08-17 12:25:17 +01:00
gingerBill
344e8afa36 #clobber cc -> #clobber flags 2026-08-17 12:10:08 +01:00
Flāvius
b54c60b76a rexcode: the x86 test suite could fail and the build said PASS
Found by accident, and worse than the bug that found it. Five deliberately
broken decode cases came back green through `build.lua --test --isa x86`, while
running the same suite directly reported "253/258 PASSED, 5 FAILED".

Two independent holes, both open, so neither backstopped the other:

  - the x86 test binary ended at `print_summary()` and never called `os.exit`,
    so it exited 0 no matter how many cases failed;
  - `do_test` looked for the words "N failed" in the output, and the x86
    harness prints "N FAILED" — a lowercase-only Lua pattern, so the largest
    suite in the tree was exempt from its own gate.

The exit code is the check that should have been load-bearing, so the harness
sets it. The output match stays as a backstop for a suite that forgets to, and
is now case-insensitive.

How long this has been true is not knowable from here — every x86 regression
since the pattern was written would have been reported as PASS.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01Riok9vMpkLmo78wsVKJHhz
2026-08-16 12:05:52 -04:00
Flāvius
3e3eec090d x86: +r decoding was legacy-only, so BSWAP could not be read back
`bswap` is `0F C8+rd` — the register rides in the opcode's low three bits, like
`push`/`pop`/`xchg`/`mov`, but behind an escape byte. The decoder's retry at the
+r base opcode was gated on `esc == .NONE`, so only the register-0 forms
(`0F C8` = bswap eax, `48 0F C8` = bswap rax) landed on a table entry directly;
the other seven registers came back INVALID_OPCODE. Emission was always correct
— every `bswap` this compiler has ever produced runs — but a disassembly
containing one stopped dead, which is how it surfaced: three functions in
sigil's JIT corpus disassembled to a header with no instructions under it.

The table was never the problem. BSWAP is in `tablegen/encoding_table.odin` and
in the generated decode table, exactly where it should be.

Fixing the gate meant looking at why the retry existed twice. There is a correct
+r handler further down, carrying comments that describe two bugs already found
and fixed in it — "scan ALL entries, not just the first", "scan for the sized
register rather than assuming op0" — and the copy inside the retry had received
neither, plus a third of its own. So the retry now re-runs only the LOOKUP and
falls through to the single handler, which fixes two more instruction families
that were equally undecodable:

  - `xchg rAX, r` (90+rd): 0x90's run sorts NOP ahead of XCHG, and the copy
    tested only the first entry for a +r form, so every `xchg rAX, r` was
    rejected.
  - `push bx` / `pop bx` / `mov cx, imm` (any +r under 0x66): the copy passed
    `prefix` where the legacy row wants 0, since for legacy opcodes 0x66 is
    operand size rather than part of the opcode's identity.

Two supporting changes. The shared handler's default answer is now the first +r
entry rather than `idx.start`, so a fall-through at 0x90 cannot answer NOP for
an `xchg`. And a base-opcode retry that does not land on a +r form is now an
error rather than a fall-through: decoding 0x0E as the 0x08 entry (OR) would be
a wrong instruction reported confidently, which is worse than an unknown byte.

Verified three ways. Every opcode in every escape map was decoded before and
after: 154 combinations changed, every one of them INVALID -> valid, and nothing
that already decoded decodes differently. All 24 BSWAP encodings and all 96
legacy +r encodings were diffed against llvm-mc's disassembly and agree
operand-for-operand. Six new decode-only cases pin the three families; five of
them fail without this change.

(Two remaining differences from llvm-mc are deliberate and documented here:
implicit accumulators are left unmaterialized so a short form re-encodes to the
short form, and `48 90` reads as `xchg rax` rather than `nop`.)

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01Riok9vMpkLmo78wsVKJHhz
2026-08-16 12:05:42 -04:00
gingerBill
08f3be70cf Add helper methods to the asm_tables_amd64.cpp 2026-08-12 21:18:10 +01:00