Commit Graph

52 Commits

Author SHA1 Message Date
gingerBill
648c418fc4 Restrict riscv to only allow [base + disp] (i.e. disallow index*scale style things) 2026-08-21 14:31:58 +01:00
gingerBill
4a4a5045f8 Check for float register width exactly for risc-v frontend 2026-08-21 12:19:02 +01:00
gingerBill
a604ddceb1 Support pseudo macro mnemonics (for RISC-V) in the frontend 2026-08-21 11:47:41 +01:00
gingerBill
d0fb380c20 Support riscv _aq _rl _aqrl suffixes for mnemonics 2026-08-21 01:05:47 +01:00
gingerBill
de8c0dc4fe Fix register width test for risc-v, and improve operand slot type inference for risc-v 2026-08-21 00:38:34 +01:00
gingerBill
7a7bfea0bd Begin work on pseudo mnemonics in the checker 2026-08-20 19:12:44 +01:00
gingerBill
cfb8a109b6 Begin work on pseudo-aliases 2026-08-20 17:51:47 +01:00
gingerBill
84f9bc76f9 Mockout inline asm for riscv 2026-08-20 14:42:42 +01:00
gingerBill
baae2636b8 Add support for x86 mnenomics in and out 2026-08-20 09:53:28 +01:00
gingerBill
ea04ce30e4 Remove dead comment 2026-08-19 16:45:23 +01:00
gingerBill
22bdf11436 Rename to instruction_table.odin 2026-08-19 16:44:42 +01:00
gingerBill
bda4c2cd95 Merge ENCODING_TABLE and CLOBBER_TABLE into a single INSTRUCTION_TABLE 2026-08-19 16:44:19 +01:00
gingerBill
7a01de6a45 Add extra tables to cpp-gen.odin 2026-08-19 16:08:02 +01:00
gingerBill
8956deb322 Check for implicitly read registers which have not be handled 2026-08-19 12:29:54 +01:00
gingerBill
4cf22b3efa Merge pull request #7380 from dbriemann/dlb/vpdpwssd
Add AVX-512 VNNI VPDPWSSD support to inline assembly
2026-08-19 12:53:41 +02:00
gingerBill
8d0cc4d64b Clobber implicit_wr and implicit_rd 2026-08-19 11:03:50 +01:00
David Linus Briemann
36af738347 core:rexcode: regenerate x86 encoding tables 2026-08-19 09:09:58 +02:00
David Linus Briemann
8370fdaf7c core:rexcode: add AVX-512 VNNI VPDPWSSD 2026-08-19 09:09:50 +02:00
gingerBill
6e17e7a2de Add missing x86 instructions 2026-08-18 13:19:23 +01:00
gingerBill
8d33a47fab Improve comment for the CLOBBER_TABLE 2026-08-18 11:54:45 +01:00
gingerBill
18df1ed23e Correct clobber_table.odin 2026-08-18 11:44:35 +01:00
gingerBill
80d7f6462a Minor clean up 2026-08-18 11:33:49 +01:00
gingerBill
35ae861ff6 Use number rather than enum 2026-08-18 11:28:54 +01:00
gingerBill
8e807fb7aa Use new clobber forms in check_asm.cpp 2026-08-18 11:23:20 +01:00
gingerBill
b1b08c13c0 Update clobber table to encode the clobbering for each of the forms 2026-08-18 11:20:30 +01:00
gingerBill
a2bcf3177a Improve error messages for register class printing 2026-08-17 21:10:24 +01:00
gingerBill
8f2a4346fc Handle _SSE edge cases 2026-08-17 19:31:38 +01:00
gingerBill
e2e4a61003 Remove suffixes 2026-08-17 19:29:42 +01:00
gingerBill
db94c5a6cb Begin work in %flags.zf et al 2026-08-17 12:25:17 +01:00
gingerBill
344e8afa36 #clobber cc -> #clobber flags 2026-08-17 12:10:08 +01:00
gingerBill
08f3be70cf Add helper methods to the asm_tables_amd64.cpp 2026-08-12 21:18:10 +01:00
gingerBill
dbe5761bb0 Minor change 2026-08-12 16:19:58 +01:00
gingerBill
5eb0239474 Utilize triple quote strings within the C++ asm table generation 2026-08-12 16:09:18 +01:00
gingerBill
43f078aedc Infer asm #side_effects where possible from the mnemonics 2026-08-12 14:52:37 +01:00
gingerBill
b32846bb35 Minor change to implies_side_effects 2026-08-12 14:16:10 +01:00
gingerBill
2300a48782 Infer #clobber memory and #clobber cc from the mnemonics directly 2026-08-12 12:45:48 +01:00
gingerBill
b9a7ed9942 Add amd64 clobber table to asm_tables_amd64.cpp 2026-08-12 11:33:07 +01:00
gingerBill
6bd2fd7e8b Add clobber table for x86 2026-08-12 11:25:03 +01:00
gingerBill
21ad041232 Handle prefixes better 2026-08-11 17:44:55 +01:00
gingerBill
5621cbc85a Improve scoring for operand error handling 2026-08-11 15:06:14 +01:00
gingerBill
ce6346a20f Check immediates if they support the range or are not allowed (e.g. floats) 2026-08-11 14:52:21 +01:00
gingerBill
ed2bc91596 Add some missing vector instructions to the x86 encoding table 2026-08-11 14:18:37 +01:00
gingerBill
ef21ffa285 Templatize the check_asm.cpp code ready for other architectures 2026-08-11 14:00:41 +01:00
gingerBill
c717cb4ae9 Implement check_asm_operand_size_class 2026-08-11 13:08:39 +01:00
gingerBill
b0364d2c60 Improve error message for invalid operand kinds 2026-08-11 11:56:03 +01:00
gingerBill
400203c344 Verify the asm instruction operands against the Encoding.ops 2026-08-11 11:47:48 +01:00
gingerBill
5ca7638bb2 Check asm instruction operand count 2026-08-11 11:11:53 +01:00
gingerBill
70ca5c0936 Validate the names of mnemonics, prefixes, and registers for amd64 2026-08-11 10:44:34 +01:00
gingerBill
d827be77cd Begin work on generating the AMD64 asm tables for C++ 2026-08-11 10:15:41 +01:00
Flāvius
263e82a48a rexcode/x86: byte-exact encode/decode round-trip (247 -> 0)
Fix the operand-size/prefix bug class reported by the sigil backend, then close
every failure a whole-ISA encode->decode->re-encode audit surfaced -- 247 -> 0
over the 1165 round-trippable legacy forms.

Encode/decode:
- MOVSX/MOVZX take 66h from the destination, not the source (CRC32, whose r/m
  source drives 66h, is unchanged)
- operand-less 16-bit forms (CBW/CWD, MOVSW/CMPSW/SCASW/LODSW/STOSW,
  IRET/PUSHF/POPF) emit 66h via a new opsize_16 flag
- CRC32/MOVBE and POPCNT/LZCNT/TZCNT: mandatory F2/F3 beats 66h on decode
- mandatory-prefix REP double-encode: F2/F3 no longer re-emitted as REP
- fixed-ModR/M decode: x87 (FNOP/FCHS/FADD ST(i)/...) and the 0F 01/AE/C7/1E
  system-op groups (VMCALL/RDTSCP/LFENCE/ENDBR/...); gen.odin preserves the
  fixed ModR/M byte, the decoder matches and consumes it
- implicit-operand round-trip (accumulator short forms, x87 ST(i), xchg) via a
  positional matcher + emit path; accumulators stay implicit so hand-built
  `add eax, imm` keeps the general form (typed-builder consistency)
- MOV to/from CR/DR/segment (were decoding as GPRs); reg-vs-mem disambiguation
  (RDRAND vs VMPTRLD, MOVLHPS vs MOVHPS); x87 M80 operand size; PINSRW; NOP vs
  XCHG at 0x90
- LOCK standalone; ENTER two immediates; PUSH/POP FS/GS (segment fixed by the
  opcode + non-cacheable); BOUND marked 32-bit-only; RDRAND/RDSEED r16
  (66 is operand-size, resolved against the mandatory-66 VMCLEAR by ModR/M)

Tools/tests:
- revive dump_verify_input + verify_against_llvm (stale Result API; drop the
  aliases that were masking the fixed bugs); align verify_tables with the
  preserved fixed-ModR/M ext
- new tests/test_narrow_widths.odin: byte-exact vs llvm-mc + round-trip guards
- fold the bit-rotted tests32 package into the main suite (i386 Mode._32 paths)

248 tests pass; verify_tables passes.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01115ktMoX5qGAfp1VemBzCP
2026-07-02 10:32:00 -04:00