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inst_add(X0, X1, X2) encoded `add v0.16b, v1.16b, v2.16b`. It built the operand as op_v_16b(u8(reg_hw(dst))), which throws away the register's class and rebuilds a V register from the bare number -- so an X register became a V register before the matcher, whose whole job is to reject that, ever saw it. It encoded, round-tripped, and printed cleanly. Seven mnemonics with both a scalar and a vector three-register form were affected: add, and, bic, eor, orn, orr, sub. The vector constructors now take the register the caller actually has and put the arrangement in op.size, so the class survives. A wrong class matches no form and encode reports it; the right class picks the right form, which is what the matcher was always supposed to do. The same laundering hid a second bug. Because every arrangement built the same Odin signature, all of a mnemonic's arrangements collapsed onto one builder name and only the first survived -- ADD has seven NEON forms and six were unreachable. 229 mnemonics were in that state. The arrangement is now part of the builder name (inst_add_v8b_v8b_v8b), so they are all reachable: 992 builders becomes 1847. The overload group is unchanged, since it still dedups by Odin signature, so inst_add(V0, V1, V2) still means .16b as before. Making them reachable exposed two pre-existing bugs, both fixed here: CMLE/CMLT/FCMLE/FCMLT compare against zero and the zero is part of the syntax rather than an encoded operand, so their disassembly was missing the trailing `#0`/`#0.0` and no assembler would take it; and BFCVTN was typed .8h at the destination where the architecture says .4h (BFCVTN2 is the .8h one, and was already right). Verified against llvm-mc: of the 874 all-register vector builders, 803 are byte-exact and none disagree. The 10 that llvm cannot assemble are the already-known modelling gaps -- SM3TT lane indices, TBL/TBX register lists, and PMULL's .1q destination, which the arrangement encoding cannot represent since 1 lane * 16 bytes collides with 16B. The other 61 are the harness passing V registers where a scalar B/H/S/D/Q view is required, which is the class check doing its job. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA