mirror of
https://github.com/odin-lang/Odin.git
synced 2026-09-02 10:13:35 +00:00
5cba6402f6
The arm64 pass turned up the same class of bug elsewhere: mnemonics named
after an encoding rather than after what an assembler accepts, and forms
that no caller can reach because the thing that tells them apart is not
checked.
mips
* The printer mapped every `_` to `.`, but MSA spells the sign qualifier
with an underscore and only the element size with a dot: `adds_s.b`,
`max_s.h`, `copy_u.w`. `adds.s.b` is rejected by an assembler. 91
mnemonics were printing text that would not reassemble. The name alone
cannot decide it -- MSA's ADDS_S_D and the FP convert CVT_S_D have the
same shape and want opposite treatment -- so the family is read off the
form's feature.
* `encode` now takes `features: Feature_Set = FEATURES_ALL` and skips
forms outside it, mirroring `decode`, which has had that parameter all
along. That asymmetry was the reason 12 mnemonics carried an ISA-variant
suffix: with no way to say which MIPS you were targeting, the pre-R6 and
R6 encodings of `mul` had to be two enum members. They are now one
mnemonic with two forms. Eight of the twelve did not even need the
feature filter -- pre-R6 MADD takes rs,rt while the PS2 MMI MADD takes
rd,rs,rt, so operand matching alone separates them. Verified against
llvm-mc: pre-R6 `mul` 712a4002, R6 `mul` 012a4098, `madd $t1,$t2`
712a0000. The printer's hand-written override table is gone.
arm32
* 20 `*_LANE` mnemonics folded into their base. The lane form differs from
the base in an operand TYPE already (DPR_ELEM vs DPR), so the matcher
could always tell them apart; the split only cost us the printed name,
which was the enum name verbatim -- `vqdmulh_lane`, which no assembler
takes. VMOV/VLD1-4/VST1-4 are left alone: their lane forms collide with
the base because register lists and lane indices are not modelled.
riscv
* ZEXT_H and REV8 each carry an RV32 and an RV64 encoding with identical
operands, and the forms were already tagged rv32_only / rv64_only -- the
encoder just never looked. `encode` now takes `xlen: XLEN = .RV64` and
filters, so the RV64 encodings are reachable at all: zext.h 0805c53b and
rev8 6b85d513, both confirmed against llvm-mc.
mos6502
* SAX_NMOS folded into SAX. The undocumented NMOS store-A&X and the
HuC6280 register swap share the mnemonic `sax`; one takes a memory
operand and the other takes none, so they are just two form sets.
Verified: every rexcode suite matches HEAD exactly, all 13 packages build,
and MIPS mnemonics llvm-mc does not recognise drop from 448 to 354.
Still open: arm32 has 201 form signatures no caller can select, because the
NEON data type (.i8/.i16/.f32) is not an operand -- `inst_vadd(d0,d1,d2)`
always yields the first form, and only a decoder-supplied form_id hint can
pick another. 38 arm32 mnemonics still carry encoding-shaped names
(VPADD_F, VCEQ_Z, VLDRB_GATHER, VMOV_Q_R, ...).
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>
362 lines
13 KiB
Odin
362 lines
13 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_riscv
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import "core:rexcode/isa"
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// =============================================================================
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// RISC-V DECODER
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// =============================================================================
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//
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// Two passes, mirroring mips/decoder.odin. The RISC-V-specific bits:
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//
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// * Two-level dispatch: primary opcode (bits 6-0) directly indexes
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// DECODE_INDEX_OPCODE[128]; opcode 0x53 (OP-FP) is sub-bucketed
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// further by funct7 (bits 31-25). Within each bucket, linear scan
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// of `(word & e.mask) == e.bits`.
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//
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// * XLEN filter: the decoder takes an XLEN parameter (.RV32 / .RV64);
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// entries flagged `rv32_only` are skipped when decoding RV64, and
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// vice versa.
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//
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// * Scattered immediates: B-type and J-type targets are reconstructed
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// via gather_b / gather_j helpers in encoder.odin and emitted as
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// RELATIVE-kind operands carrying the absolute byte target.
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XLEN :: enum u8 {
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RV32,
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RV64,
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}
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Instruction_Info :: struct {
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offset: u32,
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decode_entry: u16,
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_: u16,
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}
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#assert(size_of(Instruction_Info) == 8)
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decode :: proc(
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data: []u8,
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relocs: []Relocation,
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instructions: ^[dynamic]Instruction,
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inst_info: ^[dynamic]Instruction_Info,
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label_defs: ^[dynamic]Label_Definition,
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errors: ^[dynamic]Error,
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xlen: XLEN = .RV64,
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) -> (byte_count: u32, ok: bool) {
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n_bytes := u32(len(data)) & ~u32(1) // align to halfword (RVC is 2-byte)
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errors_start := u32(len(errors))
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pending_branches: [dynamic]isa.Branch_Target
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defer delete(pending_branches)
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for byte_count < n_bytes {
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// Read the first halfword; bits[1:0] != 11 means compressed (2 bytes).
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hword_lo := read_u16_le(data, byte_count)
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ilen: u32 = 4
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word: u32
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if (hword_lo & 0x3) != 0x3 {
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ilen = 2
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word = u32(hword_lo)
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} else {
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if byte_count + 4 > n_bytes { break }
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word = read_u32_le(data, byte_count)
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}
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inst: Instruction
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info: Instruction_Info
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entry_idx := decode_one_inline(word, byte_count, xlen, ilen == 2, &inst, &info)
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if entry_idx < 0 {
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append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE})
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inst = Instruction{mnemonic = .INVALID, length = u8(ilen)}
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info = Instruction_Info{offset = byte_count}
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} else {
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inst.length = u8(ilen)
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inst_idx_for_branches := u32(len(instructions))
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for slot in 0..<inst.operand_count {
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op := &inst.ops[slot]
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if op.kind == .RELATIVE && op.relative >= 0 {
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append(&pending_branches, isa.Branch_Target{
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inst_idx = inst_idx_for_branches,
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op_idx = slot,
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target = u32(op.relative),
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})
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}
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}
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}
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append(instructions, inst)
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append(inst_info, info)
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byte_count += ilen
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}
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isa.infer_labels_from_branches(pending_branches[:], byte_count, label_defs, relocs)
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ok = u32(len(errors)) == errors_start
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return
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}
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// =============================================================================
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// Internal
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// =============================================================================
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@(private="file")
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decode_one_inline :: #force_inline proc "contextless" (
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word: u32, pc: u32, xlen: XLEN, compressed: bool,
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inst: ^Instruction, info: ^Instruction_Info,
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) -> int {
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range: Decode_Index
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if compressed {
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// RVC: 5-bit dispatch key from (op[1:0], funct3[15:13]).
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// op==0,1,2 + funct3=0..7 -> 24 buckets.
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key := (word & 0x3) | ((word >> 13) & 0x7) << 2
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range = DECODE_INDEX_RVC[key]
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} else {
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opcode := u8(word & 0x7F)
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if opcode == 0x53 {
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funct7 := u8((word >> 25) & 0x7F)
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range = DECODE_INDEX_OP_FP[funct7]
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} else {
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range = DECODE_INDEX_OPCODE[opcode]
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}
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}
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if range.count == 0 { return -1 }
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base := int(range.start)
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cnt := int(range.count)
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matched_idx := -1
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for i in 0..<cnt {
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e := &DECODE_ENTRIES[base + i]
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if !xlen_accepts(xlen, e.flags) { continue }
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if (word & e.mask) == e.bits {
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matched_idx = base + i
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break
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}
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}
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if matched_idx < 0 { return -1 }
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entry := &DECODE_ENTRIES[matched_idx]
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inst.mnemonic = entry.mnemonic
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inst.length = 4
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inst.flags = {}
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cnt_used: u8 = 0
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if entry.ops[0] != .NONE {
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inst.ops[0] = extract_operand_inline(word, pc, entry.ops[0], entry.enc[0])
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cnt_used = 1
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if entry.ops[1] != .NONE {
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inst.ops[1] = extract_operand_inline(word, pc, entry.ops[1], entry.enc[1])
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cnt_used = 2
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if entry.ops[2] != .NONE {
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inst.ops[2] = extract_operand_inline(word, pc, entry.ops[2], entry.enc[2])
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cnt_used = 3
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if entry.ops[3] != .NONE {
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inst.ops[3] = extract_operand_inline(word, pc, entry.ops[3], entry.enc[3])
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cnt_used = 4
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}
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}
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}
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}
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inst.operand_count = cnt_used
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info.offset = pc
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info.decode_entry = u16(matched_idx)
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return matched_idx
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}
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// Shared with the encoder: an rv32_only / rv64_only form is only selectable
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// when the target XLEN matches.
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@(private)
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xlen_accepts :: #force_inline proc "contextless" (xlen: XLEN, f: Encoding_Flags) -> bool {
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if f.rv32_only && xlen != .RV32 { return false }
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if f.rv64_only && xlen != .RV64 { return false }
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return true
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}
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@(private="file")
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extract_operand_inline :: #force_inline proc "contextless" (
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word: u32, pc: u32, ot: Operand_Type, en: Operand_Encoding,
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) -> Operand {
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switch en {
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case .NONE:
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return {}
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// ---- Register slots ----------------------------------------------------
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case .RD:
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return reg_operand(decode_reg(word, 7, ot))
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case .RS1:
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return reg_operand(decode_reg(word, 15, ot))
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case .RS2:
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return reg_operand(decode_reg(word, 20, ot))
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case .RS3:
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return reg_operand(decode_reg(word, 27, ot))
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// ---- Shift amounts -----------------------------------------------------
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case .SHAMT5:
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return Operand{immediate = i64((word >> 20) & 0x1F), kind = .IMMEDIATE, size = 1}
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case .SHAMT6:
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return Operand{immediate = i64((word >> 20) & 0x3F), kind = .IMMEDIATE, size = 1}
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// ---- Immediates --------------------------------------------------------
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case .IMM_I:
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return Operand{immediate = i64(gather_i(word)), kind = .IMMEDIATE, size = 2}
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case .IMM_S:
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return Operand{immediate = i64(gather_s(word)), kind = .IMMEDIATE, size = 2}
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case .IMM_U:
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return Operand{immediate = i64((word >> 12) & 0xFFFFF), kind = .IMMEDIATE, size = 4}
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case .IMM_B:
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target := u32(i32(pc) + gather_b(word))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 2}
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case .IMM_J:
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target := u32(i32(pc) + gather_j(word))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 4}
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// ---- Memory operand variants ------------------------------------------
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case .OFFSET_BASE_I:
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base := decode_reg(word, 15, .GPR)
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disp := gather_i(word)
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return Operand{mem = Memory{base = base, disp = disp}, kind = .MEMORY, size = 4}
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case .OFFSET_BASE_S:
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base := decode_reg(word, 15, .GPR)
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disp := gather_s(word)
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return Operand{mem = Memory{base = base, disp = disp}, kind = .MEMORY, size = 4}
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case .OFFSET_BASE_A:
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base := decode_reg(word, 15, .GPR)
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return Operand{mem = Memory{base = base, disp = 0}, kind = .MEMORY, size = 4}
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// ---- Specialty fields --------------------------------------------------
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case .CSR_FIELD:
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return Operand{immediate = i64((word >> 20) & 0xFFF), kind = .IMMEDIATE, size = 2}
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case .ZIMM_FIELD:
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return Operand{immediate = i64((word >> 15) & 0x1F), kind = .IMMEDIATE, size = 1}
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case .FENCE_PRED:
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return Operand{immediate = i64((word >> 24) & 0xF), kind = .IMMEDIATE, size = 1}
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case .FENCE_SUCC:
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return Operand{immediate = i64((word >> 20) & 0xF), kind = .IMMEDIATE, size = 1}
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case .ROUND_FIELD:
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return Operand{immediate = i64((word >> 12) & 0x7), kind = .IMMEDIATE, size = 1}
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case .AQRL:
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return Operand{immediate = i64((word >> 25) & 0x3), kind = .IMMEDIATE, size = 1}
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// ---- C extension register slots ---------------------------------------
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case .C_RD_RS1:
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return reg_operand(decode_reg(word, 7, ot))
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case .C_RS2:
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return reg_operand(decode_reg(word, 2, ot))
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case .C_RD_PRIMED, .C_RS2_PRIMED:
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hw := u16((word >> 2) & 0x7) + 8
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cls := u16(REG_GPR)
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if ot == .FPR_C { cls = REG_FPR }
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return reg_operand(Register(cls | hw))
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case .C_RS1_PRIMED, .C_RD_RS1_PRIMED:
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hw := u16((word >> 7) & 0x7) + 8
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cls := u16(REG_GPR)
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if ot == .FPR_C { cls = REG_FPR }
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return reg_operand(Register(cls | hw))
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// ---- C extension immediates -------------------------------------------
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case .C_IMM_CI_S:
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v := i32(((word >> 12) & 0x1) << 5 | ((word >> 2) & 0x1F))
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if v & 0x20 != 0 { v |= ~i32(0x3F) }
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
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case .C_IMM_CI_U:
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v := u32(((word >> 12) & 0x1) << 5 | ((word >> 2) & 0x1F))
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1}
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case .C_IMM_CIW:
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v := i64(((word >> 11) & 0x3) << 4 |
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((word >> 7) & 0xF) << 6 |
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((word >> 6) & 0x1) << 2 |
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((word >> 5) & 0x1) << 3)
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return Operand{immediate = v, kind = .IMMEDIATE, size = 2}
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case .C_IMM_LUI:
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v := i32(((word >> 12) & 0x1) << 17 | ((word >> 2) & 0x1F) << 12)
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if v & 0x20000 != 0 { v |= ~i32(0x3FFFF) }
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 4}
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case .C_IMM_ADDI16SP:
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v := i32(((word >> 12) & 0x1) << 9 |
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((word >> 6) & 0x1) << 4 |
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((word >> 5) & 0x1) << 6 |
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((word >> 3) & 0x3) << 7 |
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((word >> 2) & 0x1) << 5)
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if v & 0x200 != 0 { v |= ~i32(0x3FF) }
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return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2}
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case .C_IMM_CSS_W:
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v := i64(((word >> 9) & 0xF) << 2 | ((word >> 7) & 0x3) << 6)
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return Operand{immediate = v, kind = .IMMEDIATE, size = 1}
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case .C_IMM_CSS_D:
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v := i64(((word >> 10) & 0x7) << 3 | ((word >> 7) & 0x7) << 6)
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return Operand{immediate = v, kind = .IMMEDIATE, size = 2}
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case .C_IMM_CL_W:
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v := i64(((word >> 10) & 0x7) << 3 | ((word >> 6) & 0x1) << 2 | ((word >> 5) & 0x1) << 6)
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return Operand{immediate = v, kind = .IMMEDIATE, size = 1}
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case .C_IMM_CL_D:
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v := i64(((word >> 10) & 0x7) << 3 | ((word >> 5) & 0x3) << 6)
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return Operand{immediate = v, kind = .IMMEDIATE, size = 2}
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// ---- C extension memory operands --------------------------------------
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case .C_OFFSET_BASE_W:
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base := Register(REG_GPR | u16(((word >> 7) & 0x7) + 8))
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disp := i32(((word >> 10) & 0x7) << 3 | ((word >> 6) & 0x1) << 2 | ((word >> 5) & 0x1) << 6)
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return Operand{mem = Memory{base = base, disp = disp}, kind = .MEMORY, size = 4}
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case .C_OFFSET_BASE_D:
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base := Register(REG_GPR | u16(((word >> 7) & 0x7) + 8))
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disp := i32(((word >> 10) & 0x7) << 3 | ((word >> 5) & 0x3) << 6)
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return Operand{mem = Memory{base = base, disp = disp}, kind = .MEMORY, size = 4}
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case .C_SP_OFFSET_W:
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disp := i32(((word >> 12) & 0x1) << 5 | ((word >> 4) & 0x7) << 2 | ((word >> 2) & 0x3) << 6)
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return Operand{mem = Memory{base = SP, disp = disp}, kind = .MEMORY, size = 4}
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case .C_SP_OFFSET_D:
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disp := i32(((word >> 12) & 0x1) << 5 | ((word >> 5) & 0x3) << 3 | ((word >> 2) & 0x7) << 6)
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return Operand{mem = Memory{base = SP, disp = disp}, kind = .MEMORY, size = 4}
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// ---- C extension branches/jumps ---------------------------------------
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case .C_BRANCH9:
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target := u32(i32(pc) + gather_c_branch(word))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 2}
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case .C_BRANCH12:
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target := u32(i32(pc) + gather_c_jump(word))
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return Operand{relative = i64(target), kind = .RELATIVE, size = 2}
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}
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return {}
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}
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@(private="file")
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decode_reg :: #force_inline proc "contextless" (word: u32, shift: u8, ot: Operand_Type) -> Register {
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hw := u16((word >> shift) & 0x1F)
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if ot == .FPR { return Register(REG_FPR | hw) }
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return Register(REG_GPR | hw)
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}
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@(private="file")
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reg_operand :: #force_inline proc "contextless" (r: Register) -> Operand {
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return Operand{reg = r, kind = .REGISTER, size = 4}
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}
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// -----------------------------------------------------------------------------
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// Buffer-Sizing Helpers (let callers pre-size so the decode hot path never
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// reallocates; allocates no new buffers -- only the caller's arrays grow).
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// -----------------------------------------------------------------------------
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// Instruction-count ceiling for `data` (base is 4 bytes, compressed (C) 2; minimum 2).
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@(require_results)
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decode_max_instruction_count :: #force_inline proc "contextless" (data: []u8) -> int {
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return len(data) / 2
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}
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// Typical-case estimate of the instruction count for `data`.
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@(require_results)
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decode_estimate_instruction_count :: #force_inline proc "contextless" (data: []u8) -> int {
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return len(data) / 4 + 8
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}
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// Pre-size the caller's decode output arrays for `data` (reserves on top of any
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// existing elements; nil to skip; exact=true for the ceiling, else the estimate).
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decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic]Instruction_Info, label_defs: ^[dynamic]Label_Definition, data: []u8, exact: bool = false) {
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n := exact ? decode_max_instruction_count(data) : decode_estimate_instruction_count(data)
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if instructions != nil { reserve(instructions, len(instructions) + n) }
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if inst_info != nil { reserve(inst_info, len(inst_info) + n) }
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if label_defs != nil { reserve(label_defs, len(label_defs) + n) }
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}
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