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https://github.com/odin-lang/Odin.git
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a4f08f8307
Each ISA's hand-written ENCODING_TABLE (the single source of truth) now lives in a per-arch tablegen/ metaprogram that flattens it and serializes committed binary blobs; the library #loads those into @(rodata) at compile time rather than compiling a table body. No arch keeps encoding_table.odin or decoding_tables.odin -- only a generated tables.odin loader and tables/*.bin. * Two-stage, type-checked pipeline: tablegen Stage A emits human-readable generated Odin, which compiles and serializes the blobs in Stage B. * encode() goes through encoding_forms(m); decoders are unchanged apart from x86's flattened 2-D index. Decode tables are byte-identical to the old ones. * build.lua: a LuaJIT driver for the metaprograms, validations, and tests, with cross-platform gating and a clear report. * Docs refreshed; the obsolete forward-looking plan in cross_arch_design.md trimmed to what was actually built. * Attribution headers added to all rexcode source files; the generators emit them so generated files keep them.
187 lines
7.1 KiB
Odin
187 lines
7.1 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_mos6502_tests
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// Spot-check that ENCODING_TABLE entries are present with the canonical
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// opcode bytes and lengths. Covers a representative slice of every
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// CPU tier (NMOS official, NMOS undocumented, 65C02, HuC6280).
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//
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// Run with: odin run mos6502/tests
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import "core:fmt"
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import "core:os"
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import m "../"
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@(private="file") passes := 0
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@(private="file") failures := 0
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@(private="file")
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check :: proc(
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name: string,
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mn: m.Mnemonic,
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want_mode_idx: int, // which form (index) to check; usually 0
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want_opcode: u8,
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want_length: u8,
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want_cpu: m.CPU,
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) {
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_run := m.ENCODE_RUNS[u16(mn)]
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encs := m.ENCODE_FORMS[_run.start:][:_run.count]
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if len(encs) <= want_mode_idx {
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fmt.printfln(" [FAIL] %-12s no encoding at idx %d", name, want_mode_idx)
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failures += 1
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return
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}
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e := encs[want_mode_idx]
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if e.opcode != want_opcode || e.length != want_length || e.cpu != want_cpu {
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fmt.printfln(" [FAIL] %-12s op=%02x/len=%d/cpu=%v want %02x/%d/%v",
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name, e.opcode, e.length, e.cpu,
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want_opcode, want_length, want_cpu)
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failures += 1
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return
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}
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fmt.printfln(" [ok] %-12s op=%02x len=%d cpu=%v",
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name, e.opcode, e.length, e.cpu)
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passes += 1
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}
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@(private="file")
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check_mode :: proc(name: string, mn: m.Mnemonic, want_mode: m.Operand_Type, want_opcode: u8) {
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// Find the form whose first Operand_Type matches `want_mode`.
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_run := m.ENCODE_RUNS[u16(mn)]
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for e in m.ENCODE_FORMS[_run.start:][:_run.count] {
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if e.ops[0] == want_mode {
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if e.opcode == want_opcode {
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fmt.printfln(" [ok] %-22s op=%02x", name, want_opcode)
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passes += 1
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} else {
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fmt.printfln(" [FAIL] %-22s got op=%02x want %02x", name, e.opcode, want_opcode)
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failures += 1
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}
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return
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}
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}
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fmt.printfln(" [FAIL] %-22s no form with mode %v", name, want_mode)
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failures += 1
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}
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main :: proc() {
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fmt.println("=== MOS 6502 encoding-table spot checks ===")
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// ---- NMOS official core --------------------------------------------------
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check_mode("LDA #imm", .LDA, .IMM_8, 0xA9)
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check_mode("LDA zp", .LDA, .MEM_ZP, 0xA5)
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check_mode("LDA zp,X", .LDA, .MEM_ZP_X, 0xB5)
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check_mode("LDA abs", .LDA, .MEM_ABS, 0xAD)
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check_mode("LDA abs,X", .LDA, .MEM_ABS_X, 0xBD)
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check_mode("LDA abs,Y", .LDA, .MEM_ABS_Y, 0xB9)
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check_mode("LDA (zp,X)", .LDA, .MEM_IND_X, 0xA1)
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check_mode("LDA (zp),Y", .LDA, .MEM_IND_Y, 0xB1)
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check_mode("STA zp", .STA, .MEM_ZP, 0x85)
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check_mode("STA abs", .STA, .MEM_ABS, 0x8D)
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check_mode("ADC #imm", .ADC, .IMM_8, 0x69)
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check_mode("SBC abs,Y", .SBC, .MEM_ABS_Y, 0xF9)
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check_mode("ASL A", .ASL, .A_IMPL, 0x0A)
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check_mode("ROL A", .ROL, .A_IMPL, 0x2A)
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check_mode("BIT zp", .BIT, .MEM_ZP, 0x24)
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check_mode("BIT abs", .BIT, .MEM_ABS, 0x2C)
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check("BNE", .BNE, 0, 0xD0, 2, .NMOS)
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check("BEQ", .BEQ, 0, 0xF0, 2, .NMOS)
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check("BPL", .BPL, 0, 0x10, 2, .NMOS)
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check("BVS", .BVS, 0, 0x70, 2, .NMOS)
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check_mode("JMP abs", .JMP, .MEM_ABS, 0x4C)
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check_mode("JMP (abs)", .JMP, .MEM_IND, 0x6C)
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check("JSR", .JSR, 0, 0x20, 3, .NMOS)
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check("RTS", .RTS, 0, 0x60, 1, .NMOS)
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check("RTI", .RTI, 0, 0x40, 1, .NMOS)
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check("BRK", .BRK, 0, 0x00, 1, .NMOS)
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check("NOP", .NOP, 0, 0xEA, 1, .NMOS)
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check("CLC", .CLC, 0, 0x18, 1, .NMOS)
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check("SEI", .SEI, 0, 0x78, 1, .NMOS)
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check("CLD", .CLD, 0, 0xD8, 1, .NMOS)
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check("TXA", .TXA, 0, 0x8A, 1, .NMOS)
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check("TYA", .TYA, 0, 0x98, 1, .NMOS)
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check("PHA", .PHA, 0, 0x48, 1, .NMOS)
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check("PLA", .PLA, 0, 0x68, 1, .NMOS)
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check("INX", .INX, 0, 0xE8, 1, .NMOS)
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check("INY", .INY, 0, 0xC8, 1, .NMOS)
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check("DEX", .DEX, 0, 0xCA, 1, .NMOS)
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check("DEY", .DEY, 0, 0x88, 1, .NMOS)
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// ---- NMOS undocumented ----------------------------------------------------
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check_mode("LAX zp", .LAX, .MEM_ZP, 0xA7)
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check_mode("LAX abs,Y", .LAX, .MEM_ABS_Y,0xBF)
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check_mode("SAX_NMOS zp", .SAX_NMOS, .MEM_ZP, 0x87)
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check_mode("SAX_NMOS abs", .SAX_NMOS, .MEM_ABS, 0x8F)
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check_mode("DCP abs", .DCP, .MEM_ABS, 0xCF)
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check_mode("ISC abs", .ISC, .MEM_ABS, 0xEF)
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check_mode("RLA abs", .RLA, .MEM_ABS, 0x2F)
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check_mode("RRA abs", .RRA, .MEM_ABS, 0x6F)
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check_mode("SLO abs", .SLO, .MEM_ABS, 0x0F)
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check_mode("SRE abs", .SRE, .MEM_ABS, 0x4F)
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check("ALR", .ALR, 0, 0x4B, 2, .NMOS_UNDOC)
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check("ARR", .ARR, 0, 0x6B, 2, .NMOS_UNDOC)
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check("AXS", .AXS, 0, 0xCB, 2, .NMOS_UNDOC)
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check("USBC", .USBC, 0, 0xEB, 2, .NMOS_UNDOC)
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check("JAM (0x02)",.JAM, 0, 0x02, 1, .NMOS_UNDOC)
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check("ANC ($0B)", .ANC, 0, 0x0B, 2, .NMOS_UNDOC)
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check("ANC ($2B)", .ANC, 1, 0x2B, 2, .NMOS_UNDOC)
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// ---- 65C02 additions ------------------------------------------------------
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check("BRA", .BRA, 0, 0x80, 2, .CMOS_65C02)
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check("INA", .INA, 0, 0x1A, 1, .CMOS_65C02)
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check("DEA", .DEA, 0, 0x3A, 1, .CMOS_65C02)
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check("PHX", .PHX, 0, 0xDA, 1, .CMOS_65C02)
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check("PHY", .PHY, 0, 0x5A, 1, .CMOS_65C02)
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check("PLX", .PLX, 0, 0xFA, 1, .CMOS_65C02)
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check("PLY", .PLY, 0, 0x7A, 1, .CMOS_65C02)
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check_mode("STZ zp", .STZ, .MEM_ZP, 0x64)
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check_mode("STZ abs", .STZ, .MEM_ABS, 0x9C)
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check_mode("LDA (zp)", .LDA, .MEM_IND_ZP, 0xB2)
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check_mode("ADC (zp)", .ADC, .MEM_IND_ZP, 0x72)
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check_mode("JMP (abs,X)", .JMP, .MEM_IND_ABS_X, 0x7C)
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check_mode("TRB zp", .TRB, .MEM_ZP, 0x14)
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check_mode("TSB zp", .TSB, .MEM_ZP, 0x04)
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check_mode("BIT #imm", .BIT, .IMM_8, 0x89)
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// Rockwell bit ops
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check("RMB0", .RMB0, 0, 0x07, 2, .CMOS_65C02)
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check("RMB3", .RMB3, 0, 0x37, 2, .CMOS_65C02)
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check("SMB0", .SMB0, 0, 0x87, 2, .CMOS_65C02)
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check("SMB7", .SMB7, 0, 0xF7, 2, .CMOS_65C02)
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check("BBR0", .BBR0, 0, 0x0F, 3, .CMOS_65C02)
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check("BBR7", .BBR7, 0, 0x7F, 3, .CMOS_65C02)
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check("BBS0", .BBS0, 0, 0x8F, 3, .CMOS_65C02)
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check("BBS7", .BBS7, 0, 0xFF, 3, .CMOS_65C02)
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// ---- HuC6280 --------------------------------------------------------------
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check("SXY", .SXY, 0, 0x02, 1, .HUC6280)
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check("SAX (HuC)",.SAX, 0, 0x22, 1, .HUC6280)
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check("SAY", .SAY, 0, 0x42, 1, .HUC6280)
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check("CLA", .CLA, 0, 0x62, 1, .HUC6280)
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check("CLX", .CLX, 0, 0x82, 1, .HUC6280)
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check("CLY", .CLY, 0, 0xC2, 1, .HUC6280)
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check("CSL", .CSL, 0, 0x54, 1, .HUC6280)
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check("CSH", .CSH, 0, 0xD4, 1, .HUC6280)
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check("ST0", .ST0, 0, 0x03, 2, .HUC6280)
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check("ST1", .ST1, 0, 0x13, 2, .HUC6280)
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check("ST2", .ST2, 0, 0x23, 2, .HUC6280)
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check("TAM", .TAM, 0, 0x53, 2, .HUC6280)
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check("TMA", .TMA, 0, 0x43, 2, .HUC6280)
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check("BSR", .BSR, 0, 0x44, 2, .HUC6280)
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check("TII", .TII, 0, 0x73, 7, .HUC6280)
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check("TDD", .TDD, 0, 0xC3, 7, .HUC6280)
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check("TIN", .TIN, 0, 0xD3, 7, .HUC6280)
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check("TIA", .TIA, 0, 0xE3, 7, .HUC6280)
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check("TAI", .TAI, 0, 0xF3, 7, .HUC6280)
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check_mode("TST # zp", .TST, .IMM_8, 0x83)
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fmt.println()
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fmt.printfln("==> table: %d passed, %d failed", passes, failures)
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if failures > 0 { os.exit(1) }
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run_pipeline_tests()
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}
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