mirror of
https://github.com/odin-lang/Odin.git
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47fc72e0ba
Every mnemonic with an encode form now has a generated inst_<mnem>/emit_<mnem> overload group. The per-arch generators map ALL operand types — nothing is skipped: arm64 gains shifted/extended registers (multi-param via op_shifted/op_extended), SVE Z-regs + predicates, SME tile/slice, NEON arrangements/lanes, bitmask/sysreg/pattern immediates and condition codes (427 -> 777 mnemonics); arm32 gains shifted/register-shifted regs, register lists, NEON lanes and all encoded-immediate subclasses (479 -> 592); x86 gains m80 and descriptor-table memory operands — FBLD/FBSTP, LGDT/SGDT/LIDT/SIDT, FLD/FSTP, far-indirect JMP/CALL, BOUND (1167 -> 1175). Mnemonic-specific builders are now fully generated, not hand-written: deleted the hand-written helpers the generated groups collided with — riscv inst_jal/inst_jalr, arm64 inst_b_cond/inst_cbz/inst_tbz/inst_csel, mos6502 inst_tst — and let the generators own those names (arm64 also gains inst_cbnz/tbnz/csinc/csinv/csneg). Updated the affected test call-sites. The generic operand-shape helpers (inst_r_r, inst_r_r_i, inst_ldst, ...) remain as delegation targets. Decode-only mnemonics with no encode form are correctly left without builders. ppc/ppc_vle/rsp/mos65816 were already complete. All 10 ISAs: structure + compile + tests pass; generators idempotent.
107 lines
4.2 KiB
Odin
107 lines
4.2 KiB
Odin
// rexcode · Brendan Punsky (dotbmp@github), original author
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package rexcode_arm64
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// =============================================================================
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// INSTRUCTION
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// =============================================================================
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Instruction_Flags :: bit_field u8 {
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_: u8 | 8,
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}
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Instruction :: struct #packed {
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ops: [4]Operand `fmt:"v,operand_count"`, // 4 * size_of(Operand)
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mnemonic: Mnemonic, // 2
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operand_count: u8, // 1
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flags: Instruction_Flags, // 1
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length: u8, // 1 -- always 4
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}
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#assert(size_of(Instruction) == 77)
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// =============================================================================
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// Builders -- the most common shapes; less-common forms can be built
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// inline by the caller using the Instruction struct directly.
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// =============================================================================
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@(require_results)
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inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 0, length = 4}
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}
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// Single-register (e.g. BR, BLR).
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@(require_results)
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inst_r :: #force_inline proc "contextless" (m: Mnemonic, r: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 4,
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ops = {op_reg(r), {}, {}, {}}}
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}
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// 2-register (e.g. CLZ, RBIT).
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@(require_results)
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inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rd), op_reg(rn), {}, {}}}
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}
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// 3-register (e.g. ADD shifted, MUL, UDIV, ASRV).
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@(require_results)
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inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_reg(rn), op_reg(rm), {}}}
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}
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// 4-register R4-type (MADD, MSUB, SMADDL, ...).
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@(require_results)
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inst_r_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm, ra: Register) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 4, length = 4,
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ops = {op_reg(rd), op_reg(rn), op_reg(rm), op_reg(ra)}}
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}
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// 2-register + immediate (e.g. ADD imm).
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@(require_results)
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inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd, rn: Register, imm: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_reg(rn), op_imm(imm), {}}}
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}
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// 1-register + immediate (e.g. MOVZ).
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@(require_results)
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inst_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, imm: i64) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rd), op_imm(imm), {}, {}}}
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}
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// MOVZ/MOVN/MOVK with explicit hw shift (0/16/32/48).
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@(require_results)
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inst_mov_imm :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, imm: i64, hw: u8) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rd), op_imm(imm), op_imm(i64(hw), 1), {}}}
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}
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// Load/store register: Rt + memory.
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@(require_results)
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inst_ldst :: #force_inline proc "contextless" (m: Mnemonic, rt: Register, mm: Memory) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 2, length = 4,
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ops = {op_reg(rt), op_mem(mm), {}, {}}}
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}
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// Load/store pair: Rt, Rt2, memory.
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@(require_results)
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inst_ldp_stp :: #force_inline proc "contextless" (m: Mnemonic, rt, rt2: Register, mm: Memory) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 3, length = 4,
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ops = {op_reg(rt), op_reg(rt2), op_mem(mm), {}}}
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}
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// PC-relative branch (B, BL).
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@(require_results)
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inst_branch :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32) -> Instruction {
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return Instruction{mnemonic = m, operand_count = 1, length = 4,
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ops = {op_label(label_id, 4), {}, {}, {}}}
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}
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// NOTE: inst_b_cond / inst_cbz (+cbnz) / inst_tbz (+tbnz) /
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// inst_csel (+csinc/csinv/csneg) are now generated per-mnemonic in
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// mnemonic_builders.odin (e.g. inst_cbz(rt, label), inst_cbnz(rt, label),
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// inst_csinc(rd, rn, rm, cond)). They are no longer hand-written here so the
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// generator can own those names for full mnemonic coverage.
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