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6fd233f041
New arm32 specgen (llvm-mc --triple=armv8a --mattr=+neon as the bits oracle, empirical masks): VADDL/VSUBL/VABAL/VABDL (Qd,Dn,Dm) and VADDW/VSUBW (Qd,Qn,Dm) across s/u 8/16/32; the compare aliases VCLE/VCLT (= VCGE/VCGT with Vn/Vm swapped) and VACLE/VACLT (= VACGE/VACGT swapped, f32); and VQRSHL shift-by-vector. 84 forms over 11 mnemonics. Built-in llvm round-trip verify passes; spot-checked byte-exact with distinct Q/D registers; 600 tests green.
147 lines
6.8 KiB
Lua
147 lines
6.8 KiB
Lua
#!/usr/bin/env luajit
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-- rexcode · Brendan Punsky (dotbmp@github), original author
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--
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-- Encode-form spec generator (arm32 / A32 NEON). Expands compact per-family
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-- specs into ENCODING_TABLE entries, deriving `bits` from llvm-mc (the oracle)
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-- and `mask` empirically: assemble each form all-zero, then one variant per
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-- operand field at its max register, and mask = ~(union of the deltas). The
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-- data-type suffix (.s8/.u16/.f32/...) selects the U and size bits, so each
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-- type is assembled separately and llvm produces the right `bits`.
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--
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-- Output replaces the SPECGEN:BEGIN..SPECGEN:END region of encoding_table.odin
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-- in place; the hand-written core is untouched.
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--
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-- Run: luajit tablegen/specgen.lua (from arm32/, or with a full path)
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local bit = require("bit")
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local LLVM = "llvm-mc --assemble --triple=armv8a --mattr=+neon,+fullfp16 --show-encoding"
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local DIR = (arg[0]:match("^(.*)/[^/]*$")) or "."
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local TABLE = DIR .. "/encoding_table.odin"
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local function word(line)
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local p = io.popen(string.format("printf '%%s\\n' '%s' | %s 2>/dev/null", line, LLVM))
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local out = p:read("*a"); p:close()
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local b1,b2,b3,b4 = out:match("0x(%x%x),0x(%x%x),0x(%x%x),0x(%x%x)")
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if not b1 then return nil end
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return tonumber(b4..b3..b2..b1, 16)
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end
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local function mask_of(base, variants)
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local x = 0
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for _, w in ipairs(variants) do x = bit.bor(x, bit.bxor(base, w)) end
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return bit.band(bit.bnot(x), 0xFFFFFFFF)
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end
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local sections, skips, n_forms, n_mnem = {}, {}, 0, 0
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-- Emit a mnemonic block. `forms` is a list of {ops, enc, feat, asm, maxes}:
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-- ops/enc prebuilt "{.A, .B, .C, .NONE}" text
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-- asm function(vals) -> asm string (vals[i] = register number for field i)
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-- maxes list of per-field max register numbers (D up to 31, Q up to 15)
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local function block(mnem, forms)
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local rows = {}
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for _, f in ipairs(forms) do
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local zero = {}; for i=1,#f.maxes do zero[i]=0 end
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local b0 = word(f.asm(zero))
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if b0 then
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local vs, ok = {}, true
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for i=1,#f.maxes do
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local v={}; for j=1,#f.maxes do v[j]=0 end; v[i]=f.maxes[i]
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local w=word(f.asm(v)); if w then vs[#vs+1]=w else ok=false end
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end
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if ok then
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rows[#rows+1]=string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .%s, .A32, {cond_in_28=false}},",
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mnem, f.ops, f.enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), f.feat or "NEON")
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n_forms=n_forms+1
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else skips[#skips+1]=mnem end
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else skips[#skips+1]=mnem end
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end
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if #rows>0 then sections[#sections+1]=string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows,"\n")); n_mnem=n_mnem+1 end
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end
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local INT_TYPES = {"s8","s16","s32","u8","u16","u32"}
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local SHIFT_TYPES = {"s8","s16","s32","s64","u8","u16","u32","u64"}
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-- Build the forms for a family across a type list, given a shape descriptor.
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-- shape.ops/enc are text; shape.asm(t, v) builds asm for type t and regs v;
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-- shape.maxes is the per-field max list.
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local function family(mnem, llvm, types, shape)
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local forms = {}
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for _, t in ipairs(types) do
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forms[#forms+1] = {
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ops = shape.ops, enc = shape.enc, feat = shape.feat,
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maxes = shape.maxes,
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asm = function(v) return shape.asm(llvm, t, v) end,
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}
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end
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block(mnem, forms)
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end
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-- ---- Three-register long: Qd, Dn, Dm ---------------------------------------
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local LONG = {
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ops = "{.QPR, .DPR, .DPR, .NONE}", enc = "{.VD_Q, .VN_D, .VM_D, .NONE}", maxes = {15,31,31},
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asm = function(op,t,v) return string.format("%s.%s q%d, d%d, d%d", op, t, v[1], v[2], v[3]) end,
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}
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-- ---- Three-register wide: Qd, Qn, Dm ---------------------------------------
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local WIDE = {
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ops = "{.QPR, .QPR, .DPR, .NONE}", enc = "{.VD_Q, .VN_Q, .VM_D, .NONE}", maxes = {15,15,31},
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asm = function(op,t,v) return string.format("%s.%s q%d, q%d, d%d", op, t, v[1], v[2], v[3]) end,
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}
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family("VADDL","vaddl",INT_TYPES,LONG); family("VSUBL","vsubl",INT_TYPES,LONG)
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family("VABAL","vabal",INT_TYPES,LONG); family("VABDL","vabdl",INT_TYPES,LONG)
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family("VADDW","vaddw",INT_TYPES,WIDE); family("VSUBW","vsubw",INT_TYPES,WIDE)
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-- ---- Compare aliases (VCLE/VCLT = VCGE/VCGT with Vn/Vm swapped) -------------
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-- Dd, Dn, Dm == VCGE Dd, Dm, Dn -> enc swaps to {VD, VM, VN}.
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local CMP_D = {
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ops = "{.DPR, .DPR, .DPR, .NONE}", enc = "{.VD_D, .VM_D, .VN_D, .NONE}", maxes = {31,31,31},
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asm = function(op,t,v) return string.format("%s.%s d%d, d%d, d%d", op, t, v[1], v[2], v[3]) end,
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}
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local CMP_Q = {
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ops = "{.QPR, .QPR, .QPR, .NONE}", enc = "{.VD_Q, .VM_Q, .VN_Q, .NONE}", maxes = {15,15,15},
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asm = function(op,t,v) return string.format("%s.%s q%d, q%d, q%d", op, t, v[1], v[2], v[3]) end,
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}
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local CMP_TYPES = {"s8","s16","s32","u8","u16","u32","f32"}
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for _, it in ipairs({{"VCLE","vcle"},{"VCLT","vclt"}}) do
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local forms = {}
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for _, t in ipairs(CMP_TYPES) do
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forms[#forms+1] = {ops=CMP_D.ops, enc=CMP_D.enc, maxes=CMP_D.maxes, asm=function(v) return CMP_D.asm(it[2],t,v) end}
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forms[#forms+1] = {ops=CMP_Q.ops, enc=CMP_Q.enc, maxes=CMP_Q.maxes, asm=function(v) return CMP_Q.asm(it[2],t,v) end}
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end
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block(it[1], forms)
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end
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-- absolute compare (f32 only)
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for _, it in ipairs({{"VACLE","vacle"},{"VACLT","vaclt"}}) do
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block(it[1], {
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{ops=CMP_D.ops, enc=CMP_D.enc, maxes=CMP_D.maxes, asm=function(v) return CMP_D.asm(it[2],"f32",v) end},
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{ops=CMP_Q.ops, enc=CMP_Q.enc, maxes=CMP_Q.maxes, asm=function(v) return CMP_Q.asm(it[2],"f32",v) end},
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})
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end
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-- ---- Shift by vector (VRSHL/VQRSHL): Dd, Dm, Dn (value, shift) --------------
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-- asm Dm -> Vm, asm Dn -> Vn -> enc {VD, VM, VN}.
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local SHL_D = {
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ops = "{.DPR, .DPR, .DPR, .NONE}", enc = "{.VD_D, .VM_D, .VN_D, .NONE}", maxes = {31,31,31},
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asm = function(op,t,v) return string.format("%s.%s d%d, d%d, d%d", op, t, v[1], v[2], v[3]) end,
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}
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local SHL_Q = {
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ops = "{.QPR, .QPR, .QPR, .NONE}", enc = "{.VD_Q, .VM_Q, .VN_Q, .NONE}", maxes = {15,15,15},
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asm = function(op,t,v) return string.format("%s.%s q%d, q%d, q%d", op, t, v[1], v[2], v[3]) end,
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}
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for _, it in ipairs({{"VQRSHL","vqrshl"}}) do
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local forms = {}
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for _, t in ipairs(SHIFT_TYPES) do
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forms[#forms+1] = {ops=SHL_D.ops, enc=SHL_D.enc, maxes=SHL_D.maxes, asm=function(v) return SHL_D.asm(it[2],t,v) end}
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forms[#forms+1] = {ops=SHL_Q.ops, enc=SHL_Q.enc, maxes=SHL_Q.maxes, asm=function(v) return SHL_Q.asm(it[2],t,v) end}
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end
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block(it[1], forms)
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end
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-- ---- splice into the SoT ---------------------------------------------------
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local region = "\t// SPECGEN:BEGIN\n" .. table.concat(sections, "\n") .. "\n\t// SPECGEN:END"
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local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close()
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local new, n = src:gsub("\t// SPECGEN:BEGIN.-\t// SPECGEN:END", (region:gsub("%%", "%%%%")))
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if n ~= 1 then io.stderr:write("FATAL: expected one SPECGEN region, found "..n.."\n"); os.exit(1) end
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local wh = assert(io.open(TABLE, "w")); wh:write(new); wh:close()
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io.write(string.format("specgen(arm32): wrote %d mnemonics / %d forms\n", n_mnem, n_forms))
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if #skips > 0 then io.write(" skipped "..#skips.." form(s)\n") end
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